Interconnects Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters ECE 261 Krish Chakrabarty 1 Introduction Chips are mostly made of ires called interconnect In stick diagram, ires set size Transistors are little things under the ires Many layers of ires Wires are as important as transistors Speed Poer Noise Alternating layers run orthogonally ECE 261 Krish Chakrabarty 2
Wire Geometry Pitch = + s Aspect ratio: AR = t/ Old processes had AR << 1 Modern processes have AR 2 Pack in many skinny ires l s t h ECE 261 Krish Chakrabarty 3 Layer Stack AMI 0.6 µm process has 3 metal layers Modern processes use 6-10+ metal layers Example: Intel 180 nm process M1: thin, narro (< 3λ) High density cells M2-M4: thicker For longer ires M5-M6: thickest For V DD, GND, clk Layer T (nm) W (nm) S (nm) AR 6 1720 860 860 2.0 1000 5 1600 800 800 2.0 1000 4 1080 540 540 2.0 700 3 700 320 320 2.2 700 2 700 320 320 2.2 700 1 480 250 250 1.9 800 Substrate ECE 261 Krish Chakrabarty 4
Wire Resistance ρ= resistivity (Ω*m) ρ l l R = = R t R = sheet resistance (Ω/ ) is a dimensionless unit(!) Count number of squares R = R * (# of squares) t l t l l 1 Rectangular Block R = R (L/W) Ω 4 Rectangular Blocks R = R (2L/2W) Ω = R (L/W) Ω ECE 261 Krish Chakrabarty 5 Choice of Metals Until 180 nm generation, most ires ere aluminum Modern processes often use copper Cu atoms diffuse into silicon and damage FETs Must be surrounded by a diffusion barrier Metal Silver (Ag) Copper (Cu) Gold (Au) Aluminum (Al) Tungsten (W) Molybdenum (Mo) Bulk resistivity (µω*cm) 1.6 1.7 2.2 2.8 5.3 5.3 ECE 261 Krish Chakrabarty 6
Sheet Resistance Typical sheet resistances in 180 nm process Layer Diffusion (silicided) Diffusion (no silicide) Polysilicon (silicided) Polysilicon (no silicide) Metal1 Metal2 Metal3 Metal4 Metal5 Metal6 Sheet Resistance (Ω/ ) 3-10 50-200 3-10 50-400 0.08 0.05 0.05 0.03 0.02 0.02 ECE 261 Krish Chakrabarty 7 Contacts Resistance Contacts and vias also have 2-20 Ω Use many contacts for loer R Many small contacts for current croding around periphery ECE 261 Krish Chakrabarty 8
Wire Capacitance Wire has capacitance per unit length To neighbors To layers above and belo C total = C top + C bot + 2C adj s layer n+1 h 2 t h 1 C top C bot C adj layer n layer n-1 ECE 261 Krish Chakrabarty 9 Capacitance Trends Parallel plate equation: C = εa/d Wires are not parallel plates, but obey trends Increasing area (W, t) increases capacitance Increasing distance (s, h) decreases capacitance Dielectric constant ε = kε 0 ε 0 = 8.85 x 10-14 F/cm k = 3.9 for SiO 2 Processes are starting to use lo-k dielectrics k 3 (or less) as dielectrics use air pockets Typical (M2) ires have ~ 0.2 ff/µm Compare to 2 ff/µm for gate capacitance ECE 261 Krish Chakrabarty 10
Diffusion & Polysilicon Diffusion capacitance is very high (about 2 ff/µm) Comparable to gate capacitance Diffusion also has high resistance Avoid using diffusion runners for ires! Polysilicon has loer C but high R Use for transistor gates Occasionally for very short ires beteen gates ECE 261 Krish Chakrabarty 11 Lumped Element Models Wires are a distributed system Approximate ith lumped element models R R/N R/N N segments R/N R/N C C/N C/N C/N C/N R R R/2 R/2 C L-model C/2 C/2 π-model C T-model 3-segment π-model is accurate to 3% in simulation L-model needs 100 segments for same accuracy! Use single segment π-model for Elmore delay ECE 261 Krish Chakrabarty 12
Example Metal2 ire in 180 nm process 5 mm long 0.32 µm ide Number of squares = 5000/0.32 = 15625 Construct a 3-segment π-model R = 0.05 Ω/ => R = 15625 * 0.05 = 781 Ω C permicron = 0.2 ff/µm => C = 0.2 ff/µm * 5000 µm = 1 pf 260 Ω 167 ff 167 ff 260 Ω 167 ff 167 ff 260 Ω 167 ff 167 ff ECE 261 Krish Chakrabarty 13 Wire RC Delay Estimate the delay of a 10x inverter driving a 2x inverter at the end of the 5mm ire from the previous example. R = 2.5 kω*µm for gates Unit inverter: 0.36 µm nmos, 0.72 µm pmos Unit inverter has 4λ = 0.36µm ide nmos, 8λ = 0.72µm ide pmos Unit inverter: effective resistance of (2.5 kω*µm)/(0.36µm) = 6.9 kω Capacitance: (0.36µm + 0.72 µm) * (2fF/µm) = 2fF 781 Ω 690 Ω 500 ff 500 ff 4 ff t pd = 1.1 ns Driver Wire Load ECE 261 Krish Chakrabarty 14
Crosstalk A capacitor does not like to change its voltage instantaneously. A ire has high capacitance to its neighbor. When the neighbor sitches from 1-> 0 or 0->1, the ire tends to sitch too. Called capacitive coupling or crosstalk. Crosstalk effects Noise on non-sitching ires Increased delay on sitching ires ECE 261 Krish Chakrabarty 15 Crosstalk Delay Assume layers above and belo on average are quiet Second terminal of capacitor can be ignored Model as C gnd = C top + C bot Effective C adj depends on behavior of neighbors Miller effect A B C Cgnd adj C gnd B Constant Sitching ith A Sitching opposite A V V DD 0 2V DD C eff(a) C gnd + C adj C gnd C gnd + 2 C adj MCF 1 0 2 ECE 261 Krish Chakrabarty 16
Crosstalk Noise Crosstalk causes noise on non-sitching ires If victim is floating: model as capacitive voltage divider Cadj Vvictim = V C + C gnd v adj aggressor Aggressor V aggressor Victim C adj C gnd-v V victim ECE 261 Krish Chakrabarty 17 Coupling Waveforms Simulated coupling for C adj = C victim 1.8 Aggressor 1.5 1.2 0.9 Victim (undriven): 50% 0.6 0.3 Victim (half size driver): 16% Victim (equal size driver): 8% Victim (double size driver): 4% 0 0 200 400 600 800 1000 1200 1400 1800 2000 t (ps) ECE 261 Krish Chakrabarty 18
Noise Implications So hat if e have noise? If the noise is less than the noise margin, nothing happens Static CMOS logic ill eventually settle to correct output even if disturbed by large noise spikes But glitches cause extra delay Also cause extra poer from false transitions Dynamic logic never recovers from glitches Memories and other sensitive circuits also can produce the rong anser ECE 261 Krish Chakrabarty 19 Wire Engineering Goal: achieve delay, area, poer goals ith acceptable noise Degrees of freedom: 2.0 0.8 1.8 0.7 Width 1.6 0.6 1.4 0.5 1.2 Spacing 1.0 0.4 0.8 0.3 Layer 0.6 0.2 0.4 0.1 0.2 Shielding Delay (ns): RC/2 0 0 500 1000 1500 2000 Pitch (nm) Coupling: 2C adj / (2C adj +C gnd ) 0 0 500 1000 1500 2000 Pitch (nm) Wire Spacing (nm) 320 480 640 vdd a 0 a 1 gnd a 2 a 3 vdd vdd a 0 gnd a 1 vdd a 2 gnd a 0 b 0 a 1 b 1 a 2 b 2 ECE 261 Krish Chakrabarty 20
Repeaters R and C are proportional to l RC delay is proportional to l 2 Unacceptably great for long ires ECE 261 Krish Chakrabarty 21 Repeaters R and C are proportional to l RC delay is proportional to l 2 Unacceptably great for long ires Break long ires into N shorter segments Drive each one ith an inverter or buffer Wire Length: l Driver Receiver l/n N Segments Segment l/n l/n Driver Repeater Repeater Repeater Receiver ECE 261 Krish Chakrabarty 22
Repeater Design Ho many repeaters should e use? Ho large should each one be? Equivalent circuit Wire length l Wire Capacitance C *l, Resistance R *l Inverter idth W (nmos = W, pmos = 2W) Gate Capacitance C *W, Resistance R/W.. ECE 261 Krish Chakrabarty 23 Repeater Results Write equation for Elmore Delay Differentiate ith respect to W and N Set equal to 0, solve l = N t pd l W = 2RC R C ( 2 2) = + RC R C RC R C ~60-80 ps/mm in 180 nm process ECE 261 Krish Chakrabarty 24