Lecture 400 DiscreteTime omparators (4/8/02) Page 4001 LETURE 400 DISRETETIME OMPARATORS (LATHES) (READING: AH 475483) Objective The objective of this presentation is: 1.) Illustrate discretetime comparators 2.) Estimate the propagation delay time Outline Switched capacitor comparators Regenerative comparators (latches) Summary EE 6412 Analog Integrated ircuit Design II P.E. Allen 2002 Lecture 400 DiscreteTime omparators (4/8/02) Page 4002 Switched apacitor omparator V 1 V 2 φ 2 V p V OS A V out V 2 V 1 V OS V OS p V OS A V out A switched capacitor comparator Equivalent circuit when the φ 2 switches are closed Fig. 8.51 Phase: The V 1 input is sampled and the dc input offset voltage is autozeroed. V ( ) = V 1 V OS and V p ( ) = V OS φ 2 Phase: V 2 V out (φ 2 ) =A p (V 1V OS ) p V OS p p AV OS p = A (V 2 V 1 ) V p OS p AV p OS = A(V 2 V 1 ) A(V p 1 V 2 ) if p is smaller than. EE 6412 Analog Integrated ircuit Design II P.E. Allen 2002
Lecture 400 DiscreteTime omparators (4/8/02) Page 4003 DifferentialIn, DifferentialOut Switched apacitor omparator φ 2 v in v out φ 2 omments: Reduces the influence of charge injection Eliminates even harmonics Fig. 8.52 EE 6412 Analog Integrated ircuit Design II P.E. Allen 2002 Lecture 400 DiscreteTime omparators (4/8/02) Page 4004 Regenerative omparators Regenerative comparators use positive feedback to accomplish the comparison of two signals. Latches have a faster switching speed that the previous bistable comparators. NMOS and PMOS latch: I 1 I 2 M2 v o1 vo2 v o1 vo2 M2 I 1 I 2 NMOS latch PMOS latch How is the input applied to a latch? The inputs are initially applied to the outputs of the latch. V o1 = initial input applied to v o1 V o2 = initial input applied to v o2 Fig. 8.53 EE 6412 Analog Integrated ircuit Design II P.E. Allen 2002
Lecture 400 DiscreteTime omparators (4/8/02) Page 4005 Step Response of a Latch ircuit: I 1 I 2 v o2 R i and i are the 1 resistance and capacitance v o1 Vo2 V o1 seen to ground from the i V M2 g o1 ' m1v o2 R 1 s th transistor. Nodal equations: g m1 V o2 G 1 V o1 s 1 V o1 V o1 s = g m1 V o2 G 1 V o1 s 1 V o1 1 V o1 = 0 g m2 V o1 G 2 V o2 s 2 V o2 V o2 s = g m2 V o1 G 2 V o2 s 2 V o2 2 V o2 = 0 Solving for V o1 and V o2 gives, R 1 1 V o1 = sr 1 1 1 V o1 g m1r 1 sr 1 1 1 V τ 1 o2 = sτ 1 1 V o1 g m1r 1 sτ 1 1 V o2 R 2 2 V o2 = sr 2 2 1 V o2 g m2r 2 sr 2 2 1 V τ 2 o1 = sτ 2 1 V o2 g m2r 2 sτ 2 1 V o1 Defining the output, V o, and input, V i, as V o = V o2 V o1 and V i = V o2 V o1 g m2 V o1 2 R 2 V o2 ' s V o2 Fig. 8.54 EE 6412 Analog Integrated ircuit Design II P.E. Allen 2002 Lecture 400 DiscreteTime omparators (4/8/02) Page 4006 Step Response of the Latch ontinued Solving for V o gives, τ V o = V o2 V o1 = sτ1 V i g mr sτ1 V o or τ V i τ V i V o = sτ(1g m R) = 1g m R τ V i sτ = 1g m R 1 sτ 1 where τ τ = 1g m R Taking the inverse Laplace transform gives v o (t) = V i e t/τ = V i e t(1g mr) /τ e g mrt/τ V i, if g m R >>1. Define the latch time constant as τ τ L g m R = g m = 0.67WL ox 2K (W/L)I = 0.67 ox if gs. V out (t) = e t/τ L V i WL 3 2K I EE 6412 Analog Integrated ircuit Design II P.E. Allen 2002
Lecture 400 DiscreteTime omparators (4/8/02) Page 4007 Step Response of a Latch ontinued Normalize the output voltage by (V OH V OL ) to get V out (t) V i V OH V OL = e t/τ L V OH V OL which is plotted as, 1 0.5 0.4 0.3 0.8 0.2 0.1 V i V 0.05 OH V OL 0.6 V out 0.03 V OH V OL 0.01 0.4 0.005 V OH V OL The propagation delay time is t p = τ L ln 2 V i 0.2 0 0 1 2 t 3 4 5 τ L Fig. 8.55 EE 6412 Analog Integrated ircuit Design II P.E. Allen 2002 Lecture 400 DiscreteTime omparators (4/8/02) Page 4008 Example 8.51 Time domain characteristics of a latch. Find the time it takes from the time the latch is enabled until the output voltage, V out, equals V OH V OL if the W/L of the latch NMOS transistors is 10µm/1µm and the latch dc current is 10µA when V i = 0.1(V OH V OL ) and V i = 0.01(V OH V OL ). Find the propagation time delay ( V out =0.5(V OH V OL )) for the latch for each of these conditions. Solution The transconductance of the latch transistors is g m = 2 110 10 10 = 148µS The output conductance is 0.4µS which gives g m R of 59.2V/V. Since g m R is greater than 1, we can use the above results. Therefore the latch time constant is found as τ L = 0.67 ox WL 3 2K I = 0.67(24x10 4) (10 1)x10 18 2 110x106 10x106 = 108ns If we assume that the propagation time delay is the time for the output to reach (V OH V OL ), then for V i = 0.01(V OH V OL ) that t p = 4.602τ L = 497ns and for V i = 0.1(V OH V OL ) that t p = 2.306τ L = 249ns. If we assume that the propagation time delay is the time when the output is 0.5(V OH V OL ), then using the above results or Fig. 8.55 we find for V i = 0.01(V OH V OL ) that t p = 3.91τ L = 422ns and for V i = 0.1(V OH V OL ) that t p = 1.61τ L = 174ns. EE 6412 Analog Integrated ircuit Design II P.E. Allen 2002
Lecture 400 DiscreteTime omparators (4/8/02) Page 4009 omparator using a Latch with a BuiltIn Threshold How does it operate? 1.) Devices in shaded region operate in the M7 triode region. Latch M9 2.) When the latch/reset goes high, the upper /Reset crosscoupled inverterlatch regenerates. The drain currents of M5 and M6 are steered to M5 obtain a final state determined by the mismatch between the R 1 and R 2 resistances. M3 M2 1 W 1 R 1 = K N L (v in V T ) W 2 L (V REF V T ) V REF and 1 W 1 R = K 2 N L (v in V T ) W 2 L (V REF V T ) 3.) The input voltage which causes R 1 and R 2 to be equal is given by v in (threshold) = (W 2 /W 1 )V REF W 2 /W 1 = 1/4 generates a threshold of ±0.25V REF. Performance 20Ms/s & 200µW M8 M6 0 Latch /Reset v out v out M4 R 1 R 2 M2 v in v in V REF φ1 Fig. 8.56 T.B. ho and P.R. Gray, A 10b, 20Msamples/s, 35mW pipeline A/D onverter, IEEE J. SolidState ircuits, vol. 30, no. 3, pp. 166172, March 1995. EE 6412 Analog Integrated ircuit Design II P.E. Allen 2002 Lecture 400 DiscreteTime omparators (4/8/02) Page 40010 Simple, Low Power Latched omparator M9 M7 M8 0 M5 M6 φ1 M3 v out v out M4 v in M2 v in Dissipated 50µW when clocked at 2MHz. Fig. 8.57 A. oban, 1.5V, 1mW, 98dB DeltaSigma AD, Ph.D. dissertation, School of EE, Georgia Tech, Atlanta, GA 303320250. EE 6412 Analog Integrated ircuit Design II P.E. Allen 2002
Lecture 400 DiscreteTime omparators (4/8/02) Page 40011 Dynamic Latch ircuit: φ Latch M6 M8 V REF M3 M4 v out voutv in M7 M2 φ Latch M5 Input offset voltage distribution: Fig. 8.58 Number of Samples 20 10 0 15 ;;;;; σ = 5.65 Power dissipation/sampling rate = 4.3µW/Ms/s L = 1.2µm (0.6µm Process) 10 5 0 5 10 15 Input offset voltage (mv) Fig. 8.59 EE 6412 Analog Integrated ircuit Design II P.E. Allen 2002 Lecture 400 DiscreteTime omparators (4/8/02) Page 40012 SUMMARY Discretetime comparators must work with clocks Switched capacitor comparators use op amps to transfer charge and autozero Regenerative comparators (latches) use positive feedback The propagation delay of the regenerative comparator is slow at the beginning and speeds up rapidly as time increases The highest speed comparators will use a combination of openloop comparators and latches EE 6412 Analog Integrated ircuit Design II P.E. Allen 2002