18k x 16 HIGH SPEED ASYN CHRON OUS CMOS STATIC RAM Ex tended Tem per a ture TTS18WV16 FEATURES -High-speed access time: 0,5,35,45ns -Low Active Power: 55mW (typical) -Low stand-by power: 1 W (typical) CMOS standby -Single power supply -V dd 3.3V.5% -Fully static operation:no clock or refresh required -Three state outputs -Data Control for upper and lower bytes -Military and Extended temperature support Description The TTS18WV16 is an high-speed,,097,15-bit static RAMs organized as 131,07 words by 16 bits. Its fabricated using high performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The TTS18WV16 is packaged in the JEDEC standard 44-pin Ceramic LCC. UB OE A7 A6 A5 A4 A3 A A1 A0 CE LB I/O15 I/O14 I/O13 I/O1 GND V DD I/O11 I/O10 I/O9 I/O8 I/O0 I/O1 I/O I/O3 V DD GND I/O4 I/O5 I/O6 I/O7 WE NC A8 A9 A10 A11 NC A1 A13 A14 A15 A16 Func tion Block Di a gram 44 Pin LCC Con fig u ra tion 1
TT Semiconductor Ex tended Tem per a ture TTS18WV16 DC OPERATING CONDITIONS V DD =3.3V 5% Pa ram e ter Sym bol Con di tions Min. Max. Units Out put HIGH Volt age V OH V DD = Min, I OH = -4.0mA.4 V Out put LOW Volt age V OL V DD = Min, I OH = 8.0mA 0.4 V In put HIGH Volt age V IH V DD + 0.3 V In put LOW Volt age 1 V IL -0.3 0.8 V In put Leak age I IL GND V IN V DD - A Out put Leak age I LO GND V OUT V DD, Out puts Dis abled - A ABSOLUTE MAXIMUM RATINGS Pa ram e ter Sym bol Min. Units Ter mi nal Volt age with Re spect to GND V TERM -0.5 to V DD + 0.5 V VDD Re lates to GND V DD -.9 to 3.9 V Stor age Tem per a ture T STG -65 to +0 C Power Dis si pa tion P T 0.5 W INPUT/OUTPUT CAPACITANCE (T A = 5 C, f = 1 MHz, V DD = 3.3V) Pa ram e ter Sym bol Con di tions Max. Units In put Ca pac i tance C IN V IN =0V 6 pf In put/out put Ca pac i tance C I/O V OUT =0V 8 pf 1. V IL (min) = -0.3V DC; V IL (min) = -.0V AC (pulse width < 10 ns). Not 100% tested. Up to 15 C
TTS18WV16 Ex tended Tem per a ture TT Semiconductor TRUTH TABLE Mode WE CE OE LB UB I/O0-I/07 I/O8-I/O15 VDD Cur rent Not Se lected (Power-down) X H X X X High-Z High-Z I SB1, I SB Out put Dis abled H L H X X High-Z High-Z I CC X L X H H High-Z High-Z Read H L L L H D OUT D OUT I CC H L L H L High-Z D OUT H L L L L D OUT D OUT Write L L X L H D IN High-Z I CC L L X H L High-Z D IN L L X L L D IN D IN OPERATING RANGE (V DD ) (T A = 5 C, f = 1 MHz, V DD = 3.3V) Range Mil i tary Ex tended Temp High est Temp Am bi ent Tem per a -ture -55 C to +15 C -55 C to +175 C -40 C to +15 C POWER SUPPLY CHARACTERISTICS 1-0 -5-35 -45 Pa ram e ter Sym bol Con di tions Min Max Min Max Min Max Min Max Units V DD Dy namic Op er at ing I CC V DD = Max Mil 50 40 35 30 ma Sup ply Cur rent I OUT = 0 ma, f = f MAX ET 100 80 70 60 CE =V IL HT 130 10 110 100 V IN V DD - 0.3V or typ 18 V IN 0.4V Op er at ing Sup ply Cur rent I CC1 V DD = Max Mil 4 4 4 4 ma I OUT = 0 ma, f = 0 ET 4 4 4 4 HT 4 4 4 4 CMOS Standby Cur rent I SB V DD = Max Mil 100 75 75 75 ma CE V DD - 0.V ET 00 150 150 150 V IN V DD - 0.V or HT 50 190 190 190 V IN 0.V, f = 0 Typ 4 1. At f=f MAX, address and data inputs are cycling at the maximum frequency, f= 0 means no input lines change. Typical values are measured at V DD = 3.0V, T A = 5 C and not 100% tested. 3
TT Semiconductor Ex tended Tem per a ture TTS18WV16 AC TEST CONDITIONS Pa ram e ter Unit 3.3V 5% In put Pulse Level 0.4V to V DD -0.3V In put Rise and Fall Times 1V/ns In put and Out put Tim ing VDD/+0.05V and Ref er ence Level (V REF ) Out put Load See Fig ures 1 and R1 ( ) 317 R ( ) 351 V TM 3.3V READ CYCLE SWITCHING CHARACTERISTICS 1-0 -5-35 -45 Pa ram e ter Sym bol Min Max Min Max Min Max Min Max Units Read Cy cle Time t RC 0 5 35 45 ns Ad dress Ac cess Time t AA 0 5 35 45 ns Out put Hold Time t OHA.5 6 8 10 ns CE Ac cess Time t ACE 0 5 35 45 ns OE Ac cess Time t DOE 8 1 15 0 ns OE to High-Z Out put t HZOE 0 8 8 10 0 15 ns OE to Low-Z Out put t LZOE 0 0 0 0 ns CE to High-Z Out put t HZCE 0 8 0 8 0 10 0 15 ns CE to Low-Z Out put t LZCE 3 10 10 10 ns LB, UB Ac cess Time t BA 0 8 0 5 0 35 45 ns LB, UB to High-Z Out put t HZB 8 8 10 0 15 ns LB, UB to Low-Z Out put t LZB 0 0 0 0 ns 1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.5V, input levels of 0.4V to V DD -0.3V and output loading specified in Figure 1a.. Tested with load in Figure 1b. Transition is measured 500mV from steady-state voltage. Not 100% tested. 4
TTS18WV16 Ex tended Tem per a ture TT Semiconductor Tel: 1 714 57-57; Fax: +1 714 57-5; Web: www.ttsemiconductor.com 5
TT Semi con duc tor Ex tended Tem per a ture TTS18WV16 WRITE CYCLE SWITCHING CHARACTERISTICS 1, -0-5 -35-45 Pa ram e ter Sym bol Min Max Min Max Min Max Min Max Units Write Cy cle Time t WC 0 5 35 45 ns CE to Write End t SCE 1 18 5 35 ns Ad dress Setup Time t AW 1 15 5 35 ns to Write End Ad dress Hold from Write End t HA 0 0 0 0 ns Ad dress Setup Time t SA 0 0 0 0 ns LB, UB Valid to End of Write t PWB 1 18 30 35 ns WE Pulse Width (OE = High) t PWE 1 WE Pulse Width (OE=Low) t PWE 1 18 30 35 ns 17 0 30 35 ns Data Setup to Write End t SD 9 1 15 0 ns Data Hold from Write End t HD 0 0 0 0 ns WE LOW to High-Z Out put t HZWE 3 WE HIGH to LOW-Z Out put t LZWE 3 0 9 0 1 0 0 ns 3 5 5 5 ns 1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to V DD -0.3 and output loading specified in Figure 1a.. Tested with load in Figure 1b. Transition is measured 500mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB, or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates and write. 6
TTS18WV16 Ex tended Tem per a ture TT Semiconductor TT Semiconductor; 35 North Shepard Street; Anaheim, California 9831; USA 7
TTS18WV16 Ex tended Tem per a ture TT Semiconductor 8
TT Semiconductor Ex tended Tem per a ture TTS18WV16 Data Retention Switching Characteristics Pa ram e ter Sym bol Test Con di tion Op tions Min Typ 1 Max Units V DD for Data Re ten tion V DR See Data Retention Wave form.0 3.6 V Data Re ten tion Cur rent I DR V DD =.0V, CE V DD -0.V Mil. 0 100 A Ext. 00 HT 50 Data Re ten tion Setup Time t SDR See Data Re ten tion Wave form 0 ns Re cov ery Time t RDR See Data Retention Wave form t RC ns 1.Typical values are measured at V DD = 3.0V, T A = 5 C and not 100% tested. 9
TTS18WV16 Ex tended Tem per a ture TT Semiconductor Fig ure 1: 44 Ld LCC Package Fig ure 6: Or der ing Information 10