Floating Gate Devices: Operation and Compact Modeling Paolo Pavan (1), Luca Larcher (1) and Andrea MarmirolI (2) (1) Università di Modena e Reggio Emilia, Via Fogliani, 1 42100 Reggio Emilia (Italy) - pavan.paolo@unimo.it (2) STMicroelectronics, Central R&D, Via C. Olivetti, 2, 20010 Agrate Brianza (MI), Italy andrea.marmiroli@st.com
Motivation and Purposes OUTLINE Floating Gate (FG) Device model: FG voltage calculation (DC) Parameter extraction procedure Program/erase current modeling (TRANSIENT) Fowler-Nordheim tunnel current + a new self-consistent model to calculate the electric field within the oxide Channel Hot Electron (CHE) and Channel Initiated Secondary Electron (CHISEL) currents Reliability simulations Stress and Radiation Induced Leakage Current Advantages and Conclusions
MOTIVATIONS AND PURPOSES FG memory cells are usually replaced with standard MOS in industry circuit simulations: Spice-like models demanded The standard method to calculate the FG potential uses capacitive coupling coefficients, α i = C i /C T V FG = α CG V CG + α D V D + α S V S + α B V B Constant capacitive coupling coefficients errors [1] The optimum model should be: Spice-like, compact, accurate, reliable (both DC and transient) [1] L. Larcher, et al., IEEE Trans. Elect. Devices, Sept. 2001
The new DC model Control Gate Floating Gate CPP VFG Source P-substrate Body Drain C PP V FG = interpoly dielectric capacitance = Floating Gate voltage
Elements of the DC model The new Spice-like model uses lumped circuit elements: the capacitor, C PP, which takes into account the inter-poly dielectric capacitance the MOS transistor: can be MOS Model 9 (Philips) or BSIM3v3 (Berkeley), or The voltage controlled voltage source, V FG : It implements the procedure to calculate the FG voltage in a C code routine It is necessary to overcome problems in simulating a capacitive net in DC conditions
V FG calculation FG CG VFG V FG is calculated by solving the charge neutrality equation at the FG node: D S B Q MOS + Q CPP = Q W/E Q CPP = C PP (V FG -V CG ) Q W/E = charge injected into the FG during the write/erase (constant in DC conditions) Q MOS = f(v FG,V S,V B,V D ) calculated by means of the MOS model charge equations.
Q MOS calculation MOS Model 9 (Philips) charge equations: MOS [ QB + QD + QS] + CGDOVGD + CGSOVGS CGBOVGB Q = + Q = Q Q B S D f = f = f ( C, V, V, V, V, K ) OX FB SB T1 GB ( V, V,C, δ, F) DS2 GT3 OX ( V, V,C, δ, F ) DS2 GT3 OX 2 2 J J 0 MOS Parameters: K 0, C OX, V FB MOS electrical internal variables: V T1, V GT3, V DS2, δ 2, F J
Solution of charge equation The charge neutrality equation is an implicit equation in V FG : F(V FG ) = Q MOS (V FG ) + Q CPP (V FG ) Q W/E = 0 It has no analytical solution, due to the complex expression of Q MOS ELDO (Spice-like simulator) solves it numerically through suitable convergence algorithms Note that F is monotonic versus V FG for all the bias combinations (V CG,V S,V B,V D ) in the functionality range of the device, thus guaranteeing the physical meaning of the derived V FG solution
Parameters of the model Parameters of the equivalent MOS transistor (dummy cell): they can be extracted by applying the standard MOS parameter procedure to the dummy cell. Only one additional parameter compared to a standard MOS transistor: the Floating Gate to Control Gate capacitance C PP derived from the cross section and layout of the cell No additional costs compared to the standard modeling activity for MOS transistors The model is very easy and simple to use
The new transient model The DC model of FG memories can be extended to model transient conditions by adding some voltage controlled current sources to include program and erase currents Write currents of E 2 PROM and Flash are different: hence, number and position of current sources may vary for E 2 PROM and Flash Each voltage controlled current source models analytically a specific kind of program/erase current: Fowler-Nordheim, CHE, CHISEL One additional Eldo parameter allows the user to choose the desired Floating Gate memory (Flash or E 2 PROM) model
The new transient E 2 PROM model Control Gate CPP Floating Gate Drain IW/E VFG Source P-substrate Body For E 2 PROM memories, I W/E models the program/erase Fowler-Nordheim current flowing across the tunnel oxide
The new transient Flash model Control Gate Floating Gate CPP Iw1 Iw3 VFG Iw2 Source Body P-substrate Drain For Flash memories: I W1 and I W2 model the erase FN current; I W3 the CHE+CHISEL program current
Fowler-Nordheim current source The voltage controlled current source (implemented in ELDO) modeling Fowler/Nordheim currents allows to reproduce program-erase and erase operations of E 2 PROM and Flash memories, respectively. I FN B ( ) = 2 FN F ox ATAFNF ox exp Fox A T = area of the tunneling region A FN, B FN = Fowler-Nordheim coefficients depending on the Si/SiO 2 barrier F OX = electric field across the oxide, which has been evaluated through.
F OX calculation F OX = ( V V ) FG S,D,B T V OX FB ψ S ψ P V FB = flat-band voltage ψ S = surface potential drop at Si/SiO 2 interface ψ P = surface potential drop at poly-si/sio 2 interface To correctly evaluate ψ S and ψ P is necessary to take into account poly depletion and charge quantization effects: for this reason, a self consistent model has been used [2] The so calculated F OX has been incorporated in the FG model through an analytical law, parameterized on the FG and S,D,B dopings, which are additional parameters [2] L. Larcher et al., A new model of gate capacitance, IEEE Trans. Elect. Devices
CHE-CHISEL current source CHE-CHISEL gate currents have been modeled analytically and included by means of a voltage controlled current source This way, actual program operations of modern Flash memories can be reproduced also by circuit simulations The CHE-CHISEL current model adopts a new approach to model hot carrier phenomena, and particularly, to describe the high energy distribution of carriers involved in impact ionization phenomena
CHISEL current modeling The key point of CHISEL [3] current modeling is the accurate calculation of energy distribution of tertiary electrons, that are generated by four physical mechanisms (M) Gate CHISEL CHE Source M4 e 1 e 3 M2 h 2 M1 e 1,2 Drain Impact Ionization M3 h 2,3 Body [3] L. Larcher, P.Pavan, A New Analytical Model of Channel Hot Electron (CHE) and CHannel Initiated Secondary ELectron (CHISEL), MSM 2002, 2002, pp. 738-741.
Reliability Simulations Leakage currents across the gate oxide (SILC [4] -RILC [5] ) are modeled analytically and included by means of some voltage controlled current sources The model can simulate the reliability degradation of Flash and E 2 PROM memories due to the aging of the gate oxide induced by Program/Erase cycles and also by the exposure to ionizing radiation: read/gate/drain disturb prediction Now, our work is focused to model leakage currents due to Trap-Assisted Tunneling through n-traps including also the phonon contribution (percolation path) [4] L. Larcher et al. A Model of the Stress Induced Leakage Current in Gate Oxides, IEEE Trans. Electr. Devices, Vol.48, N.2, 2001, pp.285-288. [5] L. Larcher et al. A model of radiation induced leakage current (RILC) in ultra-thin gate oxides, IEEE Trans. Nuclear Science, Vol. 46 (6), pp. 1553-1561, 1999.
SILC - RILC modeling The Stress-Induced Leakage Current (SILC) and the Radiation-Induced Leakage Current are modeled assuming an inelastic Trap-Assisted Tunneling (TAT) as conduction mechanism cathode SiO 2 E p x T t ox anode
Simulation results Simulation results achieved by this model are excellent in both DC and transient condition, for either Flash and E 2 PROM memories, WITHOUT any free parameter to improve the fitting quality We tested the simulation capability of this model on both E 2 PROM and Flash memories, in DC and transient conditions.
DC E 2 PROM: I DS -V CG I (A) DS 10-5 10-6 10-7 10-8 V=0V SB C PP = 3 ff W=0.3 µm L=0.75 µm V=5V SB 10-9 simulation V (exp) 0..5 step 1V SB 10-10 0 1 2 3 4 5 V (V) CG
DC E 2 PROM: I DS -V DS 140 120 100 simulation V=0V B V=5V G V=4V G I ( A) DS µ 80 60 40 V=3V G V=2V G 20 V=1V G 0 0 0.5 1 1.5 2 2.5 3 3.5 4 V DS (V)
DC E 2 PROM: I DS -V CG 120 100 simulation V=0V B V (exp) 0.8..3.8 step 1V D I ( A) DS µ 80 60 V=3.8V D 40 20 V=0.8V D 0 0 1 2 3 4 5 V (V) CG
DC Flash: I DS -V CG 10-4 10-5 V (exp) 0..2 step 0.5V SB I (A) DS 10-6 10-7 10-8 V=0V SB V=2V SB C PP = 0.8 ff W=0.25 µm L=0.375 µm 10-9 10-10 10-11 V=0.1V DS simulation 2 3 4 5 6 7 V (V) CG
DC Flash: I DS -V DS I ( A) DS µ 25 20 15 10 5 simulation V B =0 V V CG =4 V V CG =3.75 V V CG = 3.5 V V CG =3.25 V V =3 V CG 0 0 0.3 0.6 0.9 1.2 1.5 1.8 V DS (V)
DC Flash: I DS -V CG I ( A) D µ 60 50 40 30 20 simulation V (exp) D 0.1 V 0.7 V 1.3 V 1.9 V C PP = 0.4 ff W=0.16 µm L=0.3 µm 10 0 2 2.5 3 3.5 4 4.5 5 5.5 6 V (V) CG
DC Flash: I DS -V DS 25 simulation V CG = 3.4 V I ( A) DS µ 20 15 10 V B =0 V C PP = 0.4 ff W=0.22 µm L=0.3 µm V CG = 3.2 V V =3 V CG V CG =2.8 V 5 0 V CG =2.6 0 0.3 0.6 0.9 1.2 1.5 1.8 V (V) DS
I ( A) D µ 30 25 20 15 10 5 DC Flash: I DS -V DS simulation V (exp) D 0.4 V 0.8 V 1.2 V 1.6 V 0 1.5 2.0 2.5 3.0 3.5 V (V) CG
T Transient Flash: V T -time V (V) 7 6 5 4 V (exp) -2.7..-4.7 step 1V G0 V = -4.7 V G0 Erase bias: D float V S =V B =8 V V CG 3 V = -2.7 V G0 V G,MAX 2 1 0 simulation V=V=8 B S V 0 0.1 0.2 0.3 0.4 Time (s) V G0 Time
T Transient Flash: V T -time V (V) 7 6 5 4 3 2 dv/dt (exp)= 12.5,20,25,30,35,50,60 V/s simulation dv/dt= 12.5V/s 1 0 dv/dt= 60 V/s 0 0.1 0.2 0.3 0.4 Time (s)
Erase E 2 PROM: V T -time 4 3 Lines: simulations Symbols: measures 2 V T (V) 1 0-1 T RISE (ms ) 0.3 0.4 0.5 0.6 12V V CG -ramp -2-3 T RIS 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Time (ms) E V D =V B =0V V S =0V
Program E 2 PROM: V T -time 3 12V V D -ramp 2 V CG =V B =0V V T (V) 1 0 T RISE (ms ) 0.3 0.4 0.6 T RIS E 0.7 V S floating -1-2 Lines: simulations Symbols: measures 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Time (ms)
Program E 2 PROM: V FG and V S 6 5 Dotted lines: V FG Solid lines: V S 4 3 2 T RISE (ms ) 0.3 0.6 12V V D -ramp 1 0-1 T RIS 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Time (ms) E
Erase E 2 PROM: Tunnel Current 60 50 Lines: simulations Symbols: measures V D -ramp Nominal I TUN (pa) 40 30 T RIS E Rea l 20 10 0 I TUN,MEAS = C CG dv dt 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 Time (ms) T
Simulation results: Flash program V (V) T 9 8 7 6 5 4 3 2 8 4 V CG pulse (V) 0 0 1 2 3 4 time ( µ s) V =4.2V DS (A) V (exp) SB 0 V 0.6 V 1.2 V 1.5 V 0 1 2 3 4 time ( µ s) No free parameter to improve the fitting quality!!
E 2 PROM retention simulations 4.7 4.2 N C 10-1 - fresh 10 2 VT(V) 3.7 10 3 3.2 10 4 2.7 5 N=10 C 0 1 2 3 4 5 6 7 8 9 10 Years
E 2 PROM read path schematic Current bias for sense amp VPSENSE VISENSE Sense Amplifier out VBOOST CG bias voltage generator VCG COL<0> COL<i> COL<n> CG voltage transfer block COL<i> WL BL Mini array of virgin cells CG<i> CELLS
E 2 PROM read path signals 6 5 V WL 4 V (V) 3 2 V SENSE OUT V CG V CELL 1 0 V REF V BL 0 100 200 300 400 500 Time (nsec )
E 2 PROM read path signals /2 3.0 3.0 2.5 V SENSE OUT 2.5 V SENSE OUT 2.0 V CELL 2.0 V CELL V (V) 1.5 V REF V (V) 1.5 V REF 1.0 V B L 1.0 V B L 0.5 0.5 0 0 310 330 350 370 390 410 Time (nsec ) 320 340 360 380 400 420 Time (nsec )
Advantages This model features many advantages compared to others proposed in the literature: The parameter extraction procedure is the same of a standard MOS transistors The simulation time is comparable to that of a simple MOS transistor V FG calculation procedure does NOT use capacitive coupling coefficients: this means a more accurate V FG calculation (considering the capacitive coupling coefficients as constants introduces errors)
Coupling coefficients: α CG -Flash VB=-1V VS=0V αcg 0.72 0.70 0.68 0.66 0.64 9 8 66.75 55.63 44.5 33.38 22. 11.13 0 0 1 2 3 VCG 4 5 V FG = α CG V CG + α D V D + α S V S + α B V B VD
Coupling coefficients: α D -Flash V FG = α CG V CG + α D V D + α S V S + α B V B αd 0.15 0.13 0.11. 0.07 9 8 7 60 50 40 30 20 10 0 0.05 9 2 3 4 5 VD VCG VB=-1V VS=0V
Advantages /2 This is the first compact DC and transient model of a FG memory cell: it can be used for both single device simulations and circuit simulations Fitting results are excellent WITHOUT any free parameter to improve the fitting quality This model is easily scalable: scaling rules are taken into account in the MOS model itself, and they do not affect the V FG calculation This model is easily upgradeable: voltage controlled current sources can be replaced independently on other elements of the model
Conclusions We developed a new compact Spice-like DC and transient model of the FG memory cell It overcomes the fixed coupling coefficients approach, thus improving the FG memory cell modeling It is easily scalable and upgradeable Its simulation time is not critical Parameters can be extracted applying the same procedure used for MOS transistor Simulation results are excellent without any free parameter to improve the fitting quality It can be used for statistical analysis (effects of statistical fluctuation of critical parameters)
References Paolo Pavan, Luca Larcher, Andrea Marmiroli, Floating Gate devices: Operation and Compact Modeling, Kluwer Academic Publishers, 2004, 140 pp., ISBN 1-4020-7731-9