Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models Ketan N. Patel, Igor L. Markov and John P. Hayes University of Michigan, Ann Arbor 48109-2122 {knatel,imarkov,jhayes}@eecs.umich.edu Abstract Circuit reliability is an increasingly imortant design consideration for modern logic circuits. To this end, our work focuses on the evaluation of circuit reliability under robabilistic gate-level fault models that can cature both soft errors, e.g., radiation-related, and satially-uniform manufacturing defects. This basic task can, in rincile, be used (i) by synthesis rocedures to select more reliable circuits, and (ii) to estimate yield for electronic nanotechnologies where high defect density is exected. We roose a matrix-based formalism to comute the error robability of the whole circuit based on robabilities of secific gate errors. This formalism is surrisingly related to that of quantum circuits, but also exhibits several new features. The numerical comutation of error robabilities in large circuits runs into the same scalability roblems as the simulation of quantum circuits. Therefore, we hoe to adat recent advances in quantum circuit simulation to the context of this work. 1 Introduction Device geometries continue to shrink in dee sub-micron VLSI circuits as clock seeds increase and er-chi costs dro. Finer device features make circuits more suscetible to manufacturing defects, noise-related transient faults and interference from radiation. In articular, we distinguish (i) soft errors that occur non-deterministically and may be related to alha-articles or gamma-radiation [4], and (ii) manufacturing defects that ermanently damage circuit comonents. Both tyes manifest in the form of logic errors and may be difficult to revent in the nearfuture technologies. Therefore, fault-tolerance and errorcorrection techniques aear increasingly imortant. Previously, fault-tolerant circuits and architectures have been roosed to absorb soft errors without jeoardizing the function of comuting systems. Examles include totally self-checking circuits [5] and dynamic verification of microrocessor oerations [1]. In the latter aroach, when a fault is detected, the oeration is redone, with a serious runtime enalty. However, the checker circuit is small and does not slow down the rocessor until a fault is discovered. With dynamic verification, the main rocessor does not have to be fully verified because rare faults, not found during simulation, can be tolerated. However, dynamic verification assumes very low incidence of logic errors, which can only be guaranteed by circuit-level techniques. The existing literature on circuit test and fault-tolerant circuits tyically uses interconnect-based models, e.g., stuck-at and bridging faults. While these models enable fast and ractically useful algorithms, they cannot adequately model more subtle behavior that faulty gates may exhibit. On the other hand, some interconnect faults can be catured by gate-level fault models with the hel of fake buffers inserted at the right laces. The anticiation of high defect densities in circuit comonents is suorted by recent work on chemicallyassembled electronic nanotechnology [2]. The authors exect defect rates of 1-10% in first technology generations. A roosed solution is a rogrammable circuit fabric with test structures that would allow to discover all actual defects in each circuit manufactured. A logic circuit can then be maed onto fully-functional gates and wires.
With less drastic means of tolerating errors in mind, our work focuses on circuits with faulty gates. In articular, we oint out that technology-secific faults in logic gates can be modeled robabilistically: for a given inut, every outut can be observed with a certain robability. Such models cature not only soft errors, but also manufacturing defects that are equally likely to occur in any gate of a given tye. Our work shows that the robability of erroneous outut deends not only on the faultiness of gates, but also on circuit structure. Related logic otimization would require a reliable way to evaluate the error robability of a circuit. The main contribution of this work is an analytical technique for this task. This technique fundamentally differs from existing architectural [1, 4] and emirical aroaches. We also oint out a surrising connection between the evaluation of circuit error robability and numerical simulation of quantum circuits. The remaining art of this manuscrit is organized as follows. We introduce robabilistic gate-level fault models in Section 2 where we also comute error-roerties of logic circuits with one-bit outut. In Section 3 we show that multi-outut circuits can achieve better faulttolerance. Similarities of the error-robability comutation to the simulation of quantum circuits are covered in Section 4. Conclusions and on-going work are discussed in Section 5. 2 Basic Methodology Below we first introduce gate-level fault models and then exlain how error roerties of a logic circuit can be modeled in terms of those models. An examle is given. 2.1 Probabilistic Gate-Level Fault Models In error-free oeration the function of a combinational logic circuit or gate can be reresented by a truth table, which is a deterministic maing of inut values to outut values. For examle, the truth table for an AND gate mas the inut value 01 to the outut value 0. However, in the resence of soft errors or manufacturing defects this inut may occasionally lead to a 1 at the outut of the gate. If we know how often this is likely haen, we can model this behavior using a robabilistic transfer matrix. Inthis matrix, column indices reresent inut values, and row in- Inuts 11 10 01 00 Outut 0 1 (a) Outut 0 1 Inut 0 1 (b) Inuts 11 10 01 00 Outut 0 1 Figure 1: Probabilistic transfer matrices used for noisy logic gates: (a) AND, (b) NOT, and (c) OR. The variable denotes the robability the gate will give an incorrect outut. Note matrices a and c are rotated. dices reresent outut values, while matrix elements cature air-wise transition robabilities. For examle, consider the ossible robabilistic transfer matrices shown in Figure 1 for the the standard AND, NOT and OR gates. In these examles the gates give the incorrect outut value with robability. In general, we could use any fixed robability distribution for the columns of the matrices. For examle, if we knew that the AND gate was twice as likely to give the incorrect outut for inuts 01 and 10 versus for inuts 00 and 11, we could reflect this is the matrix: [ 1 1 2 1 2 2 2 1 The only requirement is that each column sums to 1, since we assume that some value is always seen at the outut. The number of rows and columns are exonential in the number of gate inuts and oututs resectively. ]. 2.2 Derivation of Circuit Proerties The concet of the robabilistic transfer matrix is not restricted to gates. It can also reresent the function of a noisy circuit. The element in the i-th row and j-th column reresents the robability that the i-th outut value will be observed when the j-th inut value is given to the circuit. Now for convenience we also define the ideal transfer matrix. This is the robabilistic transfer matrix when there are no errors. Each column of this matrix contains (c)
A A B A B B BA A B B A (a) (b) (c) Figure 2: Basic ways to interconnect circuit comonents and the corresonding oeration on the robabilistic transfer matrices. (a) serial (b) arallel (c) fanout exactly one 1 with the remaining elements being 0. Now if we know the robability distribution of inut values that will be given to the circuit, that is, if we know that the i-th inut value will be given to the circuit with robability i, then we can calculate the error robability of the circuit from the ideal and robabilistic transfer matrices C and P: 2 n 1 i P [ j,i], i=0 j:c( j,i)=0 where P [i, j] denotes the element in the i-th row and j-th column of matrix P. For the noisy AND gate in Figure 1a this calculation gives a robability that the gate will give an incorrect outut. Therefore, if we can construct the robabilistic transfer matrix for a circuit, then we can calculate its error robability. Now we show that if we assume that gate errors occur indeendently and we know the robabilistic transfer matrices of the gates in the circuit, then by erforming oerations on these we can obtain the robabilistic transfer matrix of the circuit. The basic method is as follows: we construct the circuit by connecting together gates into sub-circuits then connecting together these subcircuits; each time we connect two comonents, we derive the robabilistic transfer matrix of the combined circuit from those of the comonents. There are three basic ways in which comonents in a well-formed circuit are combined: serially, in arallel, and through fanout. These are illustrated in Figure 2. We now show how each of these oerations affects the robabilistic transfer matrices. Serial Comosition is the most straightforward. This occurs when a comonent acts on the oututs of another comonent. The robabilistic transfer matrix of the result is given by the roduct of those of the comonents. For examle, consider the serially connected comonents shown in Figure 2a. Suose A and B denote the robabilistic transfer matrices of the two comonents. Let comonent A have n inuts and m oututs, and comonent B have m inuts and l oututs. Let us calculate the robability that when an inut i is given to the first comonent, we observe an outut j. This is by definition the element in the j-th row and i-th column of the overall error transfer matrix. If an inut i is given to the first comonent, the robability distribution of the oututs of the first comonent are given by the i-th column of A. The vector with the robabilities that each of the ossible inuts to the second comonent give an outut j is given by the j row of B. Therefore, the robability that the outut of the second comonent will be j, given that i is inut to the first comonent, is equal to the inner roduct of the i-th column of A and the j-th row of B. Thus, the overall robabilistic transfer matrix is given by B A. Parallel Comosition involves two or more circuit comonents acting on disjoint sets of bits. The corresonding matrix oeration is the tensor roduct of the robabilistic transfer matrices of the comonents. Consider the examle shown in Figure 2b. Suose A and B denote the robabilistic transfer matrices of the two comonents. Let comonent A have n inuts and m oututs and let comonent B have l inuts and k oututs. Consider an inut i to the overall circuit, which can be artitioned into inuts i A and i B to the resective comonents A and B. Since the two comonents are indeendent, the robability distribution of the oututs for the first comonent are given by the i A -th column of A and those of the second comonent are given by the i B -th column of B. So the robability that an outut j =(j A j B ) is observed is given by the roduct A [ ja,i A ] B [ jb,i B ], which is the element in the i-th row and j-th column of the combined robabilistic transfer matrix. Writing out the entire matrix we have A [0,0] B A [0,1] B A [0,n] B A [1,0] B A [1,1] B A [1,n] B...., A [m,0] B A [m,1] B A [m,n] B
a b c (a) a c b (b) Figure 3: Two circuits that comute the function f (a,b,c)=b+a c. The circuit to the right is more robust to transient gate faults than the one to the left, assuming a uniform gate failure robability. Incorrect outut robability 0.7 0.6 0.5 0.4 0.3 0.2 0.1 Circuit (a) Circuit (b) which is equal to the tensor (Kronecker) roduct A B. Fanout When comonents are connected with fanout an outut of one comonent is connected to multile inuts of the following comonent. In order to reresent this tye of connection, we simly eliminate those columns in the robabilistic transfer matrix of the second comonent that corresond to different values on the coied wire. For examle, consider the circuit in Figure 2c. If comonent B has two inuts both from the same outut of comonent A, we would eliminate columns 1 = {01} and 2 = {10} from comonent B s robabilistic transfer matrix. 2.3 Circuit Examle Using the three basic oerations above, we can find the overall robabilistic transfer matrix for any well-formed combinational circuit. Now we illustrate this method for two different circuits shown in Figure 3, both comuting the function f (a,b,c)=b + a c. For convenience, we denote the robabilistic transfer matrices of the AND, NOT, and OR gates by the names of the gates and to simlify the algebra we define q = 1. First we take the circuit given in Figure 3a. At deth 1 we take the tensor of the two AND gates: [ ] [ ] qqq qqq T 1 = AND AND =. q q This yields a 4 16 matrix with column labels abbc. In order to reduce out the dulicate coy of b we eliminate the columns where the two coies are not the same, i.e., columns with labels of the form X01X and X10X. This 0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Gate error robability () Figure 4: Probability of incorrect outut as a function of gate error robability for the two circuits in Figure 3. leaves the following transfer matrix: q 2 q 2 q 2 q q 2 q 2 q 2 T 1 = q q q q 2 q q 2 q. q q q 2 q q q 2 q 2 2 2 q 2 2 q q 2 Finally we aly the OR and NOT gates: T 3 = NOT T 2 = NOT OR T 1 For the circuit in Figure 3b, we have T 3 = OR (AND NOT) (NOT NOT I 2 ), where I 2 is the robabilistic transfer matrix for an ideal wire, i.e., the 2 2 identity matrix. We can now calculate the error robability for each circuit given the inut value distribution. Assuming that all inut values to the circuits are equirobable, Figure 4 shows the robability of an incorrect outut for both circuits with resect to the gate error robability. The second circuit has a lower robability of giving an incorrect outut over the entire range of gate error robabilities. The basic intuition here is that long narrow circuits are
generally more error-rone than short wide ones. In this examle, all aths to the outut in the first circuit must go through the last two gates. Therefore, faults in either of these gates affect all ossible inuts. By contrast, in the second circuit, only the last gate is used by all aths from an inut to the outut. This examle should only be taken as an illustration of our method, not as a realistic evaluation of the relative robustness of the circuits in Figure 3. In a real alication the robability that a gate fails would robably be correlated with both the gate tye and the gate inuts. Both of these could be incororated into our method by using more accurate robabilistic transfer matrices for the gates in the circuits. 3 Better Fault-Tolerance using Multile Oututs Thus far our rimary goal has been to evaluate error roerties of different circuit structures that comute the same function. However the achievable error roerties for the circuits we have considered have been limited by the error-resistance of the gate driving the outut: if this gate gives a faulty outut so does the circuit. This is a general limitation of single-outut circuits. One way to decrease the robability of errors is to encode inut and outut using redundant wires. In this case, a logical bit (or set of bits) is reresented by a larger number of hysical bits. For examle, a simle outut encoding could ma the logical value 0 to three hysical bits all with value 0, similarly with the logical 1 value. A circuit with a single logical outut bit would actually have three hysical bits as oututs. If one of the outut gates fails, the correct logical outut is still retrievable from the remaining two correct outut bits. Of course, decoding circuitry is necessary at some oint, only delaying the inevitable single gate failure limit, however this may be ostoned to the end of the comutation where this relatively small decoding logic can be made hysically robust. This is in contrast to making each of the circuit s gates hysically more robust. The use of encoded inuts and outut fits relatively seamlessly into our methodology. For reresenting the inut encoding, we have two choices: we can either choose the inut value distribution to reflect the encoding, i.e., have robability 0 for non-code values; or we can actually eliminate the columns of the robabilistic transfer matrices reresenting non-code values. The latter is very similar to our method for reresenting fanout in Section 2.2. In general the first method is concetually simler, but may require extra unnecessary comutations. At the outut we need to reresent the maing of hysical outut bits to logical oututs; in our three bit examle above, we would ma 000, 100, 010, and 001 all to the logical outut value 0. This is easily done by modifying the ideal transfer matrix: rather than a single 1 in each column of this matrix reresenting the correct outut value, we have multile 1 s reresenting each of the ossible correct outut values. Another way to increase the error-resistance of a single outut circuit is to increase the reliability of the limiting gate, namely the gate driving the outut. This may be ossible in some imlementation and for some noise environments; for examle, two basic gate sizes may be available in some imlementations with the larger being less suscetible to radiation effects. Carrying this argument further, we could add the flexibility to choose gate sizes for any of the gates in the circuit, given erhas some limit on the area overhead. However, in general it may not be obvious which gates sizes should be increased to maximize error-resistance. Our method for evaluating the circuit s error-resistance could be very useful for this. 4 Quantum Circuits and Scalability Quantum comutations are reresented by comlex unitary matrices [6] (multilying a unitary matrix by its conjugate-transose gives the identity matrix). The square of the amlitude of each element gives the robability of a transition from one basis state to another. Such matrices cature the functions of individual quantum gates and also whole quantum circuits (note that quantum gates have as many inuts as oututs, ditto for quantum circuits). Quantum states, including circuit inut and outut, are comlex vectors. Given a unitary matrix of a quantum gate, the outut is roduced by inut using matrix-vector multilication. Because of this, sequential comosition is reresented by the regular matrix-matrix multilication and arallel comosition by the tensor (Kronecker) roduct.
This is similar to how we comute the robabilistic transfer matrix of a circuit from gate matrices. There are a few imortant differences between our roblem and the quantum circuit roblem. 1. Quantum circuits do not have fanouts. Thus, one of our oerations does not have a quantum analog. 2. All quantum gates have the same number of oututs as inuts, and therefore all of the matrices are square. This is usually not the case for our roblem. 3. The matrix elements in our case are real, while they may be comlex in the quantum circuit case. On the other hand, our matrices do not have to be realunitary (a.k.a. orthogonal) the only requirement is that all elements in every column add u to one. 4. Our comutation differs greatly from the oeration of quantum circuits in the last ste. Quantum measurement is alied after a quantum circuit, but we use an unrelated oeration to calculate the error robability from the robabilistic transfer matrix. The matrices in both our roblem and the quantum circuit roblem are double-exonential in size with resect to the number of inuts and oututs. This leads to obvious scalability concerns for numerical methods. However, these concerns are already being addressed in the field of simulation of quantum circuit with BDD-based techniques [3, 7] which we hoe to adat to our domain. To simulate a quantum circuit, one starts with an inut vector and comutes an outut vector. Quantum measurement the last ste, irrelevant to our work is simulated by comuting the robabilities of all ossible outcomes. The simulation of quantum circuits [3, 7] is imortant, because, among other things, it rovides a method to evaluate designs rior to imlementation. A recent roosal to deal with the scalability roblem detects and eliminates common arithmetic sub-exressions, drastically simlifying the comutation [7]. Comutationally, this aroach is based on Binary Decision Diagrams, articularly the QuIDD datastructure adated from Algebraic Decision Diagrams (ADDs). All matrices and vectors are reresented by decision diagrams and relevant oerations are erformed using DD traversals. This aroach aears alicable to our roblem as well, with the caveat that we must develo a new BDD-based oeration to model fanout. This is one of directions of on-going work. 5 Conclusions and On-going Work This work is reliminary, and we are investigating several further directions. These include more detailed analyses of the analogy with quantum circuit simulation. Through the adatation of the QuIDD Pro quantum circuit simulator [7] we hoe to significantly imrove the erformance of our basic method. We also exloring ways to simlify the calculations by using aroximations at critical stages, while still reserving the integrity of the result. We also lan incororate our circuit reliability evaluation method into synthesis algorithms, articularly faulttolerant synthesis methods acting on encoded inuts and oututs. This has the otential of significantly imroving circuit reliability. A better understanding of fault-tolerant logic may be ossible by analytical means. For examle, one somewhat obvious roerty we ve observed is that long narrow circuits tend to be more suscetible to gate faults than short wide ones. Further studies of error roerties of logic circuits, e.g., trees, may lead to new circuit otimization strategies and heuristics usable during synthesis. References [1] T. M. Austin. DIVA: A Dynamic Aroach to Microrocessor Verification, Journal of Instruction Level Parallelism, May 2000. [2] S. C. Goldstein and M. Budiu. NanoFabrics: Sarial Comuting Using Molecular Electronics, Intl. Sym. on Com. Arch., June 2001. [3] D. Greve. QDD: a quantum comuter emulation library, htt://home.lutonium.net/ dagreve/qdd.html [4] S. Kim and A. K. Somani. Soft error sensitivity characterization for microrocessor deendability enhancement strategy, Proc. Intl. Conf. on Deendable Systems and Networks, 2002. [5] P.K.Lala.Self-Checking and Fault-Tolerant Digital Design. Academic Press, Inc., 2001. [6] M.A.NielsenandI.L.Chuang.Quantum Comutation and Quantum Information. Cambridge Univ. Press, 2000. [7] G. F. Viamontes, M. Rajagoalan, I. L. Markov, and J. P. Hayes. Gate-level Simulation of Quantum Circuits, Proc. ASPDAC 2003,. 295-301.