INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 7C/CT/CU/CMOS Logic Family Specifications The IC06 7C/CT/CU/CMOS Logic Package Information The IC06 7C/CT/CU/CMOS Logic Package Outlines 7C/CT16 8-bit serial-in/parallel-out shift register File under Integrated Circuits, IC06 December 1990
7C/CT16 FEATURES Gated serial data inputs Asynchronous master reset Output capability: standard I CC category: MSI GENERAL DESCRIPTION The 7C/CT16 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. Data is entered serially through one of two inputs (D sa or D sb ); either input can be used as an active IG enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied IG. Data shifts one place to the right on each LOW-to-IG transition of the clock (CP) input and enters into Q 0, which is the logical AND of the two data inputs (D sa,d sb ) that existed one set-up time prior to the rising clock edge. A LOW level on the master reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all outputs LOW. The 7C/CT16 are 8-bit edge-triggered shift registers with serial data entry and an output from each of the eight stages. QUICK REFERENCE DATA GND = 0 V; T amb = 25 C; t r = t f = 6 ns SYMBOL PARAMETER CONDITIONS C TYPICAL CT UNIT t PL / t PL propagation delay CP to Q n MR to Q n C L = pf; V CC = 5 V f max maximum clock frequency 78 61 Mz C I input capacitance 3.5 3.5 pf C PD power dissipation capacitance per notes 1 and 2 package 0 0 pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D = C PD V 2 CC f i + (C L V 2 CC f o ) where: f i = input frequency in Mz f o = output frequency in Mz (C L V 2 CC f o ) = sum of outputs C L = output load capacitance in pf V CC = supply voltage in V 2. For C the condition is V I = GND to V CC For CT the condition is V I = GND to V CC 1.5 V 11 1 16 ns ns ORDERING INFORMATION See 7C/CT/CU/CMOS Logic Package Information. December 1990 2
7C/CT16 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 2 D sa,d sb data inputs 3,, 5, 6, 10, 11,, 13 Q 0 to Q 7 outputs 7 GND ground (0 V) 8 CP clock input (LOW-to-IG, edge-triggered) 9 MR master reset input (active LOW) 1 V CC positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 1990 3
7C/CT16 Fig. Functional diagram. APPLICATIONS Serial data transfer FUNCTION TABLE OPERATING MODES INPUTS Note 1. = IG voltage level h = IG voltage level one set-up time prior to the LOW-to-IG clock transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-IG clock transition q = lower case letters indicate the state of the referenced input one set-up time prior to the LOW-to-IG clock transition = LOW-to-IG clock transition OUTPUTS MR CP D sa D sb Q 0 Q 1 Q 7 reset (clear) L X X X L L L shift l l h h l h l h L L L q 0 q 6 q 0 q 6 q 0 q 6 q 0 q 6 Fig.5 Logic diagram. December 1990
7C/CT16 DC CARACTERISTICS FOR 7C For the DC characteristics see 7C/CT/CU/CMOS Logic Family Specifications. Output capability: standard I CC category: MSI AC CARACTERISTICS FOR 7C GND = 0 V; t r = t f = 6 ns; C L = 50 pf SYMBOL t PL / t PL t PL t TL / t TL t W t W t rem t su t h f max PARAMETER propagation delay 1 CP to Q n propagation delay MR to Q n 39 1 11 output transition time clock pulse width IG or LOW master reset pulse width; LOW removal time MR to CP set-up time D sa, D sb to CP hold time D sa,d sb to CP maximum clock pulse frequency T amb ( C) 7C +25 0 to +85 0 to +5 min. typ. max. min. max. min. max. 80 16 1 60 10 60 10 60 10 6 30 35 19 7 6 1 5 17 6 5 17 6 5 8 3 2 6 2 2 23 71 85 170 3 29 10 28 2 75 13 100 20 17 75 13 75 13 75 13 5 2 28 2 3 37 175 35 30 95 19 16 0 2 20 90 18 90 18 90 18 20 2 255 51 3 210 2 36 110 22 19 UNIT TEST CONDITIONS V CC (V).5.5.5.5.5.5.5.5 Mz 2.0.5 WAVEFORMS December 1990 5
7C/CT16 DC CARACTERISTICS FOR 7CT For the DC characteristics see 7C/CT/CU/CMOS Logic Family Specifications. Output capability: standard I CC category: MSI Note to CT types The value of additional quiescent supply current ( I CC ) for a unit load of 1 is given in the family specifications. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT D sa,d sb CP MR UNIT LOAD COEFFICIENT 0.25 0.60 0.90 AC CARACTERISTICS FOR 7CT GND = 0 V; t r = t f = 6 ns; C L = 50 pf T amb ( C) TEST CONDITIONS 17 36 5 5 ns.5 19 38 8 57 ns.5 7CT SYMBOL PARAMETER UNIT V WAVEFORMS +25 0 to +85 0 to +5 CC (V) min. typ. max. min. max. min. max. t PL / t PL propagation delay CP to Q n t PL propagation delay MR to Q n t TL / t TL output transition time 7 19 22 ns.5 t W t W t rem t su t h f max clock pulse width IG or LOW master reset pulse width; LOW removal time MR to CP set-up time D sa,d sb to CP hold time D sa,d sb to CP maximum clock pulse frequency 18 7 23 27 ns.5 18 10 23 27 ns.5 16 7 20 2 ns.5 6 18 ns.5 2 ns.5 27 55 22 18 Mz.5 December 1990 6
7C/CT16 AC WAVEFORMS (1) C : V M = 50%; V I = GND to V CC. CT : V M = 1.3 V; V I = GND to 3 V. Waveforms showing the clock (CP) to output (Q n ) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. (1) C : V M = 50%; V I = GND to V CC. CT : V M = 1.3 V; V I = GND to 3 V. Fig.7 Waveforms showing the master reset (MR) pulse width, the master reset to output (Q n ) propagation delays and the master reset to clock (CP) removal time. (1) C : V M = 50%; V I = GND to V CC. CT : V M = 1.3 V; V I = GND to 3 V. Fig.8 Waveforms showing the data set-up and hold times for D n inputs. December 1990 7
7C/CT16 PACKAGE OUTLINES See 7C/CT/CU/CMOS Logic Package Outlines. December 1990 8
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