UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on Marc 15 t, 2005 by Cris Baker (crbaker@eecs) Andrei Vladimirescu Homework #6 EECS141 Due Friday, April 1 st, 4pm @240 Cory Problem 1 CMOS Analysis 1A Implement te equation = (( + )( + + ) + ) X A B C D E F G using complementary CMOS. Size te devices so tat te output resistance is te same as tat of an inverter wit an NMOS W/L = 2 and PMOS W/L = 6. Pull-down (W/L) n : Sizeof( A, B ) = 8 Sizeof (C, D, E ) = 12 Sizeof( F ) = 4 Sizeof( G ) = 2 Pull-up (W/L) p : Sizeof( G, F ) = 12 Sizeof( A, B, C, D, E ) = 24 1B Wic input pattern(s) would give te worst and best equivalent pull-up or pulldown resistance? Using te sizing from part a, find combination of inputs tat would maximize (worst) or minimize (best) resistance. For worst case analysis, for pull-down, want to carge up as many internal capacitances as possible; for pull-up, we want to discarge as many internal capacitances as possible.
Pull-down Pull-up Best G, F, A, B, C, D, E: 0 1 G, F, A, B, C, D, E: 1 0 Worst B, E: 0; F, A, C, D: 1; G: 0 1 B, E: 0; F, A, C, D: 1; G: 1 0 Wit B, E, and G equal to zero te pull down pat will be off and te pull-up network will carge up all internal capacitances because F, A, C, and D are on in te pull-down network. Once G transitions, all te carge stored on te output and internal nodes will ave to discarge troug one transistors. Similar reasoning ere; wit G in te pull-down network on, it discarges all internal nodes to zero; once G switces, te pullup network must carge up all internal nodes bot in te pullup networks, and pull-down networks. Tere could be a lot of variations on te interpretation of worse case. Te interpretation ere was to ave to carge or discarge te most capacitance. Anoter interpretation could be only exciting te longest series pat (toug we ve sized it suc tat tis pat is equivalent to te unit inverter). 1C Verify part b wit SPICE (using g25.mod).
* w6 prob 1c.lib '/ome/ff/ee141/models/g25.mod' TT.param low=0.param ig=2.5 VDD 1 0 ig VA 6 0 PWL 0 low 2n low 2.1n ig 4.1n ig 4.2n low 6.2n low 6.3n ig VB 16 0 PWL 0 low 2n low 2.1n ig 4.1n ig 4.2n low VC 4 0 PWL 0 low 2n low 2.1n ig 4.1n ig 4.2n low 6.2n low 6.3n ig VD 12 0 PWL 0 low 2n low 2.1n ig 4.1n ig 4.2n low 6.2n low 6.3n ig VE 7 0 PWL 0 low 2n low 2.1n ig 4.1n ig 4.2n low VF 13 0 PWL 0 low 2n low 2.1n ig 4.1n ig 4.2n low 6.2n low 6.3n ig VG 5 0 PWL 0 low 2n low 2.1n ig 4.1n ig 4.2n low 8.2n low 8.3n ig + 12.3n ig 12.4n low M0 11 5 1 1 pmos L=240E-9 W=3E-6 AD=1.8E-12 AS=1.8E-12 PD=7.2E-6 PS=7.2E-6 +M=1 M4 8 16 11 1 pmos L=240E-9 W=6E-6 AD=3.6E-12 AS=3.6E-12 PD=13.2E-6 +PS=13.2E-6 M=1 M5 8 6 11 1 pmos L=240E-9 W=6E-6 AD=3.6E-12 AS=3.6E-12 PD=13.2E-6 +PS=13.2E-6 M=1 M6 15 13 1 1 pmos L=240E-9 W=3E-6 AD=1.8E-12 AS=1.8E-12 PD=7.2E-6 +PS=7.2E-6 M=1 M1 15 7 8 1 pmos L=240E-9 W=6E-6 AD=3.6E-12 AS=3.6E-12 PD=13.2E-6 +PS=13.2E-6 M=1 M2 15 12 8 1 pmos L=240E-9 W=6E-6 AD=3.6E-12 AS=3.6E-12 PD=13.2E-6 +PS=13.2E-6 M=1 M3 15 4 8 1 pmos L=240E-9 W=6E-6 AD=3.6E-12 AS=3.6E-12 PD=13.2E-6 +PS=13.2E-6 M=1 * 7 = E * 12 = D * 16 = B * 6 = A, 4 = C, 3 = net34, 9 = net37 * 15 = X, 5 = G * 13 = F, 10 = net43 M7 14 7 0 0 nmos L=240E-9 W=3E-6 AD=1.8E-12 AS=1.8E-12 PD=7.2E-6 PS=7.2E-6 +M=1 M8 3 12 14 0 nmos L=240E-9 W=3E-6 AD=1.8E-12 AS=1.8E-12 PD=7.2E-6 +PS=7.2E-6 M=1 M9 9 16 0 0 nmos L=240E-9 W=1.98E-6 AD=1.188E-12 AS=1.188E-12 PD=5.16E-6 +PS=5.16E-6 M=1 M10 10 4 3 0 nmos L=240E-9 W=3E-6 AD=1.8E-12 AS=1.8E-12 PD=7.2E-6 +PS=7.2E-6 M=1 M11 10 6 9 0 nmos L=240E-9 W=1.98E-6 AD=1.188E-12 AS=1.188E-12 PD=5.16E-6 +PS=5.16E-6 M=1 M12 15 5 0 0 nmos L=240E-9 W=480E-9 AD=288E-15 AS=288E-15 PD=2.16E-6 +PS=2.16E-6 M=1 M13 15 13 10 0 nmos L=240E-9 W=1.02E-6 AD=612E-15 AS=612E-15 PD=3.24E-6 +PS=3.24E-6 M=1.options nmod post=2.tran 100p 15n.END
Pull-down Pull-up Best 165ps 51.8ps Worst 575ps 445ps Note te lack of symmetry; our sizing above for symmetry in te worst case doesn t account for te fact tat in te worst case, we re carging/discarging internal node capacitance. 1D If P(A=1)=P(F=1)=0.5, P(B=1)=0.2, P(C=1)=P(E=1)=0.3, P(D=1)=1, and P(G=1)=0.6, determine te dynamic power dissipation in te logic gate. Assume V DD =2.5V, C out =30fF, f clk =250MHz and te inputs are uncorrelated. ( ) p = p + p p p + p p p = 0.695 p α x= 0 G F A B C D E = 1 p = 0.305 x= 1 x= 0 = p p = 0.212 0 1 x= 0 x= 1 2 ( )( )( ) ( ) 2 15 6 P = α C V f = 0.212 30 10 2.5 250 10 = 9.94µ W dyn 0 1 out DD clk 1E Suppose all NMOS devices are (W/L) n and PMOS devices are (W/L) p. Does your implementation of X yield te lowest output capacitance. If so, wy; if not, rearrange your implementation so it as te lowest output capacitance. Explain.
Dependi ng on ow your scematic looks you migt ave to rearrange it. Te goal is to ave te minimum number of transistors, from eiter te pull-up or pull- drain-* capacitances. In te scematic above, move G in te pull-up network down networks, attaced to te output node X. Tis minimizes te number of from te top of te series connection, to te output, reducing te number of transistors attaced to X from 6 to 3. Problem 2 More CMOS 2A Wat is te logic function of circuits A and B in te figure below? Wic one is a dual network and wic one is not? Is te non-dual network still a valid static logic gate? Explain. List any advantages of one configuration over te oter. Bot logic functions implement te XNOR: F = AB+ AB = AB + AB Circuit A is te dual network; circuit B is not a dual network. Circuit B is a valid static gate because te pull-up input combinations AA and BB are never active (i.e. deleting te connection in te pull-up network does not break te gate s functionality). One advantage of Circuit B is tat it doesn t ave a common node to all devices in te PMOS; suc a node as more capacitance. Tis may result in sligtly lower pull-up delay. 2B Sketc te layout of bot gates in minimum area (i.e. fewest diffusion breaks). Compare/contrast te two circuit sketces; Sow work for Euler pats. Bot gates can be implemented in layout wit zero diffusion breaks. Te Euler pat for Circuit A is BAAB ; Circuit B s Euler pat is BABA (note you ave to swap te inputs on te rigt branc of te pull-down network; oterwise you d need a diffusion break).
Te main difference is te absence of te contact (orizontal metal spanning PMOSs) in circuit B s layout. Depending on layout, differences could be quite substantial. Problem 3 - Logical Effort 3A A four-input AOI21 gate works like one two-input (A, B) AND gate and a single input (C), driving a two-input NOR gate. Implement te AOI21 gate in one complementary CMOS gate, and size all transistors relative to an inverter wit an NMOS W/L = 1 and PMOS W/L = 2. Find te logical effort associated wit eac input.
Te logical effort for input C is (1+4)/3 = 5/3; te logical effort for inputs A B is (2+4)/3 = 2. and 3B For te saded pat sown in te above figure, find te pat brancing effort, pat electrical effort, pat logical effort, and total pat effort. Wat is te optimum effort per stage for minimizing delay? CL F = = 10 C H 1 B = b i = 9 G 200 = gi = 27 = FGB 667 5 = H = 3.67 3C Find te input capacitances {V, W, X, Y, Z} necessary for eac of te gates in te pat in order to acieve te optimum effort per stage. gz bz CL z = = 7.27fF gy by z y = = 9.90fF gx bx y x = = 4.50fF gw bw x w = = 7.36fF gv bv w v = = 2.00fF Note tat te size for gate v, 2.00fF matces our original assumption. Problem 4 - Pass-Transistor Logic
4A Wat is te function of te PTL gate below? Devise an alternate implementation of tis gate s logic function in PTL using two NMOS transistors and te output inverter (you may assume bot polarities of A and B are available). Tis gate implements te XOR function. Here s te alternate implementation: 4B For te circuit devised in part a (one wit two NMOS transistors), wat is te minimum voltage at wic tis circuit will operate correctly (and wy)? For te NMOS switces use VT0 = 0.5V, γ = 0.4V, 2 φf = 0.6V. Assume tat te inverter as an ideal VTC tat switces wen its input is at VDD/2. Tis circuit as a minimum voltage because wen te internal node is being driven to logic 1 it only reaces V DD -V TH. If tis voltage is less tan V DD /2 ten te inverter will produce an incorrect output. Tus, te minimum voltage is found from V DD -V T = V DD /2,or V DD = 2V T. Note tat V T V T0 because of te body effect. V V = 2 V + γ + 2φ 2 2φ DD DD T 0 F F Solving tis equation for V DD = 1.27V. 4C A level restoring PMOS transistor is now added to te two transistor gate devised in part a as sown in te figure below. Wat are te benefits and drawbacks of tis modification? Benefits: Full swing at internal node prevents any direct pat current from flowing in te inverter. Drawbacks:
Inputs must temporarily figt te PMOS transistor wen attempting to discarge te internal node (i.e., te input is no longer purely capacitive). Increased area as well as capacitance at te internal node. 4D If te level restoring PMOS transistor as VTH0 = -0.5V and W/L = 4 and µn = 3µP, wat is te minimum W/L for te NMOS switces in order for te circuit to function properly? In tis case we are looking for te smallest NMOS switc tat is capable of figting te level restoring PMOS to drive te internal node below V DD /2 and switcing te output. Te NMOS switc will just be strong enoug if it as te same R eq as te level restoring PMOS. Since bot devices ave V GS = V DD and te same VT, but te NMOS as 3 times greater mobility, tis will be te case wen (W/L) N = 1/3(W/L) P = 4/3. Problem 5 - Dynamic Logic. 5A Carg e saring can be azardous to te ealt of a dynamic gate. Wy? Given te to y scematic below, determine te final voltage V a long time after te switces close (t=0). Carge saring may reduce te voltage on te dynamic node to te point were logic value is not recoverable and logic errors are injected into te circuit. its Q = CV Q initial ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) = 50 0 2 + 30 1 0 + 20 4 1 + 24 4 + 2 Q = 50 V 2 + 30 V + 20 V 1 + 24 V + 2 Q final initial = Q final V 206 = = 1.67 V 124 5B Build a P-Domino implementation of te fuction F = AB(C+D) wit output inverter and keeper transistor driven by te output inverter. Explain te importance of te output inverter and keeper transistor. On wat level of te clock does tis gate evaluate? How about pre-discarge?
Te output inverter makes sure tere are no forbidden transitions (i.e. can only ave 1 0 or 1 1; cannot ave 0 1). Te forbidden transition could inadvertently discarge te output node (troug carge saring). Te keeper transistor elp staticize te dynamic node (guards against leakage). Te gate evaluates on te low level of te clock and pre-discarges on te ig level. Tis may be different if you assume te clock is inverted for P-Domino. 5C Instead of driving te keeper transistor wit te output inverter, suppose we drive te keeper transistor wit a different inverter. Tis new inverter is driven by te same node tat drives te output inverter (see below). If one were to skew te output inverter of te gate, wic direction, ig (strong PMOS) versus low skew (strong NMOS), would make te gate as a wole (P-Domino plus output inverter) faster? Wy? If one were to skew te keeper inverter, wic direction would be best and wy? Te output inverter sould be low skew (strong NMOS) because you want te transition from 1 to 0 (on te output of te inverter) to be fast. Te keeper inverter sould be ig skew (strong PMOS) because you want te keeper transistor to stay on longer to maintain te dynamic node.