The CMOS Inverter: A First Glance

The CMOS Inverter: A First Glance V DD V in V out C L

CMOS Properties Full rail-to-rail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power dissipation Direct path current during switching

CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND

Two Cascade Inverters Share power and ground V DD Connect in Metal

CMOS Inverter: First-Order DC Analysis V DD V DD V out R p V out V OL = 0 V OH = V DD V M = f(r n, R p ) R n V in = V DD V in = 0

Voltage Transfer Characteristic

PMOS Load Lines + - V GSp I Dp V in = V DD +V GSp I Dn = - I Dp V out = V DD +V DSp I Dn + V GSn - I Dn V out I Dp V in =0 I Dn I Dn V in =0 V in =1.5 V in =1.5 V GSp =-1 V DSp V DSp V out V GSp =-2.5 V in = V DD +V GSp I Dn = - I Dp V out = V DD +V DSp

CMOS Inverter Load Characteristics I Dn V in = 0 V in = 2.5 PMOS V in = 0.5 V in = 2 NMOS V in = 1 V in = 1.5 V in = 1.5 V in = 1 V in = 2 V in = 1.5 V in = 1 V in = 0.5 V in = 2.5 V in = 0 V out

CMOS Inverter Voltage Transfer Characteristics V out 0.5 1 1.5 2 2.5 NMOS off PMOS res Vdd = 2.5(V) NMOS sat PMOS res NMOS sat PMOS sat NMOS res PMOS sat V M V out = V in Switching Threshold NMOS res PMOS off 0.5 1 1.5 2 2.5 V in

V (V) M Switching Threshold as a function of Transistor Ratio 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 10 0 10 1 W p /W n

Noise in Digital Integrated Circuits v(t) V DD i(t) (a) Inductive coupling (b) Capacitive coupling (c) Power and ground noise

Mapping between analog and digital signals "1" V OH V IH V(y) V OH Slope = -1 Undefined Region V IL Slope = -1 "0" V OL V OL V IL V IH V(x)

Definition of Noise Margins "1" V OH Noise Margin High Noise Margin Low V OL "0" Gate Output NM H NM L V IH Undefined Region V IL Gate Input

Noise Margins V OH and V OL for the inverter circuit Digital Integrated Circuits 2nd Introduction to Circuits, Fourth Edition by Peter Uyemura, Inverter Copyright 2004 John Wiley & Sons. All rights reserved.

A simple Approach to Determine V out V IH and V IH IL V OH V M V in V OL V IL V IH A simplified approach

Inverter Gain 0-2 -4-6 gain -8-10 -12-14 -16-18 0 0.5 1 1.5 2 2.5 V in (V)

The Regenerative Property v 0 v 1 v 2 v 3 v 4 v 5 v 6... (a) A chain of inverters. v 1, v 3,... v 1, v 3,... f(v) finv(v) finv(v) f(v) v 0, v 2,... (b) Regenerative gate v 0, v 2,... (c) Non-regenerative gate

Impact of Process Variations (1) 2.5 V out (V) 2 1.5 1 Good NMOS Bad PMOS Nominal Good PMOS Bad NMOS 0.5 0 0 0.5 1 1.5 2 2.5 V in (V)

Impact of Process Variations (2) 2.5 0.2 2 0.15 V out (V) 1.5 1 V out (V) 0.1 0.5 0 0 0.5 1 1.5 2 2.5 V (V) in 0.05 Gain=-1 0 0 0.05 0.1 0.15 0.2 V (V) in VTC vs. Supply Voltage variation (0.25 um)

Propagation Delay

Propagation time definitions t pf = t phl t pr = t plh Digital Integrated Circuits 2nd Introduction to Circuits, Fourth Edition by Peter Uyemura, Inverter Copyright 2004 John Wiley & Sons. All rights reserved.

Delay Definitions V in 50% t phl t plh t V out 90% 50% t f 10% t r t

RC switch model equivalent for the CMOS Inverter Digital Integrated Circuits 2nd Introduction to Circuits, Fourth Edition by Peter Uyemura, Inverter Copyright 2004 John Wiley & Sons. All rights reserved.

CMOS Inverter Propagation Delay Approach 1 V DD t phl = C L V swing /2 I av I av V out C L ~ C L k n V DD V in = V DD

CMOS Inverter Propagation Delay Approach V DD V DD R p t phl = f(r n.c L ) = 0.69 R n C L V out V out C L C L R n V in = 0 (a) Low-to-high V in = V DD (b) High-to-low

Transient Response 3? 2.5 V out (V) 2 1.5 1 t plh t phl t p = 0.69 C L (R eqn +R eqp )/2 0.5 0-0.5 0 0.5 1 1.5 2 2.5 t (sec) x 10-10

Computing the Capacitances V DD V DD V in C gd12 M2 C db2 V out C g4 M4 V out2 M1 C db1 C w Interconnect C g3 M3 Fanout Simplified Model V in V out C L

The Miller Effect ΔV C gd1 V out V out ΔV V in ΔV 2C gd1 M1 ΔV V in M1 A capacitor experiencing identical but opposite voltage swings at both its terminals can be replaced by a capacitor to ground, whose value is two times the original value.

Computing the Capacitances

Design for Performance Keep capacitances small Increase transistor sizes watch out for self-loading! Increase V DD (????)

NMOS/PMOS ratio 5 x 10-11 tplh tphl 4.5 t p (sec) 4 tp β = W p /W n 3.5 3 1 1.5 2 2.5 3 3.5 4 4.5 5 β

Delay as a function of V DD 5.5 5 4.5 4 t p (normalized) 3.5 3 2.5 2 1.5 1 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 V DD (V)

Device Sizing 3.8 x 10-11 t p (sec) 3.6 3.4 3.2 3 2.8 2.6 2.4 2.2 2 (for fixed load) 2 4 6 8 10 12 14 S t p = 0.69R ref C iref (1+C ext /S.C iref ) t p = t po (1+C ext /S.C iref ) Self-loading effect: Intrinsic capacitances dominate

Impact of Rise Time on Delay 0.35 0.3 t phl (nsec) 0.25 0.2 0.15 0 0.2 0.4 0.6 t rise (nsec) 0.8 1

Inverter Sizing

Inverter Chain In Out C L If C L is given: - How many stages are needed to minimize the delay? - How to size the inverters? May need some additional constraints.

Inverter Delay Minimum length devices, L=0.25μm Assume that for W P = 2W N =2W same pull-up and pull-down currents approx. equal resistances R N = R P approx. equal rise t plh and fall t phl delays Analyze as an RC network 1 1 W R N unit W unit WP R P = Runit = RN = W unit R W 2W W Delay (D): t phl = (ln 2) R N C L Load for the next stage: W Cgin = 3 W t plh = (ln 2) R P C L unit C unit

Inverter with Load Delay R W C L R W Load (C L ) t p = kr W C L k is a constant, equal to 0.69 Assumptions: no load -> zero delay W unit = 1

Inverter with Load C P = 2C unit 2W Delay W C int C L C N = C unit Load Delay = kr W (C int + C L ) = kr W C int + kr W C L = kr W C int (1+ C L /C int ) = Delay (Internal) + Delay (Load)

Delay Formula Delay ~ R W ( C + C ) int L t p = kr W C int ( 1 + C / C ) = t ( 1 + f / γ ) L int p 0 C int = γc gin with γ 1 f = C L /C gin - effective fanout R = R unit /W ; C int =WC unit t p0 = 0.69R unit C unit

Apply to Inverter Chain In Out 1 2 N C L t p = t p1 + t p2 + + t pn C gin, j+ 1 t + pj ~ RunitCunit 1 γcgin, j N N C gin j t p = t p j = t, + 1, p0 1 +, Cgin N = j i C, + 1 = 1 = 1 γ gin, j C L

Optimal Tapering for Given N Delay equation has N - 1 unknowns, C gin,2 C gin,n Minimize the delay, find N - 1 partial derivatives Result: C gin,j+1 /C gin,j = C gin,j /C gin,j-1 Size of each stage is the geometric mean of two neighbors C gin, j = Cgin, j 1C gin, j+ 1 - each stage has the same effective fanout (C out /C in ) - each stage has the same delay

Optimum Delay and Number of Stages When each stage is sized by f and has same eff. fanout f: N f = F = C Effective fanout of each stage: L / Cgin,1 Minimum path delay p f = N F t = Nt + p0 ( 1 /γ ) N F

Example In C 1 1 f f 2 Out C L = 8 C 1 C L /C 1 has to be evenly distributed across N = 3 stages: f = 3 8 = 2

Optimum Number of Stages For a given load, C L and given input capacitance C in Find optimal sizing f t p = Nt t C f p0 p L = F C t ln F f γ ln f f 1 γ f = 0 2 ln f γ ln f ( 1/ N ) p0 F / γ + 1 = + = t p0 ln γ F ln For γ = 0, f = e, N = lnf in = f N C with N = in f ln ln F f = exp 1+ ( γ f )

Optimum Effective Fanout f Optimum f for given process defined by γ f = exp 1+ ( γ f ) f opt = 3.6 for γ=1

Impact of Self-Loading on tp No Self-Loading, γ=0 With Self-Loading γ=1 60.0 u/ln(u) 40.0 x=10,000 x=1000 20.0 x=100 x=10 0.0 1.0 3.0 5.0 7.0 u

Normalized delay function of F t = Nt + p p0 ( 1 /γ ) N F

Buffer Design N f t p 1 64 1 64 65 1 8 64 2 8 18 1 4 16 64 3 4 15 1 64 2.8 8 22.6 4 2.8 15.3