Chapter 6 The CMOS Inverter 1
Contents Introduction (MOST models) 0, 1 st, 2 nd order The CMOS inverter : The static behavior: o DC transfer characteristics, o Short-circuit current The CMOS inverter : The dynamic behavior Energy, power, and energy delay 2
Introduction - 1 Zero-order model (ideal switch) of n- and p-channel MOSFETs What for a signal between 0 and 1? Inverter Source: Weste & Harris 3
Introduction - 2 First-order model of a MOSFET Non ideal switch An MOS Transistor V GS V T S Ron D V GS What s the value of R on? Abrupt transition from on to off? 4
Introduction - 3 The MOS Transistor Polysilicon Aluminum 5
Introduction - 4 MOS Transistors n- and p-channel D D G G B In general connected to GND S NMOS S Enhancement D G G B In general connected to S PMOS Enhancement 6
Introduction - 5 I-V Relations Long-channel n-most 6 x 10-4 VGS= 2.5 V G D I D I D (A) 5 4 3 Resistive Saturation VGS= 2.0 V V DS = V GS -V T S 2 VGS= 1.5 V 1 VGS= 1.0 V VGS< 0.5 V 0 0 0.5 1 1.5 2 2.5 V DS (V) 7
Introduction - 6 I-V Relations Long-channel p-most 6 x 10-4 5 VGS=- 2.5 V S 4 Resistive Saturation VGS= -2.0 V G I D (A) 3 I D V DS = V GS -V T D 2 VGS= -1.5 V 1 VGS= -1.0 V VGS>- 0.5 V 0 0 0.5 1 1.5 2 2.5 -V DS (V) 8
Introduction - 7 9
Introduction - 8 I D versus V GS Saturation mode: V DS >V GS -V T 6 x 10-4 5 V DS =2.5 V V T = 0.5 V constant I D (A) 4 3 quadratic 2 1 0 0 0.5 1 1.5 2 2.5 V GS (V) 10
Introduction 9 Experimental setup - V GS S 1 + + G 2 B I D 1 - V DS + + - VDD = 3.3 V [0,3.3] step 0,5 V - D 3 + [0,3.3] step 0,050 V - 11
Introduction 9 An experiment Circuit description (SPICE) http://www.inf.ufsc.br/~santos/ine5442/experi ment/pmosa.cir Steps http://www.inf.ufsc.br/~santos/ine5442/experi ment/roteiro.txt 12
Introduction 10 Simulation 6.1a lambda = 0.1 V GS =-3.3 V V GS =-2.8 V V GS =-2.3 V V GS =-1.8 V V GS =-1.3 V 13
Introduction - 12 The Transistor as a Switch I D V GS = V GS V T S Ron D I DSAT R mid R 0 1 Req R0 + R 2 ( ) mid /2 V DS KP W I V V 2 L ( ) 2 DSAT DD T 14
Introduction - 13 CMOS static logic the beginning 15
Introduction - 14 CMOS static logic the beginning 16
Introduction - 15 CMOS device structure from Frank Wanlass's patent drawing. U. S. Patent Office. 17
Introduction - 16 Schematic and layout -1 N Well PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND 18
Introduction - 17 Schematic and layout -2 19
Static characteristics - 1 R p V in C L R n V in NMOS PMOS 0 OFF ON ON OFF V in = V in = 0 VGSn = VDD > VTn VGSn = 0 < VTn V = 0 > V V = V < V GSp Tp GSp DD Tp 0 20
Static characteristics - 1 R p V in C L R n V in NMOS PMOS 0 OFF ON ON OFF V in = V in = 0 VGSn = VDD > VTn VGSn = 0 < VTn V = 0 > V V = V < V GSp Tp GSp DD Tp 0 21
Static characteristics - 1 R p V in C L R n V in NMOS PMOS 0 OFF ON ON OFF V in = V in = 0 VGSn = VDD > VTn VGSn = 0 < VTn V = 0 > V V = V < V GSp Tp GSp DD Tp 0 22
Static characteristics - 2 V in C L Voltage swing is equal to the supply voltage; Logic levels are not dependent upon the relative device sizes; In steady state there always exists a path with finite resistance between the output and either or ground; The input resistance ; No direct path exists between supply and ground rails under steady-state operating conditions (this is first order approx. and is far from reality in more advanced technologies) static power 0 23
Static characteristics - 3 - PMOS Load Line I Dn V GSp + - V DSp V in = +V GSp I Dn = - I Dp V in I Dp + = +V DSp I Dn CL I Dp =2.5 V V in =0 I Dn I Dn V in =0 V in =1.5 V in =1.5 V GSp =-1 V DSp V DSp 2.5 V GSp =-2.5 V in = +V GSp I Dn = - I Dp = +V DSp 24
Static characteristics - 4 VTC V in - V GSp + I Dp I Dn - V DSp + IDn Vin= 1.5 Vin= 2 Vin= 2.5 Vin= 0 0.5 PMOS 1 1.5 NMOS 1.5 1 Vin= 2.5 2 Vin= 1 Vin= 0.5 Vin= 0 0.5 1 1.5 2 2.5 NMOS off PMOS res NMOS sat PMOS res NMOS sat PMOS sat NMOS res PMOS sat Vout NMOS res PMOS off 0.5 1 1.5 2 2.5 V in 25