CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates epartment of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe57-4f Course dministration Instructor: T: Labs: URL: Text: leksandar Milenkovic milenka@ece.uah.edu www.ece.uah.edu/~milenka E 7-L Office Hrs: MW 9:-: Fathima Tareen tareenf@eng.uah.edu ccounts on Solaris machines, Lab# is on http://www.ece.uah.edu/~milenka/cpe57-4f nalysis and esign of igital ICs, 3 rd Edition Hodges et. al., 4 Previous: IC Fabrication (slides, Chapter 3) Today: MOS Transistors (slides, Chapter ) 9/8/4 VLSI esign I;. Milenkovic CMOS Inverter: First Look V in V out 9/8/4 VLSI esign I;. Milenkovic 3
CMOS Inverter: Steady State Response V OL = V OH = V M = f(r n, R p ) R p V out = V out = R n V in = V in = 9/8/4 VLSI esign I;. Milenkovic 4 CMOS Properties Full rail-to-rail swing high noise margins Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless lways a path to V dd or in steady state low output impedance (output resistance in kω range) large fan-out (albeit with degraded performance) Extremely high input resistance (gate of MOS transistor is near perfect insulator) nearly zero steady-state input current No direct path steady-state between power and ground no static power dissipation Propagation delay function of load capacitance and resistance of transistors 9/8/4 VLSI esign I;. Milenkovic 5 Review: Short Channel I-V Plot (NMOS) I ().5.5.5 X -4 V GS =.5V V GS =.V V GS =.5V V GS =.V Linear dependence.5.5.5 V S (V) NMOS transistor,.5um, L d =.5um, W/L =.5, =.5V, V T =.4V 9/8/4 VLSI esign I;. Milenkovic 6
Short Channel I-V Plot (PMOS) ll polarities of all voltages and currents are reversed - V S (V) - V GS = -.V V GS = -.5V V GS = -.V -. -.4 -.6 I () -.8 V GS = -.5V - X -4 PMOS transistor,.5um, L d =.5um, W/L =.5, =.5V, V T = -.4V 9/8/4 VLSI esign I;. Milenkovic 7 Transforming PMOS I-V Lines Want common coordinate set V in, V out, and I n I Sp = -I Sn V GSn = V in ; V GSp = V in - V Sn = V out ; V Sp = V out - I n Vout V in = V in =.5 V in = V in =.5 V GSp = - V GSp = -.5 Mirror around x-axis V in = + V GSp I n = -I p Horiz. shift over V out = + V Sp 9/8/4 VLSI esign I;. Milenkovic 8 CMOS Inverter Load Lines PMOS.5 V in = V V in =.5V.5 X -4 NMOS V in =.5V V in =.V I n () V in =.V V in =.5V V V in =.5V in = V V in = V V in =.5V.5 V in =.5V V in =.V V in =.V V in =.5V V in =.5V.5.5.5 V in = V.5um, W/L n =.5, W/L p = 4.5, =.5V, V Tn =.4V, V Tp = -.4V 9/8/4 VLSI esign I;. Milenkovic 9
CMOS Inverter VTC.5.5.5.5.5.5 V in (V) 9/8/4 VLSI esign I;. Milenkovic CMOS Inverter VTC NMOS off PMOS res.5.5 NMOS sat PMOS res NMOS sat PMOS sat.5 NMOS res PMOS sat NMOS res PMOS off.5.5.5 V in (V) 9/8/4 VLSI esign I;. Milenkovic CMOS Inverter: Switch Model of ynamic ehavior R p V out V out R n V in = V in = 9/8/4 VLSI esign I;. Milenkovic
CMOS Inverter: Switch Model of ynamic ehavior R p V out V out R n V in = V in = Gate response time is determined by the time to charge through R p (discharge through R n ) 9/8/4 VLSI esign I;. Milenkovic 3 Relative Transistor Sizing When designing static CMOS circuits, balance the driving strengths of the transistors by making the PMOS section wider than the NMOS section to maximize the noise margins and obtain symmetrical characteristics 9/8/4 VLSI esign I;. Milenkovic 4 Switching Threshold V M where V in = V out (both PMOS and NMOS in saturation since V S = V GS ) V M r /( + r) where r = k p V STp /k n V STn Switching threshold set by the ratio r, which compares the relative driving strengths of the PMOS and NMOS transistors Want V M = / (to have comparable high and low noise margins), so want r (W/L) p k n V STn (V M -V Tn -V STn /) (W/L) n = k p V STp ( -V M +V Tp +V STp /) 9/8/4 VLSI esign I;. Milenkovic 5
Switch Threshold Example In our generic.5 micron CMOS process, using the process parameters from slide L3.5, a =.5V, and a minimum size NMOS device ((W/L) n of.5) NMOS PMOS V T (V).43 -.4 γ(v.5 ).4 -.4 V ST (V).63 - k (/V ) 5 x -6-3 x -6 λ(v - ).6 -. (W/L) p (W/L) n = 9/8/4 VLSI esign I;. Milenkovic 6 Switch Threshold Example In our generic.5 micron CMOS process, using the process parameters, a =.5V, and a minimum size NMOS device ((W/L) n of.5) NMOS PMOS V T (V).43 -.4 γ(v.5 ).4 -.4 V ST (V).63 - k (/V ) 5 x -6-3 x -6 λ(v - ).6 -. (W/L) p 5 x -6.63 (.5.43.63/) = (W/L) n -3 x -6 x x = 3.5 -. (.5.4./) (W/L) p = 3.5 x.5 = 5.5 for a V M of.5v 9/8/4 VLSI esign I;. Milenkovic 7 Simulated Inverter V M V M (V).5.4.3...9.8. ~3.4 (W/L) p /(W/L) n Note: x-axis is semilog V M is relatively insensitive to variations in device ratio setting the ratio to 3,.5 and gives V M s of.v,.8v, and.3v Increasing the width of the PMOS moves V M towards Increasing the width of the NMOS moves V M toward 9/8/4 VLSI esign I;. Milenkovic 8
Noise Margins etermining V IH and V IL 3 y definition, V IH and V IL are where dv out /dv in = - (= gain) V OH = V out V OL = VIL V M V in piece-wise linear approximation of VTC VIH NM H = - V IH NM L = V IL - pproximating: V IH = V M - V M /g V IL = V M + ( - V M )/g So high gain in the transition region is very desirable 9/8/4 VLSI esign I;. Milenkovic 9.5.5.5 CMOS Inverter VTC from Simulation.5.5.5 V in (V).5um, (W/L) p /(W/L) n = 3.4 (W/L) n =.5 (min size) =.5V V M.5V, g = -7.5 V IL =.V, V IH =.3V NM L = NM H =. (actual values are V IL =.3V, V IH =.45V NM L =.3V & NM H =.5V) Output resistance low-output =.4kΩ high-output = 3.3kΩ 9/8/4 VLSI esign I;. Milenkovic Gain eterminates gain - -4-6 -8 - - -4-6 -8 V in.5.5 Gain is a strong function of the slopes of the currents in the saturation region, for V in = V M (+r) g ---------------------------------- (V M -V Tn -V STn /)(λ n - λ p ) etermined by technology parameters, especially channel length modulation (λ). Only designer influence through supply voltage and V M (transistor sizing). 9/8/4 VLSI esign I;. Milenkovic
Impact of Process Variation on VTC Curve.5.5.5 ad PMOS Good NMOS.5.5.5 V in (V) Good PMOS ad NMOS Nominal process variations (mostly) cause a shift in the switching threshold 9/8/4 VLSI esign I;. Milenkovic Scaling the Supply Voltage.5..5.5.5 Gain=-.5..5..5 V in (V).5.5 V in (V) evice threshold voltages are evice threshold voltages are kept (virtually) constant kept (virtually) constant 9/8/4 VLSI esign I;. Milenkovic 3..5 Static CMOS Logic
CMOS Circuit Styles Static complementary CMOS - except during switching, output connected to either V or via a lowresistance path high noise margins full rail to rail swing VOH and VOL are at V and, respectively low output impedance, high input impedance no steady state path between V and (no static power consumption) delay a function of load capacitance and transistor resistance comparable rise and fall times (under the appropriate transistor sizing conditions) ynamic CMOS - relies on temporary storage of signal values on the capacitance of high-impedance circuit nodes simpler, faster gates increased sensitivity to noise 9/8/4 VLSI esign I;. Milenkovic 5 Static Complementary CMOS Pull-up network (PUN) and pull-down network (PN) In In In N In In In N PUN PN PMOS transistors only pull-up: make a connection from to F when F(In,In, In N ) = F(In,In, In N ) pull-down: make a connection from F to when F(In,In, In N ) = NMOS transistors only PUN and PN are dual logic networks 9/8/4 VLSI esign I;. Milenkovic 6 Threshold rops PUN PN 9/8/4 VLSI esign I;. Milenkovic 7
Threshold rops PUN S V GS S - V Tn PN V Tp V GS S S 9/8/4 VLSI esign I;. Milenkovic 8 Construction of PN NMOS devices in series implement a NN function NMOS devices in parallel implement a NOR function + 9/8/4 VLSI esign I;. Milenkovic 9 ual PUN and PN PUN and PN are dual networks emorgan s theorems + = = + [!( + ) =!! or!( ) =! &!] [!( ) =! +! or!( & ) =!!] a parallel connection of transistors in the PUN corresponds to a series connection of the PN Complementary gate is naturally inverting (NN, NOR, OI, OI) Number of transistors for an N-input logic gate is N 9/8/4 VLSI esign I;. Milenkovic 3
CMOS NN F 9/8/4 VLSI esign I;. Milenkovic 3 CMOS NN NN F = NN(,) F = F= = F= = F= = F= = = = = 9/8/4 VLSI esign I;. Milenkovic 3 CMOS NOR + F 9/8/4 VLSI esign I;. Milenkovic 33
CMOS NOR NOR F = NOR(,) F = = = = = = = = F= F= F= F= 9/8/4 VLSI esign I;. Milenkovic 34 Complex CMOS Gate OUT =!( + ( + C)) C 9/8/4 VLSI esign I;. Milenkovic 35 Complex CMOS Gate C OUT =!( + ( + C)) C 9/8/4 VLSI esign I;. Milenkovic 36