DM Bit Addressable Latch

Similar documents
DM7404 Hex Inverting Gates

DM74LS75 Quad Latch. DM74LS75 Quad Latch. General Description. Ordering Code: Connection Diagram. Logic Diagram. Function Table (Each Latch)

DM74LS670 3-STATE 4-by-4 Register File

DM7417 Hex Buffers with High Voltage Open-Collector Outputs

9334 DM Bit Addressable Latch

DM74LS02 Quad 2-Input NOR Gate

DM Quad 2-Input NAND Buffers with Open-Collector Outputs

DM74LS08 Quad 2-Input AND Gates


DM74LS09 Quad 2-Input AND Gates with Open-Collector Outputs

DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs

DM74S373 DM74S374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

DM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear

DM7490A Decade and Binary Counter

DM74LS373 DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

DM7446A, DM7447A BCD to 7-Segment Decoders/Drivers

DM74LS05 Hex Inverters with Open-Collector Outputs

93L34 8-Bit Addressable Latch

CD4028BC BCD-to-Decimal Decoder

74F139 Dual 1-of-4 Decoder/Demultiplexer

74F194 4-Bit Bidirectional Universal Shift Register

DM74LS244 Octal 3-STATE Buffer/Line Driver/Line Receiver

DM74LS154 4-Line to 16-Line Decoder/Demultiplexer

CD4514BC CD4515BC 4-Bit Latched/4-to-16 Line Decoders

CD4028BC BCD-to-Decimal Decoder

54LS256 DM74LS256 Dual 4-Bit Addressable Latch

DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

74F153 Dual 4-Input Multiplexer

DM7445 BCD to Decimal Decoders/Drivers

74F175 Quad D-Type Flip-Flop

74F30 8-Input NAND Gate

MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder

74F109 Dual JK Positive Edge-Triggered Flip-Flop

DM7442A BCD to Decimal Decoders

74F174 Hex D-Type Flip-Flop with Master Reset

DM54LS259 DM74LS259 8-Bit Addressable Latches

MM74C85 4-Bit Magnitude Comparator

74F537 1-of-10 Decoder with 3-STATE Outputs

74F379 Quad Parallel Register with Enable

DM74LS138, DM74LS139 Decoders/Demultiplexers

CD4024BC 7-Stage Ripple Carry Binary Counter

DM74LS90/DM74LS93 Decade and Binary Counters

CD4013BC Dual D-Type Flip-Flop

CD4511BC BCD-to-7 Segment Latch/Decoder/Driver

MM74HC139 Dual 2-To-4 Line Decoder

CD40174BC CD40175BC Hex D-Type Flip-Flop Quad D-Type Flip-Flop

CD4049UBC CD4050BC Hex Inverting Buffer Hex Non-Inverting Buffer

CD4528BC Dual Monostable Multivibrator

DM74LS240 DM74LS241 Octal 3-STATE Buffer/Line Driver/Line Receiver

MM74HC138 3-to-8 Line Decoder

MM74HCT138 3-to-8 Line Decoder

CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset

CD4071BC CD4081BC Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate

DM74LS11 Triple 3-Input AND Gates

DM74LS02 Quad 2-Input NOR Gates

MM74HC164 8-Bit Serial-in/Parallel-out Shift Register

MM74HC154 4-to-16 Line Decoder


Excellent Integrated System Limited

MM74HC4020 MM74HC Stage Binary Counter 12-Stage Binary Counter

Low Power Quint Exclusive OR/NOR Gate

DM74LS174/DM74LS175 Hex/Quad D Flip-Flops with Clear

9312 DM9312 One of Eight Line Data Selectors Multiplexers

CD4021BC 8-Stage Static Shift Register

CD40106BC Hex Schmitt Trigger

74F539 Dual 1-of-4 Decoder with 3-STATE Outputs

MM74HC175 Quad D-Type Flip-Flop With Clear

MM74C908 Dual CMOS 30-Volt Relay Driver

9321 DM9321 Dual 1-of-4 Decoder

74ACT825 8-Bit D-Type Flip-Flop

74LS75 Quad Latch. DM74LS75 Quad Latch. General Description. Ordering Code: Logic Diagram. Connection Diagram. Function Table (Each Latch)

MM74C90 MM74C93 4-Bit Decade Counter 4-Bit Binary Counter

74F Bit Random Access Memory with 3-STATE Outputs

MM74HCT08 Quad 2-Input AND Gate

MM74C912 6-Digit BCD Display Controller/Driver

CD4093BC Quad 2-Input NAND Schmitt Trigger

74F139 Dual 1-of-4 Decoder/Demultiplexer

MM74HC00 Quad 2-Input NAND Gate

MM74HC08 Quad 2-Input AND Gate

MM74C00 MM74C02 MM74C04 Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter

MM74HC161 MM74HC163 Synchronous Binary Counter with Asynchronous Clear Synchronous Binary Counter with Synchronous Clear

CD4723BM CD4723BC Dual 4-Bit Addressable Latch CD4724BM CD4724BC 8-Bit Addressable Latch

DM74LS375 4-Bit Latch

74AC08 74ACT08 Quad 2-Input AND Gate

DM74LS181 4-Bit Arithmetic Logic Unit

MM74HC573 3-STATE Octal D-Type Latch

MM74HC32 Quad 2-Input OR Gate

74F138 1-of-8 Decoder/Demultiplexer

74AC138 74ACT138 1-of-8 Decoder/Demultiplexer

MM82C19 16-Line to 1-Line Multiplexer

54153 DM54153 DM74153 Dual 4-Line to 1-Line Data Selectors Multiplexers

MM74C906 Hex Open Drain N-Channel Buffers

54LS85 DM54LS85 DM74LS85 4-Bit Magnitude Comparators

MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop

74F Bit D-Type Flip-Flop

MM74C14 Hex Schmitt Trigger

54LS352 DM74LS352 Dual 4-Line to 1-Line Data Selectors Multiplexers

MM74HC251 8-Channel 3-STATE Multiplexer

MM74HC244 Octal 3-STATE Buffer

MM74C00 MM74C02 MM74C04 Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter

Transcription:

8-Bit Addressable Latch General Description The DM9334 is a high speed 8-bit Addressable Latch designed for general purpose storage applications in digital systems. It is a multifunctional device capable of storing single line data in eight addressable latches, and being a one-of-eight decoder and demultiplexer with active level HIGH outputs. The device also incorporates an active level LOW common clear for resetting all latches, as well as an active level LOW enable. The DM9334 has four modes of operation which are shown in the mode selection table. In the addressable latch mode, data on the data line (D) is written into the addressed latch. The addressed latch will follow the data input with all nonaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous state and are unaffected by the data or address inputs. In the one-of-eight decoding or demultiplexing mode, the addressed output will follow the state of the D input with all other inputs in the LOW state. In the clear mode all outputs are LOW and unaffected by the address and data inputs. When operating the device as an addressable latch, changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode. The function tables summarize the operation of the product. Features August 1986 Revised July 2001 Common clear Easily expandable Random (addressable) data entry Serial to parallel capability 8 bits of storage/output of each bit available Active high demultiplexing/decoding capability DM9334 8-Bit Addressable Latch Ordering Code: Order Number Package Number Package Description DM9334N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Connection Diagram 2001 Fairchild Semiconductor Corporation DS006609 www.fairchildsemi.com

Function Tables E C Mode L H Addressable Latch H H Memory L L Active HIGH Eight Channel Demultiplexer H L Clear Inputs Present Output States Mode C E D A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 L H X X X X L L L L L L L L Clear L L L L L L L L L L L L L L Demultiplex L L H L L L H L L L L L L L L L L H L L L L L L L L L L L L H H L L L H L L L L L L L L H H H H L L L L L L L H H H X X X X Q N 1 Memory H L L L L L L Q N 1 Q N 1 Q N 1 Addressable H L H L L L H Q N 1 Q N 1 Latch H L L H L L Q N 1 L Q N 1 H L H H L L Q N 1 H Q N 1 H L L H H H Q N 1 Q N 1 L H L H H H H Q N 1 Q N 1 H H = HIGH Voltage Level L = LOW Voltage Level X = Don t Care Condition Q N 1 = Previous Output State Logic Diagram www.fairchildsemi.com 2

Absolute Maximum Ratings(Note 1) Supply Voltage 7V Input Voltage 5.5V Operating Free Air Temperature Range 0 to +70 C Storage Temperature Range 65 C to +150 C Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation. DM9334 Recommended Operating Conditions Symbol Parameter Min Nom Max Units V CC Supply Voltage 4.75 5 5.25 V V IH HIGH Level Input Voltage 2 V V IL LOW Level Input Voltage 0.8 V I OH HIGH Level Output Current 0.8 ma I OL LOW Level Output Current 16 ma t W ENABLE Pulse Width (Figure 1) (Note 3) 19 13 ns t SU Setup Time Data 1 (Figure 5) 20 13 (Note 3) Data 0 (Figure 5) 20 14 Address (Figure 6) 10 5 ns (Note 2) t H Hold Time Data 1 (Figure 5) 0 10 (Note 3) Data 0 (Figure 5) 0 13 ns T A Free Air Operating Temperature 0 70 C Note 2: The ADDRESS setup time is the time before the negative ENABLE transition that the ADDRESS must be stable so that the correct latch is addressed without affecting the other latches. Note 3: T A = 25 C and V CC = 5V. Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Typ Symbol Parameter Conditions Min (Note 4) Max Units V I Input Clamp Voltage V CC = Min, I I = 12 ma 1.5 V V OH HIGH Level V CC = Min, I OH = Max Output Voltage V IL = Max, V IH = Min 2.4 3.6 V V OL LOW Level V CC = Min, I OL = Max Output Voltage V IH = Min, V IL = Max 0.2 0.4 V I I Input Current @ Max Input Voltage V CC = Max, V I = 5.5V 1 ma I IH HIGH Level V CC = Max E Input 60 Input Current V I = 2.4V Others 40 µa I IL LOW Level V CC = Max E Input 2.4 Input Current V I = 0.4V Others 1.6 ma I OS Short Circuit Output Current V CC = Max (Note 5) 30 100 ma I CC Supply Current V CC = Max 56 86 ma Note 4: All typicals are at V CC = 5V, T A = 25 C. Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second. 3 www.fairchildsemi.com

Switching Characteristics at V CC = 5V and T A = 25 C From (Input) R L = 400Ω, C L = 15 pf Symbol Parameter Units To (Output) Min Max t PLH Propagation Delay Time Enable to Output, LOW-to-HIGH Level Output (Figure 1) 28 ns t PHL Propagation Delay Time Enable to Output, HIGH-to-LOW Level Output (Figure 1) 27 ns t PLH Propagation Delay Time Data to Output, LOW-to-HIGH Level Output (Figure 4) t PHL Propagation Delay Time Data to Output, HIGH-to-LOW Level Output (Figure 4) 28 ns t PLH Propagation Delay Time Address to Output, LOW-to-HIGH Level Output (Figure 2) t PHL Propagation Delay Time Address to Output, HIGH-to-LOW Level Output (Figure 2) t PHL Propagation Delay Time Clear to Output, HIGH-to-LOW Level Output (Figure 3) 31 ns Switching Time Waveforms Other Conditions: C = H, A = Stable FIGURE 1. Other Conditions: E = L, C = L, D = H FIGURE 2. Other Conditions: E = H FIGURE 3. Other Conditions: E = L, C = H, A = Stable FIGURE 4. Other Conditions: C = H, A = Stable FIGURE 5. Other Conditions: C = H Note: The shaded areas indicate when the inputs are permitted to change for predictable output performance. FIGURE 6. www.fairchildsemi.com 4

Physical Dimensions inches (millimeters) unless otherwise noted DM9334 8-Bit Addressable Latch 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 5 www.fairchildsemi.com