SN4H29, SN4H29 8-BIT ARESSABLE LATHES 8-Bit Parallel-Out Storage Register Performs Serial-to-Parallel onversion With Storage Asynchronous Parallel lear Active-High ecoder Enable Input Simplifies Expansion Expandable for n-bit Applications Four istinct Functional Modes Package Options Include Plastic Small-Outline (), Thin Shrink Small-Outline (PW), and eramic Flat (W) Packages, eramic hip arriers (FK), and Standard Plastic (N) and eramic (J) 00-mil IPs SN4H29...J OR W PAKAGE SN4H29..., N, OR PW PAKAGE (TOP VIEW) S0 S1 S2 Q0 Q1 Q2 Q GN 1 2 4 6 8 16 1 14 1 12 11 10 9 V LR G Q Q6 Q Q4 SN4H29... FK PAKAGE (TOP VIEW) description These 8-bit addressable latches are designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and active-high decoders or demultiplexers. They are multifunctional devices capable of storing single-line data in eight addressable latches, and being a 1-of-8 decoder or demultiplexer with active-high outputs. Four distinct modes of operation are selectable by controlling the clear (LR) and enable (G) inputs. In the addressable-latch mode, data at the data-in terminal is written into the addressed latch. The addressed latch follows the data input with all unaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data in the latches, G should be held high (inactive) while the address lines are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output follows the level of the input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address and data inputs. 4 2 1 20 19 18 6 1 16 1 8 14 9 10 11 12 1 The SN4H29 is characterized for operation over the full military temperature range of to 12. The SN4H29 is characterized for operation from 40 to 8. S2 Q0 N Q1 Q2 S1 S0 N Q GN N V Q4 Q LR N No internal connection G N Q Q6 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PROUTION ATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. opyright 199, Texas Instruments Incorporated POST OFFIE BOX 60 ALLAS, TEXAS 26 1
SN4H29, SN4H29 8-BIT ARESSABLE LATHES Function Tables FUNTION INPUTS OUTPUT OF EAH ARESSE OTHER FUNTION LR G LATH OUTPUT H L QiO Addressable latch H H QiO QiO Memory L L L 8-line demultiplexer L H L L lear LATH SELETION SELET INPUTS LATH S2 S1 S0 ARESSE L L L 0 L L H 1 L H L 2 L H H H L L 4 H L H H H L 6 H H H 2 POST OFFIE BOX 60 ALLAS, TEXAS 26
SN4H29, SN4H29 8-BIT ARESSABLE LATHES logic symbol S0 S1 S2 G LR 1 2 14 1 1 0 8M 0 2 G8 Z9 Z10 9, 0 10, 0R 9, 10, 9, 2 10, 2R 9, 10, R 9, 4 10, 4R 9, 10, R 9, 6 10, 6R 9, 10, R 4 6 9 10 11 12 Q0 Q1 Q2 Q Q4 Q Q6 Q This symbol is in accordance with ANSI/IEEE Std 91-1984 and IE Publication 61-12. Pin numbers shown are for the, J, N, PW, and W packages. POST OFFIE BOX 60 ALLAS, TEXAS 26
SN4H29, SN4H29 8-BIT ARESSABLE LATHES logic diagram (positive logic) S0 1 4 Q0 Q1 S1 2 6 Q2 S2 9 Q Q4 10 Q G LR 14 1 1 11 12 Q6 Q Pin numbers shown are for the, J, N, PW, and W packages. 4 POST OFFIE BOX 60 ALLAS, TEXAS 26
SN4H29, SN4H29 8-BIT ARESSABLE LATHES logic symbol, each internal latch R Q logic diagram, each internal latch (positive logic) TG Q TG R absolute maximum ratings over operating free-air temperature range Supply voltage range, V.......................................................... 0. V to V Input clamp current, I IK (V I < 0 or V I > V ) (see Note 1).................................... ±20 ma Output clamp current, I OK (V O < 0 or V O > V ) (see Note 1)................................ ±20 ma ontinuous output current, I O (V O = 0 to V ).............................................. ±2 ma ontinuous current through V or GN................................................... ±0 ma Package thermal impedance, θ JA (see Note 2): package.................................. 11 /W N package................................... 8 /W PW package................................ 149 /W Storage temperature range, T stg................................................... 6 to 10 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JES 1, except for through-hole packages, which use a trace length of zero. POST OFFIE BOX 60 ALLAS, TEXAS 26
SN4H29, SN4H29 8-BIT ARESSABLE LATHES recommended operating conditions SN4H29 SN4H29 MIN NOM MAX MIN NOM MAX UNIT V Supply voltage 2 6 2 6 V V = 2 V 1. 1. VIH High-level input voltage V = 4. V.1.1 V V = 6 V 4.2 4.2 V = 2 V 0 0. 0 0. VIL Low-level input voltage V = 4. V 0 1. 0 1. V V = 6 V 0 1.8 0 1.8 VI Input voltage V VO Output voltage V V = 2 V 0 1000 0 1000 tt Input transition (rise and fall) time V = 4. V 0 00 0 00 ns V = 6 V 0 400 0 400 TA Operating free-air temperature 12 40 8 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST ONITIONS V TA = 2 SN4H29 SN4H29 MIN TYP MAX MIN MAX MIN MAX 2 V 1.9 1.998 1.9 1.9 IOH = 20 µa 4. V 4.4 4.499 4.4 4.4 VOH VI = VIH or VIL 6 V.9.999.9.9 V IOH = 4 ma 4. V.98 4...84 IOH =.2 ma 6 V.48.8.2.4 2 V 0.002 0.1 0.1 0.1 IOL = 20 µa 4. V 0.001 0.1 0.1 0.1 VOL VI = VIH or VIL 6 V 0.001 0.1 0.1 0.1 V IOL = 4 ma 4. V 0.1 0.26 0.4 0. IOL =.2 ma 6 V 0.1 0.26 0.4 0. II VI = V or 0 6 V ±0.1 ±100 ±1000 ±1000 na I VI = V or 0, IO = 0 6 V 8 160 80 µa i 2 V to 6 V 10 10 10 pf UNIT 6 POST OFFIE BOX 60 ALLAS, TEXAS 26
SN4H29, SN4H29 8-BIT ARESSABLE LATHES timing requirements over recommended operating free-air temperature range (unless otherwise noted) tw Pulse duration V TA = 2 SN4H29 SN4H29 MIN MAX MIN MAX MIN MAX 2 V 80 120 100 LR low 4. V 16 24 20 6 V 14 20 1 2 V 80 120 100 G low 4. V 16 24 20 6 V 14 20 1 2 V 11 9 tsu Setup time, data or address before G 4. V 1 2 19 ns 6 V 1 20 16 2 V th Hold time, data or address after G 4. V ns 6 V UNIT ns switching characteristics over recommended operating free-air temperature range, L = 0 pf (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) V TA = 2 SN4H29 SN4H29 MIN TYP MAX MIN MAX MIN MAX 2 V 60 10 22 190 tphl LR Any Q 4. V 18 0 4 8 ns 6 V 14 26 8 2 2 V 6 10 19 16 ata Any Q 4. V 1 26 9 6 V 1 22 28 2 V 4 200 00 20 tpd Address Any Q 4. V 21 40 60 0 ns 6 V 1 4 1 4 2 V 66 10 2 21 G Any Q 4. V 20 4 1 4 6 V 16 29 4 2 V 28 110 9 tt Any 4. V 8 1 22 19 ns 6 V 6 1 19 16 UNIT operating characteristics, T A = 2 PARAMETER TEST ONITIONS TYP UNIT pd Power dissipation capacitance per latch No load pf POST OFFIE BOX 60 ALLAS, TEXAS 26
SN4H29, SN4H29 8-BIT ARESSABLE LATHES PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point L = 0 pf (see Note A) High-Level Pulse Low-Level Pulse tw V V LOA IRUIT VOLTAGE WAVEFORMS PULSE URATIONS Input V tplh tphl Reference Input ata Input 10% tsu th 90% 90% tr V V 10% tf In-Phase Output Out-of-Phase Output 10% tphl 90% 90% 90% tr 10% 10% tf tplh VOH 10% VOL tf VOH 90% VOL tr VOLTAGE WAVEFORMS SETUP AN HOL AN INPUT RISE AN FALL TIMES VOLTAGE WAVEFORMS PROPAGATION ELAY AN OUTPUT TRANSITION TIMES NOTES: A. L includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 0 Ω, tr = 6 ns, tf = 6 ns.. The outputs are measured one at a time with one input transition per measurement.. tplh and tphl are the same as tpd. Figure 1. Load ircuit and Voltage Waveforms 8 POST OFFIE BOX 60 ALLAS, TEXAS 26
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