Semiconductor Memories: an Introduction ti
Talk Overview Memory Trend Memory Classification Memory Architectures The Memory Core Periphery Reliability
Semiconductor Memory Trends (up to the 90 s) Memory Size as a function of time: x 4 every three years
Semiconductor Memory Trends (Updated d Further Beyond)
Trends in Memory Cell Area
Growth in DRAM Chip Capacity 1000000 256,000 100000 64,000 Kbit ca apacity 10000 1000 1,000 4,000 16,000 256 100 64 10 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 Year of introduction
Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) DRAM FIFO FLASH SRAM LIFO Shift Register CAM MRAM PRAM RRAM
Memory Timing: Definitions Read cycle READ Read access Read access Write cycle WRITE Data valid Write access DATA Data written
Memory Architecture: Decoders Intuitive architecture for n x m memory Too many select signals: N words == N select signals m bits m bits S 0 Word 0 Word 0 S 1 Word 1 S 1 Word 1 S 2 S 3 Word 2 Storage Cell A 0 A 1 S 0 S 2 S 3 Word 2 Storage Cell A k-1 S n-2 S n-1 Word n-2 Word n-1 S n-2 S n-1 Word n-2 Word n-1 Input/Output n words n select signals Input/Output Decoder reduces # of inputs k = log 2 n
Array-Structured Memory Architecture bit line 2 k-j word line A j A j+1 A k-1 storage (RAM) cell A 0 A 1 A j-1 Column Decoder Sense Amplifiers Read/Write Circuits m2 j selects appropriate word from memory row amplifies bit line swing Input/Output (m bits)
Hierarchical Memory Architecture Row address Block 0 Block i Block P 2-1 Column address Block address Control circuitry Block selector Global amplifier/driver Global data bus Advantages: 1. Shorter wires within blocks for reduced local transit times 2. Block address activates only 1 block for power savings I/O
Block Diagram of 4 Mbit SRAM Clock Z-address X-address generator buffer buffer Predecoder and block selector Bit line load Sub-glob bal row dec Global l row dec Sub-glob al row dec Transfer gate Column decoder Sense amplifier and write driver Local row dec CS, WE buffer I/O buffer x1/x4 controller Y-address buffer X-address buffer
Memory Timing: Approaches Address bus Row Address Column Address RAS CAS Address Bus Address Address transition initiates memory operation RAS-CAS timing DRAM Timing: Multiplexed l dadressing SRAM Timing: Self-timed
Read-Only Memory Cells BL BL BL 1 WL WL V DD WL BL BL BL 0 WL WL WL GND Diode ROM MOS ROM 1 MOS ROM 2
MOS OR ROM BL[0] BL[1] BL[2] BL[3] WL[0] V DD WL[1] WL[2] V DD WL[3] V bias Pull-down loads
MOS NOR ROM V DD Pull-up devices WL[0] WL [1] GND WL [2] GND WL [3] BL [0] BL [1] BL [2] BL [3]
MOS NAND ROM V DD Pull-up devices BL[0] BL[1] BL[2] BL[3] WL[0] WL[1] WL[2] WL[3] All word lines high h by default with exception of selected row
Equivalent Transient Model for MOS NOR ROM V DD BL WL r word C bit c word Word line parasitics Wire capacitance and gate capacitance Wire resistance (polysilicon) Bit line parasitics ii Resistance not dominant (metal) Drain junction and gate-drain overlap capacitance
Equivalent Transient Model for MOS NAND ROM V DD BL rbit C L WL r word c bit c word Word line parasitics Similar to NOR ROM Bit line parasitics Resistance of cascaded transistors dominates. Drain/source and complete gate capacitances
Decreasing Word Line Delay Drive the word line from both sides WL driver polysilicon word line metal word line driver Use a metal bypass polysilicon word line WL Use silicides metal bypass
Precharged MOS NOR ROM f pre V DD Precharge devices WL [0] WL [1] GND WL [2] GND WL [3] BL [0] BL [1] BL [2] BL [3] PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design.
Non-Volatile Memories The Floating-gate gate transistor (FAMOS) Source Floating gate Gate Drain D t ox G n + p t ox n +_ S Substrate Device cross-sectionsection Schematic symbol
Floating-Gate Transistor Programming 20 V 0 V 5 V 10 V 5 V 20 V 5 V 0 V 2.5 V 5 V S D S D S D Avalanche injection Removing programming Programming results in voltage leaves charge trapped. higherh V T.
A Programmable-Threshold Transistor I D 0 -state 1 -state ON ΔDV Δ T OFF V WL V GS
Floating-Gate Tunneling Oxide (FLOTOX) EEPROM Floating gate Gate I Source Drain 20 30 nm -10 V V GD 10 V n + 1 p n 1+ Substrate 10 nm FLOTOX transistor Fowler-Nordheim I-V characteristic
EEPROM Cell BL WL V DD Absolute threshold control is hard, and nonprogrammed transistor might be in depletion. 2-transistor cell (one serving as the access transistor)
Flash EEPROM Control gate Floating gate erasure Thin tunneling oxide n + 1 source programming n + 1 drain p-substrate Erasure using Fowler-Nordheim tunneling is performed in bulk for the complete chip or in a sub-section of the memory.
Cross-sections sections of NVM cells Flash EPROM Courtesy Intel
Basic Operations in a NOR Flash Memory Erase cell array BL 0 BL 1 12 V G 0 V WL 0 S D 12 V 0 V WL 1 open open
Basic Operations in a NOR Flash Memory Write 12 V BL 0 BL 1 G 6 V 12 V WL 0 S D 0 V 0V WL 1 6 V 0 V
Basic Operations in a NOR Flash Memory Read 5 V G 1V 5 V BL 0 BL 1 WL 0 S D 0 V 0V WL 1 1V 0V
NAND Flash Memory Word line(poly) Unit Cell Gate ONO Gate Oxide FG Source line (Diff. Layer) Courtesy Toshiba
NAND Flash Memory Select transistor Word lines Active area STI Bit line contact Source line contact
Read-Write Memories (RAM) STATIC (SRAM) Data stored as long as power supply is applied Large (6 transistors/cell) Fast Differential DYNAMIC (DRAM) Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended
6-transistor CMOS SRAM Cell WL V DD M 2 M 4 Q M Q M 5 6 M 1 M 3 BL BL
CMOS SRAM Analysis (Read) WL BL V DD M 4 Q = 0 M 6 M 5 Q = 1 BL V DD M 1 V DD V DD C bit C bit
CMOS SRAM Analysis (Read) 12 1.2 ise, ΔV (V) 1 0.8 0.6 Vo oltage Ri 0.4 0.2 0 0 0.5 1 1.2 1.5 2 2.5 3 Cell Ratio (CR)
CMOS SRAM Analysis (Write) V DD WL Q = 0 M 4 M6 6 M 5 Q = 1 M 1 V DD BL = 1 BL = 0
CMOS SRAM Analysis (Write) PR W 4 / L 4 W 6 / L 6
Resistance-load SRAM Cell V DD WL R L R L M 3 Q Q M 4 BL M 1 M 2 BL Static power dissipation -- Want R L large Bit lines precharged to V DD to address t p problem
3-Transistor DRAM Cell BL1 BL2 WWL RWL WWL M 3 RWL M 1 X M 2 X - V DD 2 V T C S BL 1 V DD BL 2 V DD 2 - V T ΔD V No constraints on device ratios Reads are non-destructive. Value stored at node X when writing a 1 = V WWL-V Tn
1-Transistor DRAM Cell WL BL WL Write 1 Read 1 M 1 X C S X GND V DD 2- V T BL V DD V DD /2 V sensing DD /2 C BL Write: C S is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance Voltage swing is small, typically around 250 mv. C S ΔV = V = ------------ BL V PRE (V X V PRE ) C S + C BL
DRAM Cell Observations 1T DRAM requires a sense amplifier for each bit line due to charge redistribution ib ti read-out. The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. DRAM memory cells are single-ended in contrast to SRAM cells. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a 1 into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than V DD.
Sense Amplifier Operation V BL V(1) V PRE DΔD Δ V(1) Sense amp activated p Word line activated V(0) t
1-T DRAM Cell Capacitor Metal word line Poly n + n + Inversion layer Poly induced by plate bias Cross-section SiO 2 Field Oxide Diffused bit line Polysilicon gate Layout Polysilicon plate M 1 word line Uses Polysilicon-Diffusion Capacitance Expensive in Area
Advanced 1T DRAM Cells Word line Insulating Layer Cell plate Capacitor dielectric layer Cell Plate Si Capacitor Insulator Refilling Poly Transfer gate Isolation Storage electrode Storage Node Poly 2nd Field Oxide Si Substrate Trench Cell Stacked Cell
Row Decoders Collection of 2 M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder
Hierarchical Decoders Multi-stage implementation improves performance WL 1 WL 0 A 0 A 1 A 0 A 1 A 0 A 1 A 0 A 1 A 2 A 3 A 2 A 3 A 2 A 3 A 2 A 3 A 1 A 0 A 0 A 1 A 3 A 2 A 2 A 3 NAND decoder using 2-input pre-decoders
Dynamic Decoders Precharge devices GND GND V DD WL 3 V DD WL 3 WL 2 V DD WL 2 WL 1 WL 0 V DD WL 1 WL 0 V DD φ A 0 A 0 A 1 A 1 A 0 A 0 A 1 A 1 φ 2-input NOR decoder 2-input NAND decoder
4-to-1 tree based column decoder BL 0 BL 1 BL 2 BL 3 A 0 A 0 A 1 A 1 D Number of devices drastically reduced Delay increases quadratically with # of sections; prohibitive for large decoders Solutions: buffers progressive sizing combination of tree and pass transistor t approaches
Sense Amplifiers C t ΔV p = ---------------- I av large make ΔVassmallV small as possible (make the SA as sensitive as possible) small Idea: Use Sense Amplifer small transition s.a. input output
Differential Sense Amplifier V DD M 3 M 4 y Out bit M 1 M 2 bit SE M 5 Directly applicable to SRAMs
Differential Sensing SRAM V DD PC V DD BL EQ BL y V DD M 3 M 4 V DD 2 y WL i x M 1 SE M 5 M 2 2 x x 2 x SE SRAM cell i SE x Diff. Sense 2 x Amp V DD y Output SE Output (a) SRAM sensing scheme (b) two stage differential amplifier
Latch-Based Sense Amplifier (DRAM) EQ BL BL V DD SE SE Initialized in its meta-stable point with EQ Once adequate voltage gap is created, sense amp is enabled with SE Positive feedback quickly forces output t to a stable operating point.
Charge-Redistribution Amplifier V ref V L M 1 V S C M 2 M small 3 C large Concept 2.5 2.0 1.5 Transient Response V V S in V 1.0 V L 0.5 0.0 0.0 1.00 2.00 time (nsec) V ref 5 = 3V 3.00
Charge-Redistribution Amplifier EPROM V DD SE M 4 Load Out V casc M 3 C out Cascode device WLC M 2 C col Column decoder WL M 1 C BL BL EPROM array
Single-to to-differential ti Conversion BL Cell WL x Diff. SA S.A. 2 x 1+ 1 2- V ref Output t V ref : reference voltage
Open bitline architecture with dummy cells EQ L L 1 L 0 V DD R 0 R 1 L SE BLL BLR C S C S C S SE CS C S C S Dummy cell Dummy cell
DRAM Read Process with Dummy Cell 3 3 2 2 BL BL 1 BL 1 BL 0 0 1 2 3 t (ns) reading 0 0 0 1 2 3 t (ns) reading 1 3 EQ WL 2 SE 1 0 0 1 2 3 t (ns) control signals
Voltage Regulator V DD M drive V DL V REF Equivalent Model V bias V REF - + M drive V DL
Charge Pump V DD M1 CLK A B C pump M2 2V DD -2 V T V B V DD 2 V T 0 V - V load C load V load 0 V
DRAM Timing
Reliability and Yield Semiconductor memories trade-off noise margin for density and performance. Thus, they are highly sensitive to noises (cross talk, supply noise, etc). High density and large die size cause yield problems Yield = 100 # of good chips/wafer # of chips/wafer Y = [(1 e chip_area*defect_density )/(chip_area*defect_density)] 2 Increase yield using error correction and redundancy.
Noise Sources in DRAM BL substrate t Adjacent BL C WBL α-particles WL leakage C S electrode C cross
Open Bit-line Architecture Cross Coupling EQ BL WL 1 WL 0 WL D WL D WL 0 WL 1 C WBL C WBL BL C BL C C C Sense Amplifier C C C C BL
Folded-Bitline d Architecture t WL 1 WL 1 WL C 0 CWBL WL 0 WL D WL D BL C BL x y C C C C C C EQ Sense Amplifier BL C x y BL C WBL
Transposed-Bitline Architecture BL 9 BL BL BL 99 C cross (a) Straightforward bit-line routing SA BL 9 BL BL BL 99 C cross SA (b) Transposed bit-line architecture
Alpha-particles particles (or Neutrons) α-particle il WL V DD BL SiO n + 2 1 2 1 2 2 1 2 1 1 Particle ~ 1 Million Carriers 1 1 2 2
Yield Yield curves at different stages of process maturity
Redundancy Redundant columns Redundant rows Memory Array Row Address der w Decod Row Fuse : Bank Column Decoder Column Address
Error-Correcting Codes Example: Hamming Codes with e.g. B3 Wrong 1 1 = 3 0
Redundancy and Error Correction
Data Retention in SRAM 1.30u 1.10u 900n 0.13 μm CMOS akage (A) I le 700n 500n Factor 7 300n 0.18 μm CMOS 100n 0.00.600 1.20 1.80 V DD SRAM leakage increases with technology scaling.
Suppressing Leakage in SRAM sleep V DD low-threshold transistor V DD V DDL V DD,int sleep V DD,int SRAM SRAM SRAM cell cell cell SRAM cell SRAM cell SRAM cell sleep V SS,int Inserting Extra Resistance Reducing the supply voltage
Conclusions The memory architecture has a major impact on the ease of use of the memory, its performance, power consumption, reliability and yield. The memory cell should be designed so that a maximum signal is obtained with a minimum area. While the cell design is mostly dominated by technological considerations, a clever circuit design can help maximize the signal value and transient response. The peripheral circuitry is essential to operate the memory in a reliable way and with a reasonable performance given the weak signals from the cells. Issues related to decoders, sense amplifiers, IO buffers, and voltage generations are all very critical.
Conclusions The memory must operate correctly over a variety of operating and manufacturing conditions. To increase the integration density, memory designers may often give up on signal-to-noise ratio. This makes the design vulnerable to a whole range of noise signals which h are normally less of an issue in logic design. Identifying the potential sources of malfunction and providing an appropriate model is the first requirement when addressing memory reliability. Circuit precautions to deal with potential malfunctions include redundancy and error correction.
Conclusions The field of memory design is a dynamic and exciting specialty: Coordinated efforts from marketing and planning, process design, device design, circuit design, test & production engineering, and software engineering are all needed. Many innovative approaches are possible in every design stage. The market competition is fierce, but the winner is awarded with a big prize. The leading memory technologies are being pioneered by domestic companies/engineers.
Conclusions Think flexible and think big big. Succeed as an engineer. self-motivated energetic Engineer = Self-manaGed Insightful innovative Eye on data Execute Rewards