DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575-604 yrpeng@uark.edu
Pass Transistors We have assumed source is grounded What if source > 0? e.g. pass transistor passing V g = If V s > -V t, V gs < V t Hence transistor would turn itself off nmos pass transistors pull no higher than -V tn Called a degraded 1 Approach degraded value slowly (low I ds ) pmos pass transistors pull no lower than V tp Transmission gates are needed to pass both 0 and 1 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 2
Pass Transistor Ckts V s = -V tn -V tn -V tn -V tn V s = V tp -V tn V SS -2V tn 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design
DC Response DC Response: V out vs. V in for a gate Ex: Inverter When V in = 0 -> V out = When V in = -> V out = 0 In between, V out depends on transistor size and current By KCL, must settle such that I dsn = I dsp We could solve equations But graphical solution gives more insight V in I dsp I dsn V out 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 4
Transistor Operation Current depends on region of transistor behavior For what V in and V out are nmos and pmos in Cutoff? Linear? Saturation? 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 5
nmos Operation Cutoff Linear Saturated V gsn < V tn V in < V tn V gsn > V tn V in > V tn V dsn < V gsn V tn V out < V in - V tn V gsn > V tn V in > V tn V dsn > V gsn V tn V out > V in - V tn V gsn = V in V dsn = V out V in I dsp I dsn V out 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 6
pmos Operation Cutoff Linear Saturated V gsp > V tp V in > + V tp V gsp < V tp V in < + V tp V dsp > V gsp V tp V out > V in - V tp V gsp < V tp V in < + V tp V dsp < V gsp V tp V out < V in - V tp V gsp = V in - V dsp = V out - V tp < 0 V in I dsp I dsn V out 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 7
I-V Characteristics Make pmos is wider than nmos such that b n = b p V gsn5 I dsn V gsn4 -V dsp V gsn V gsp1 V gsp2-0 V gsn2 V gsn1 V gsp V dsn V gsp4 -I dsp V gsp5 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 8
Current vs. V out, V in V in0 V in5 I dsn, I dsp V in1 V in4 V in2 V in V in V in4 V in2 V in1 V out 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 9
Load Line Analysis For a given V in : Plot I dsn, I dsp vs. V out V out must be where currents are equal in V in I dsp I dsn V out V in0 V in5 I dsn, I dsp V in1 V in4 V in2 V in V in V in4 V in2 V in1 V out 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 10
Load Line Analysis Vin = 0 V in0 I dsn, I dsp V in0 V out 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 11
Load Line Analysis Vin = 0.2 I dsn, I dsp V in1 V in1 V out 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 12
Load Line Analysis Vin = 0.4 I dsn, I dsp V in2 V in2 V out 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 1
Load Line Analysis Vin = 0.6 I dsn, I dsp V in V in V out 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 14
Load Line Analysis Vin = 0.8 I dsn, I dsp V in4 V in4 V out 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 15
Load Line Analysis Vin = 1 V in5 I dsn, I dsp V out 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 16
Load Line Analysis Summary V in0 V in5 V in1 V in4 V in2 V in V in V in4 V in2 V in1 V out 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 17
DC Transfer Curve Transcribe points onto V in vs. V out plot Transistor operating regions? V in0 V in5 V in0 V in1 V in2 A B V in1 V in4 V out C V in2 V in V in V in4 V in2 V in1 0 V in D V in4 V E in5 V tn /2 +V tp V out V in 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 18
Operating Regions Revisit transistor operating regions V in V out V out A B C Region nmos pmos A Cutoff Linear B Saturation Linear C Saturation Saturation D Linear Saturation E Linear Cutoff 0 D E V tn /2 +V tp V in 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 19
Beta Ratio If b p / b n 1, switching point will move from /2 Called skewed gate Other gates: collapse into equivalent inverter V out b b p n 0.1 b p 10 b n 2 1 0.5 0 V in 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 20
Noise Margins How much noise can a gate input see before it does not recognize the input? Logical High Output Range Output Characteristics V OH NM H Input Characteristics Logical High Input Range V IH V IL Indeterminate Region Logical Low Output Range V OL NM L GND Logical Low Input Range 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 21
Logic Levels To maximize noise margins, select logic levels at unity gain point (slope = -1) of DC transfer characteristic V out V OH Unity Gain Points Slope = -1 b p /b n > 1 V in V out V OL 0 V tn V IL V IH - V tp V in 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 22
Transient Response DC analysis tells us V out if V in is constant Transient analysis tells us V out (t) if V in (t) changes Requires solving differential equations Input is usually considered to be a step or ramp From 0 to or vice versa 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 2
Inverter Step Response Ex: find step response of inverter driving load cap V in (t) I dsn (t) V out (t) C load t 0 V in (t) V out (t) t V V in out dv () t ( t t ) out dt ( t) u( t t ) V 0 0 V I DD dsn C DD () t load I 0 t t0 Vout ( t) b VDD V t V () t V V 2 D V b 2 dsn ( t) 2 VDD V Vout VDD Vt out out D t 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 24
Delay Definitions Switching speed: t r : rise time From output crossing 0.2 to 0.8 VDD t f : fall time From output crossing 0.8 to 0.2 VDD Propagation Delay: (max delay) t pdr : rising propagation delay From input to rising output crossing VDD/2 t pdf : falling propagation delay From input to falling output crossing VDD/2 t pd : average propagation delay t pd = (t pdr + t pdf )/2 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 25
Delay Definitions Contamination Delay: (min delay) t cdr : rising contamination delay From input to rising output crossing /2 t cdf : falling contamination delay From input to falling output crossing /2 t cd : average contamination delay t pd = (t cdr + t cdf )/2 Difference between propagation and contamination delay: Output is guaranteed to stay stable before contamination delay Output is guaranteed to stay stable after propagation delay 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 26
Simulated Inverter Delay Solving differential equations by hand is too hard SPICE simulator solves the equations numerically Uses more accurate I-V models too! But simulations take time to write, may hide insight 2.0 1.5 1.0 (V) V in t pdf = 66ps t pdr = 8ps 0.5 V out 0.0 0.0 200p 400p 600p 800p 1n t(s) 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 27
Delay Estimation We would like to be able to easily estimate delay Not as accurate as simulation But easier to ask What if? The step response usually looks like a 1 st order RC response with a decaying exponential. Use RC delay models to estimate delay C = total capacitance on output node Use effective resistance R So that t pd = RC Characterize transistors by finding their effective R Depends on average current as gate switches 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 28
Effective Resistance Shockley models have limited value Not accurate enough for modern transistors Too complicated for much hand analysis Simplification: treat transistor as resistor Replace I ds (V ds, V gs ) with the effective resistance R I ds = V ds /R R averaged across switching of a digital gate Too inaccurate to predict current at any given time But good enough to predict RC delay 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 29
RC Delay Model Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nmos has resistance R, capacitance C Unit pmos has resistance 2R, capacitance C Capacitance proportional to width Resistance inversely proportional to width g d k s g R/k kc d s kc kc g d k s g s kc 2R/k kc kc d 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 0
RC Values Capacitance C = Cg = Cs = Cd = 2 ff/μm of gate width in 0.6 μm Gradually decline to 1 ff/μm in nanometer techs. Resistance R 6 KΩ*μm in 0.6 μm process Improves with shorter channel lengths Unit transistors May refer to minimum contacted device (4/2 λ) Or maybe 1 μm wide device Doesn t matter as long as you are consistent 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 1
Inverter Delay Estimate Estimate the delay of a fanout-of-1 inverter 2C A 2 1 Y R R 2C C Y 2C C R 2C C 2C C d = 6RC C 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 2
Delay Model Comparison 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design
Example: -input NAND Sketch a -input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R). 2 2 2 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 4
-input NAND Caps Annotate the -input NAND gate with gate and diffusion capacitance. 2 2 2 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 5
NAND Caps Annotated Netlist (Assume all S/D are contacted) 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 6
NAND Caps Merge capacitance on the same net Note: Capacitor with both ends shorted is discarded 2 2 2 5C 5C 5C 6C 6C 9C 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 7
Diffusion Capacitance Diffusion capacitance depends on the layout Contacted Diffusion Cap is comparable to Cg Uncontacted is about half worst best 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 8
NAND Caps Annotated Netlist (Assume only Pins are contacted) I/O pins and power pins 2C 2C 2C 2C 2C 2 2 2 2C 2C 2C 2C C C C C C C C 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 9
NAND Caps After Merging (Assume only Pins are contacted) 5C 5C 5C 2 2 2 9C C C 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 40
Merged Diffusion Capacitance We assumed contacted diffusion on every s / d. Good layout minimizes diffusion area Ex: NAND layout shares one diffusion contact Reduces output capacitance by 2C Merged uncontacted diffusion might help too Shared Contacted Diffusion Merged Uncontacted Diffusion 2C 2C Isolated Contacted Diffusion 2 2 2 7C C C C C 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 41
Elmore Delay ON transistors look like resistors Pull-up or pull-down network modeled as RC ladder Elmore delay of RC ladder t R C pd i to source i nodes i R C R R C... R R... R C 1 1 1 2 2 1 2 R 1 R 2 R R N N N C 1 C 2 C C N 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 42
Example: NAND Estimate worst-case rising and falling delay of -input NAND driving h identical gates. pdf h copies t pdr 9 5h RC + (C)(R+R/) + (C) (R+R/+R/) = (18+5h)RC 2 2 2 n 1 9C n 2 C C R R R R R R 9 5 11 5h RC t C C h C Y 5hC 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 4
Delay Components Delay has two parts Parasitic delay 18 or 11 RC Independent of load Effort delay 5h RC Proportional to load capacitance t pdr = (18+5h) RC t pdf = (11+5h) RC 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 44
Contamination Delay Best-case (contamination) delay can be substantially less than propagation delay. T cdr : If all three inputs fall simultaneously (All PMOS on) 2 2 2 n 1 9C n 2 C C Y 5hC R 5 tcdr 9 5h C h RC 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 45
Contamination Delay T cdf : Is it the same as T pdf? All NMOS are on The best case is when two diff cap are already discharged t cdf = (9+5h) RC 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 46
Layout Comparison Which layout is better? A B A B Y Y GND GND 10/10/2017 CSCE/ELEG 4914: Advnaced Digital Design 47