ECEN454 Digital Integrated Circuit Design DC & Transient Responses ECEN 454 DC Response DC Response: vs. for a gate Ex: Inverter When = -> = When = -> = In between, depends on transistor size and current By KCL, must settle such that = I dsp We could solve equations But graphical solution gives more insight I dsp ECEN 454 5. 1
Transistor Operation Current depends on region of transistor behavior For what and are nmos and pmos in Cutoff? Linear? Saturation? ECEN 454 5.3 nmos Operation Cutoff Linear Saturated gsn < gsn > gsn > dsn < dsn > I dsp ECEN 454 5.4
nmos Operation Cutoff Linear Saturated gsn < tn gsn > tn gsn > tn dsn < gsn tn dsn > gsn tn I dsp ECEN 454 5.5 nmos Operation Cutoff Linear Saturated gsn < tn gsn > tn gsn > tn dsn < gsn tn dsn > gsn tn gsn = dsn = I dsp ECEN 454 5.6 3
nmos Operation Cutoff Linear Saturated gsn < tn < tn gsn > tn > tn dsn < gsn tn < - tn gsn > tn > tn dsn > gsn tn > - tn gsn = I dsp dsn = ECEN 454 5.7 pmos Operation Cutoff Linear Saturated gsp > gsp < gsp < dsp > dsp < I dsp ECEN 454 5.8 4
pmos Operation Cutoff Linear Saturated gsp > tp gsp < tp gsp < tp dsp > gsp tp dsp < gsp tp I dsp ECEN 454 5.9 pmos Operation Cutoff Linear Saturated gsp > tp gsp < tp gsp < tp dsp > gsp tp dsp < gsp tp gsp = - tp < dsp = - I dsp ECEN 454 5.1 5
pmos Operation Cutoff Linear Saturated gsp > tp > + tp gsp < tp < + tp dsp > gsp tp > - tp gsp < tp < + tp dsp < gsp tp < - tp gsp = - tp < dsp = - I dsp ECEN 454 5.11 I- Characteristics Make pmos is wider than nmos such that β n = β p gsn5 gsn4 gsn3 - dsp gsp1 gsp - gsn gsn1 gsp3 dsn gsp4 -I dsp gsp5 ECEN 454 5.1 6
Current vs., 5, I dsp 1 4 3 3 4 1 ECEN 454 5.13 Load Line Analysis For a given : Plot, I dsp vs. must be where currents are equal in 5, I dsp 1 4 3 3 4 1 I dsp ECEN 454 5.14 7
Load Line Analysis =, I dsp ECEN 454 5.15 Load Line Analysis =., I dsp 1 1 ECEN 454 5.16 8
Load Line Analysis =.4, I dsp ECEN 454 5.17 Load Line Analysis =.6, I dsp 3 3 ECEN 454 5.18 9
Load Line Analysis =.8, I dsp 4 4 ECEN 454 5.19 Load Line Analysis = 5, I dsp 1 3 4 ECEN 454 5. 1
Load Line Summary 5, I dsp 1 4 3 3 4 1 ECEN 454 5.1 DC Transfer Curve Transcribe points onto vs. plot A B 5 1 4 C 3 3 4 1 D E tn / + tp ECEN 454 5. 11
Operating Regions Revisit transistor operating regions Region nmos pmos A B C D E A B C D E tn / + tp ECEN 454 5.3 Operating Regions Revisit transistor operating regions Region nmos pmos A Cutoff Linear B Saturation Linear C Saturation Saturation D Linear Saturation E Linear Cutoff A B C D E tn / + tp ECEN 454 5.4 1
Beta Ratio If β p / β n 1, switching point will move from / Called skewed gate Other gates: collapse into equivalent inverter β p.1 β = n β p 1 β = n 1.5 ECEN 454 5.5 Noise Margins How much noise can a gate input see before it does not recognize the input? Logical High Output Range Logical Low Output Range Output Characteristics OH OL NM H NM L GND IH IL Input Characteristics Indeterminate Region Logical High Input Range Logical Low Input Range ECEN 454 5.6 13
Logic Levels To maximize noise margins, select logic levels at β p /β n > 1 ECEN 454 5.7 Logic Levels To maximize noise margins, select logic levels at unity gain point of DC transfer characteristic Unity Gain Points Slope = -1 OH β p /β n > 1 OL tn IL IH - tp ECEN 454 5.8 14
Pass Transistors We have assumed source is grounded What if source >? e.g. pass transistor passing ECEN 454 5.9 Pass Transistors We have assumed source is grounded What if source >? e.g. pass transistor passing g = If s > - t, gs < t Hence transistor would turn itself off nmos pass transistors pull no higher than - tn Called a degraded 1 Approach degraded value slowly (low I ds ) pmos pass transistors pull no lower than tp ECEN 454 5.3 15
Pass Transistor Ckts SS ECEN 454 5.31 Pass Transistor Ckts s = - tn -tn -tn - tn s = tp - tn - tn SS ECEN 454 5.3 16
Transient Response DC analysis tells us if is constant Transient analysis tells us if changes Requires solving differential equations Input is usually considered to be a step or ramp From to or vice versa ECEN 454 5.33 Inverter Step Response Ex: find step response of inverter driving load cap in = ( t < t ) = d = dt C load ECEN 454 5.34 17
Inverter Step Response Ex: find step response of inverter driving load cap in () t = u( t t ) ( t< t ) = d () t = dt C load ECEN 454 5.35 Inverter Step Response Ex: find step response of inverter driving load cap in = u( t t ) dot u = dt ( t< t ) = C load ECEN 454 5.36 18
Inverter Step Response Ex: find step response of inverter driving load cap in () t = u( t t ) ( t< t ) = do ut Id = dt C sn () t load C load t t dsn () = > t I t < t ECEN 454 5.37 Inverter Step Response Ex: find step response of inverter driving load cap I in () t = u( t t ) ( t< t ) = do ut Id = dt C sn () t load ( ) t t β dsn = > t β t () t < t C load ECEN 454 5.38 19
Inverter Step Response Ex: find step response of inverter driving load cap I in () t = u( t t ) ( t< t ) = do ut Id = dt C sn () t load ( ) t t β dsn = > t β t () t < t t C load t ECEN 454 5.39 Delay Definitions t pdr : rising propagation delay From input to rising put crossing / t pdf : falling propagation delay From input to falling put crossing / t pd : average propagation delay t pd = (t pdr + t pdf )/ t r : rise time From put crossing.1 to.9 t f : fall time From put crossing.9 to.1 ECEN 454 5.4
Simulated Inverter Delay Solving differential equations by hand is too hard SPICE simulator solves the equations numerically Uses more accurate I- models too! But simulations take time to write. 1.5 1. () t pdf = 66ps t pdr = 83ps.5.. p 4p 6p 8p 1n t(s) ECEN 454 5.41 Inverter Fall Time ds = gs t C load t t I ( ) t t β dsn = > t β t () t < t t f1 :.9 => ( t ) t f : ( t ) =>.1 ECEN 454 5.4 1
Fall Time: Saturation Region pmos nmos C load d dt β ( + t ) = C load t f 1.9 = Cload d β( t) t = Cload( β( t.1 t) ) ECEN 454 5.43 Fall Time: Linear Region pmos nmos C load t f = Cload = β( t). 1 β Cload t (1 t d ( t) t ln(19 ) ) ECEN 454 5.44
t f Overall Fall Time Cload n.1 1 = [ + ln(19 n)] β(1 n) 1 n C k β load n = t / ECEN 454 5.45 Approximately t dr = t r / t df = t f / Rise/Fall Time and Delay ECEN 454 5.46 3