CHAPTER 6 CMOS OPERATIONAL AMPLIFIERS

Chapter 6 Introduction (6/24/06) Page 6.0 CHAPTER 6 CMOS OPERATIONAL AMPLIFIERS INTRODUCTION Chapter Outline 6. CMOS Op Amps 6.2 Compensation of Op Amps 6.3 TwoStage Operational Amplifier Design 6.4 Cascode Op Amps 6.5 Simulation and Measurement of Op Amps 6.6 Macromodels for Op Amps 6.7 Summary Hierarchical Perspective: The op amps in this chapter represent an example of a reasonable complex circuit. The blocks and subblocks of the last two chapters will be used to implement the op amp in this chapter. Chapter 6 Functional blocks or circuits (Perform a complex function) Blocks or circuits (Combination of primitives, independent) Subblocks or subcircuits (A primitive, not independent) Fig. 6.0 Chapter 6 Introduction (6/24/06) Page 6.02 What is an Op Amp? The op amp (operational amplifier) is a high gain, dc coupled amplifier designed to be used with negative feedback to precisely define a closed loop transfer function. The basic requirements for an op amp: Sufficiently large gain (the accuracy of the signal processing determines this) Differential inputs Frequency characteristics that permit stable operation when negative feedback is applied Other requirements: High input impedance Low output impedance High speed/frequency

Chapter 6 Introduction (6/24/06) Page 6.03 Why Op Amps? The op amp is designed to be used with singleloop, negative feedback to accomplish precision signal processing as illustrated below. SingleLoop Negative Feedback Network V in (s) Feedback Network V f (s) Σ The voltage gain, V out(s) V in (s) F(s) A(s) Op Amp V out (s) Op Amp Implementation of a SingleLoop Negative Feedback Network V in (s), can be shown to be equal to, V f (s) F(s) A v (s) V out (s) 0606250 Vout(s) V in (s) = A v (s) A v (s)f(s) If the product of A v (s)f(s) is much greater than, then the voltage gain becomes, Vout(s) V in (s) F(s) The precision of the voltage gain is defined by F(s). Chapter 6 Section (6/24/06) Page 6. Ideal Op Amp Symbol: SECTION 6. CMOS OPERATIONAL AMPLIFIERS APPLICATION OF THE OP AMP i i 2 v v i V SS v OUT = A v (v v 2 ) v 2 Fig. 002 Null port: If the differential gain of the op amp is large enough then input terminal pair becomes a null port. A null port is a pair of terminals where the voltage is zero and the current is zero. I.e., v v 2 = v i = 0 and i = 0 and i 2 = 0 Therefore, ideal op amps can be analyzed by assuming the differential input voltage is zero and that no current flows into or out of the differential inputs.

Chapter 6 Section (6/24/06) Page 6.2 General Configuration of the Op Amp as a Voltage Amplifier R R2 v inn v v 2 inp v Noninverting voltage amplifier: v inn = 0 = R R 2 R v inp Inverting voltage amplifier: v inp = 0 = R 2 R v inn vout Fig. 003 Chapter 6 Section (6/24/06) Page 6.3 Example 6. Simplified Analysis of an Op Amp Circuit The circuit shown below is an inverting voltage amplifier using an op amp. Find the voltage transfer function, /v in. R i i 2 Virtual Ground Fig. 004 Solution If A v, then v i 0 because of the negative feedback path through R 2. (The op amp with fb. makes its input terminal voltages equal.) v i = 0 and i i = 0 Note that the null port becomes the familiar virtual ground if one of the op amp input terminals is on ground. If this is the case, then we can write that i = v in R and i 2 = R 2 i i v in v i v out Since, i i = 0, then i i 2 = 0 giving the desired result as R 2 v in = R 2 R.

Chapter 6 Section (6/24/06) Page 6.4 Example 6.2 A More Challenging Example of Ideal Op Amp Analysis Solve for Z in of the op amp circuit shown assuming the op amps are ideal. Solution Relationships enforced by the op amps:.) I in = I 2.) V = V 2 3.) I 2 I 3 = 0 4.) V 3 = V 4 5.) I 4 I 5 = 0 6.) V in = V 5 Therefore, Z in (s) = V in I in A I in I I V 3 V 2 4 Z Z 2 Z 3 Z 4 V I V 2 3 I 4 V in I A2 5 06062502 Z 5 V 5 I in = I = V Z = V 2 Z = I 2Z 2 Z = I 3Z 2 Z = V 3Z 2 Z Z 3 = V 4Z 2 Z Z 3 = I 4Z 2 Z 4 Z Z 3 = I 5Z 2 Z 4 Z Z 3 Now, solve for Z in, Z in = V in I in = V 5 I in = V 5Z Z 3 I 5 Z 2 Z 4 = Z Z 3 Z 5 Z 2 Z 4 Chapter 6 Section (6/24/06) Page 6.5 OP AMP CHARACTERIZATION Linear and Static Characterization of the CMOS Op Amp A model for a nonideal op amp that includes some of the linear, static nonidealities: v 2 v CMRR R icm V OS C icm e n 2 * C id R id R out vout v R icm C icm Ideal Op Amp where R id = differential input resistance C id = differential input capacitance R icm = common mode input resistance CR icm = common mode input capacitance V OS = inputoffset voltage CMRR = commonmode rejection ratio (when v =v 2 an output results) e 2 n = voltagenoise spectral density (meansquare volts/hertz) 06062503

Chapter 6 Section (6/24/06) Page 6.6 Linear and Dynamic Characteristics of the Op Amp Differential and commonmode frequency response: V out (s) = A v (s)[v (s) V 2 (s)] ± A c (s) V (s)v 2 (s) 2 Differentialfrequency response: A v0 A v0 p p 2 p 3 A v (s) = s p s p 2 s = (s p )(s p 2 )(s p 3 ) p 3 where p, p 2, p 3, are the poles of the differentialfrequency response (ignoring zeros). 20log0(A v0 ) A v (jω) db Asymptotic Magnitude Actual Magnitude 6dB/oct. GB 0dB Fig. 006 ω ω 2 ω 3 ω 2dB/oct. 8dB/oct. Chapter 6 Section (6/24/06) Page 6.7 Other Characteristics of the Op Amp Power supply rejection ratio (PSRR): PSRR = V OUT A v (s) V o/v in (V dd = 0) = V o /V dd (V in = 0) Input common mode range (ICMR): ICMR = the voltage range over which the input commonmode signal can vary without influence the differential performance Slew rate (SR): SR = output voltage rate limit of the op amp Settling time (T s ): v IN v OUT v OUT (t) Final Value ε ε Final Value Final Value ε ε Upper Tolerance Lower Tolerance Settling Time 0 0 T s t Fig. 007

Chapter 6 Section (6/24/06) Page 6.8 OP AMP CATEGORIZATION Classification of CMOS Op Amps Conversion Hierarchy Voltage to Current Current to Voltage Classic Differential Amplifier Differentialtosingle ended Load (Current Mirror) Modified Differential Amplifier Source/Sink Current Loads MOS Diode Load First Voltage Stage Voltage to Current Current to Voltage Transconductance Grounded Gate Class A (Source or Sink Load) Transconductance Grounded Source Class B (PushPull) Current Stage Second Voltage Stage Table 00 Chapter 6 Section (6/24/06) Page 6.9 TwoStage CMOS Op Amp Classical twostage CMOS op amp broken into voltagetocurrent and currenttovoltage stages: M3 M4 M6 v in VBias M M2 M5 M7 v in V I I V V I I V V SS Fig. 6.8

Chapter 6 Section (6/24/06) Page 6.0 Folded Cascode CMOS Op Amp Folded cascode CMOS op amp broken into stages. V PBias M3 M0 M V PBias2 M M2 v in M8 M9 v in M6 M7 V Bias V Bias M4 M5 V I I I I V V SS 06080 Chapter 6 Section (6/24/06) Page 6. DESIGN OF CMOS OP AMPS Steps in Designing a CMOS Op Amp Steps:.) Choosing or creating the basic structure of the op amp. This step is results in a schematic showing the transistors and their interconnections. This diagram does not change throughout the remainder of the design unless the specifications cannot be met, then a new or modified structure must be developed. 2.) Selection of the dc currents and transistor sizes. Most of the effort of design is in this category. Simulators are used to aid the designer in this phase. 3.) Physical implementation of the design. Layout of the transistors Floorplanning the connections, pinouts, power supply buses and grounds Extraction of the physical parasitics and resimulation Verification that the layout is a physical representation of the circuit. 4.) Fabrication 5.) Measurement Verification of the specifications Modification of the design as necessary

Chapter 6 Section (6/24/06) Page 6.2 Design Inputs Boundary conditions:. Process specification (V T, K', C ox, etc.) 2. Supply voltage and range 3. Supply current and range 4. Operating temperature and range Requirements:. Gain 2. Gain bandwidth 3. Settling time 4. Slew rate 5. Commonmode input range, ICMR 6. Commonmode rejection ratio, CMRR 7. Powersupply rejection ratio, PSRR 8. Outputvoltage swing 9. Output resistance 0. Offset. Noise 2. Layout area Chapter 6 Section (6/24/06) Page 6.3 Specifications for a Typical Unbuffered CMOS Op Amp Boundary Conditions Requirement Process Specification See Tables 3. and 3.2 Supply Voltage ±2.5 V ±0% Supply Current 00 μa Temperature Range 0 to 70 C Specifications Value Gain 70 db Gainbandwidth 5 MHz Settling Time μsec Slew Rate 5 V/μsec Input CMR ±.5 V CMRR 60 db PSRR 60 db Output Swing ±.5 V Output Resistance N/A, capacitive load only Offset ±0 mv Noise 00nV/ Hz at KHz Layout Area 0,000 min. channel length 2

Chapter 6 Section (6/24/06) Page 6.4 Outputs of Op Amp Design The basic outputs of design are:.) The topology 2.) The dc currents 3.) The W and L values of transistors 4.) The values of components VDD Topology vin M3 M M4 M2 Cc M6 vout CL Op amp circuit or systems specifications Design of CMOS Op Amps DC Currents VBias M5 VSS 50µA L M7 W/L ratios W 06062506 Component values C R Chapter 6 Section (6/24/06) Page 6.5 Some Practical Thoughts on Op Amp Design.) Decide upon a suitable topology. Experience is a great help The topology should be the one capable of meeting most of the specifications Try to avoid inventing a new topology but start with an existing topology 2.) Determine the type of compensation needed to meet the specifications. Consider the load and stability requirements Use some form of Miller compensation or a selfcompensated approach 3.) Design dc currents and device sizes for proper dc, ac, and transient performance. This begins with hand calculations based upon approximate design equations. Compensation components are also sized in this step of the procedure. After each device is sized by hand, a circuit simulator is used to fine tune the design Two basic steps of design:.) Firstcut this step is to use hand calculations to propose a design that has potential of satisfying the specifications. Design robustness is developed in this step. 2.) Optimization this step uses the computer to refine and optimize the design.

Chapter 6 Section 2 (6/24/06) Page 6.2 SECTION 6.2 COMPENSATION OF OP AMPS INTRODUCTION TO COMPENSATION Compensation Objective Objective of compensation is to achieve stable operation when negative feedback is applied around the op amp. Types of Compensation. Miller Use of a capacitor feeding back around a highgain, inverting stage. Miller capacitor only Miller capacitor with an unitygain buffer to block the forward path through the compensation capacitor. Can eliminate the RHP zero. Miller with a nulling resistor. Similar to Miller but with an added series resistance to gain control over the RHP zero. 2. Self compensating Load capacitor compensates the op amp (later). 3. Feedforward Bypassing a positive gain amplifier resulting in phase lead. Gain can be less than unity. Because compensation plays such a strong role in design, it is considered before design. Chapter 6 Section 2 (6/24/06) Page 6.22 SingleLoop, Negative Feedback Systems Block diagram: A(s) = differentialmode voltage gain of the op amp F(s) = feedback transfer function from the output of op amp back to the input. Definitions: Openloop gain = L(s) = A(s)F(s) Closedloop gain = V out(s) V in (s) = A(s) A(s)F(s) V in (s) Stability Requirements: The requirements for stability for a singleloop, negative feedback system is, A(j 0 )F(j 0 ) = L(j 0 ) < where 0 = 360 is defined as Arg[A(j 0 )F(j 0 )] = Arg[L(j 0 )] = 0 = 360 Another convenient way to express this requirement is Arg[A(j 0dB )F(j 0dB )] = Arg[L(j 0dB )] > 0 where 0dB is defined as A(j 0dB )F(j 0dB ) = L(j 0dB ) = Σ F(s) A(s) V out (s) Fig. 200

Chapter 6 Section 2 (6/24/06) Page 6.23 Illustration of the Stability Requirement using Bode Plots A(jω)F(jω) Arg[A(jω)F(jω)] 0dB 80 225 270 35 360 20dB/decade Φ M ω 0dB ω 40dB/decade Frequency (rads/sec.) 06062507 A measure of stability is given by the phase when A(j)F(j) =. This phase is called phase margin. Phase margin = M = 360 Arg[A(j 0dB )F(j 0dB )] = 360 Arg[L(j 0dB )] ω Chapter 6 Section 2 (6/24/06) Page 6.24 Why Do We Want Good Stability? Consider the step response of secondorder system which closely models the closedloop gain of the op amp connected in unity gain. (t) A v0.4.2.0 0.8 0.6 0.4 45 50 55 60 65 70 0.2 0 0 5 0 5 Fig. 2003 ω o t = ω n t (sec.) A good step response is one that quickly reaches its final value. Therefore, we see that phase margin should be at least 45 and preferably 60 or larger. (A rule of thumb for satisfactory stability is that there should be less than three rings.) Note that good stability is not necessarily the quickest risetime.

Chapter 6 Section 2 (6/24/06) Page 6.25 Uncompensated Frequency Response of TwoStage Op Amps TwoStage Op Amps: V CC M3 M4 M6 Q3 Q4 Q6 v in M M2 v in Q Q2 VBias SmallSignal Model: M5 V SS M7 VBias Q5 V EE Q7 Fig. 2004 g m v in 2 D, D3 (C, C3) D2, D4 (C2, C4) D6, D7 (C6, C7) R C v g m2v in 2 g m4 v R 2 C v2 R 3 C 3 2 gm6 v 2 Fig. 2005 Note that this model neglects the basecollector and gatedrain capacitances for purposes of simplification. Chapter 6 Section 2 (6/24/06) Page 6.26 Uncompensated Frequency Response of TwoStage Op Amps Continued For the MOS twostage op amp: R g m3 r ds3 r ds g m3 R 2 = r ds2 r ds4 and R 3 = r ds6 r ds7 C = C gs3 C gs4 C bd C bd3 C 2 = C gs6 C bd2 C bd4 and C 3 = C L C bd6 C bd7 For the BJT twostage op amp: R = g m3 r 3 r 4 r o r o3 g m3 R 2 = r 6 r o2 r o4 r 6 and R 3 = r o6 r o7 C = C 3 C 4 s s3 C 2 = C 6 s2 s4 and C 3 = C L s6 s7 Assuming the pole due to C is much greater than the poles due to C 2 and C 3 gives, g m v in R 2 C v2 R 3 C 3 2 gm6 v 2 g m V in V V out R I C I R II C II I gmii V I Fig. 2006 The locations for the two poles are given by the following equations p = R I C I and p 2 = R II C II where RI (RII) is the resistance to ground seen from the output of the first (second) stage and CI (CII) is the capacitance to ground seen from the output of the first (second) stage.

Chapter 6 Section 2 (6/24/06) Page 6.27 Uncompensated Frequency Response of an Op Amp (F(s) = ) A vd (0) db 20dB/decade Arg[A(jω)] A(jω) 0dB Phase Shift 80 225 270 35 360 45/decade p ' 45/decade log 0 (ω) log 0 (ω) 06062508 p 2 ' ω 0dB GB 40dB/decade If we assume that F(s) = (this is the worst case for stability considerations), then the above plot is the same as the loop gain. Note that the phase margin is much less than 45 ( 6 ). Therefore, the op amp must be compensated before using it in a closedloop configuration. Chapter 6 Section 2 (6/24/06) Page 6.28 MILLER COMPENSATION Miller Compensation of the TwoStage Op Amp V CC M3 M M2 v in VBias C M M5 M4 V SS C I M6 M7 C II Q3 Q4 C M v in Q Q2 VBias The various capacitors are: = accomplishes the Miller compensation C M = capacitance associated with the firststage mirror (mirror pole) C I = output capacitance to ground of the firststage C II = output capacitance to ground of the secondstage Q5 V EE C I Q6 Q7 Fig. 2008 C II

Chapter 6 Section 2 (6/24/06) Page 6.29 Compensated TwoStage, SmallSignal Frequency Response Model Simplified Use the CMOS op amp to illustrate:.) Assume that g m3 >> g ds3 g ds 2.) Assume that g m3 C M >> GB Therefore, v v2 g m v in 2 g m2 v in r ds r ds3 C M g m3 2 g m4 v C rds2 r ds4 g m6 v 2 r ds6 r ds7 C L v in v 2 g m v in CI rds2 r ds4 g m6 v C 2 II rds6 r ds7 Fig. 2009 Same circuit holds for the BJT op amp with different component relationships. Chapter 6 Section 2 (6/24/06) Page 6.20 General TwoStage Frequency Response Analysis V in g mi V in C I RI gmii V 2 R II C II where g mi = g m = g m2, R I = r ds2 r ds4, C I = C and g mii = g m6, R II = r ds6 r ds7, C II = C 2 = C L Nodal Equations: g mi V in = [G I s(c I )]V 2 [s ]V out and 0 = [g mii s ]V 2 [G II sc II s ]V out Solving using Cramer s rule gives, V out (s) V in (s) = g mi (g mii s ) G I G II s [G II (C I C II )G I (C II )g mii ]s 2 [C I C II C I C II ] A o [ s ( /g mii )] = s [R I (C I C II )R II (C 2 )g mii R R II ]s 2 [R I R II (C I C II C I C II )] where, A o = g mi g mii R I R II In general, D(s) = s p s p 2 = s p p 2 s2 p p 2 p = V 2 V out Fig.200 R I (C I C II )R II (C II )g mii R R II g mii R R II, p 2 = [R I(C I C II )R II (C II )g mii R R II ] R I R II (C I C II C I C II ) D(s) s p s2 p p 2, if p 2 >> p z = g mii g mii C I C II C I C II g mii C II, C II > > C I

Chapter 6 Section 2 (6/24/06) Page 6.2 Summary of Results for Miller Compensation of the TwoStage Op Amp There are three roots of importance:.) Righthalf plane zero: z = g mii = g m6 This root is very undesirable it boosts the magnitude while decreasing the phase. 2.) Dominant lefthalf plane pole (the Miller pole): p g mii R I R II = (g ds2g ds4 )(g ds6 g ds7 ) g m6 This root accomplishes the desired compensation. 3.) Lefthalf plane output pole: p 2 g mii C II g m6 C L This pole must be unitygainbandwidth or the phase margin will not be satisfied. Root locus plot of the Miller compensation: Closedloop poles, 0 Openloop poles =0 jω σ p 2 p 2 ' p ' p z Fig. 20 Chapter 6 Section 2 (6/24/06) Page 6.22 Compensated OpenLoop Frequency Response of the TwoStage Op Amp A vd (0) db Uncompensated F(jω)= 20dB/decade A(jω)F(jω) Arg[A(jω)F(jω) Note that the unitygainbandwidth, GB, is Compensated GB 0dB log 0 (ω) Phase Shift Uncompensated 40dB/decade 80 225 45/decade F(jω)= 270 45/decade Compensated 35 Phase No phase margin Margin 360 log 0 (ω) p p ' p 2 ' p 2 06080 GB = A vd (0) p = (g mi g mii R I R II ) g mii R I R II = g mi = g m = g m2

Chapter 6 Section 2 (6/24/06) Page 6.23 Conceptually, where do these roots come from?.) The Miller pole: p R I (g m6 R II ) R I R II M6 v I 2.) The lefthalf plane output pole: g m6 R II Fig. 203 p 2 g m6 C II R II M6 C II GB C 0 c RII M6 C II 3.) Righthalf plane zero (One source of zeros is from multiple paths from the input to output): Fig. 204 R II = g m6 R II (/s ) R II /s where v = v = v. v R II R II /s v = R g m6 II sc c R II /s v v'' v' M6 Fig. 205 Chapter 6 Section 2 (6/24/06) Page 6.24 Further Comments on p 2 The previous observations on p 2 can be proved as follows: Find the resistance R Cc seen by the compensation capacitor,. R Cc R II v x R I M6 i x R I R Cc v gs6gm6 v gs6 i x R II 06062602 v x = i x R I (i x g m6 v gs6 )R II = i x R I (i x g m6 i x R I )R II Therefore, R Cc = v x ix = R I ( g m6 R I )R II g m6 R I R II The frequency at which Cc begins to become a short is, C < c g m6 R I R II or > g m6 R I R II p Thus, at the frequency where C II begins to short the output, Cc is acting as a short.

Chapter 6 Section 2 (6/24/06) Page 6.25 Influence of the Mirror Pole Up to this point, we have neglected the influence of the pole, p 3, associated with the current mirror of the input stage. A smallsignal model for the input stage that includes C 3 is shown below: gmv in 2 rds rds3 i 3 gm2v in i gm3 C3 2 3 rds2 rds4 V o Fig. 206 The transfer function from the input to the output voltage of the first stage, V o (s), can be written as V o (s) sc 3 2g m3 g m g m V in (s) = g m3 g ds g ds3 2(g ds2 g ds4 ) g m3 g ds g ds3 sc 3 2(g ds2 g ds4 ) sc 3 g m3 We see that there is a pole and a zero given as p 3 = g m3 C 3 and z 3 = 2g m3 C 3 Chapter 6 Section 2 (6/24/06) Page 6.26 Summary of the Conditions for Stability of the TwoStage Op Amp Unitygainbandwith is given as: GB = A v (0) p =(g mi g mii R I R II ) g mii R I R II = g mi = (g m g m2 R R 2 ) g m2 R R 2 = g m The requirement for 45 phase margin is: ±80 Arg[Loop Gain] = ±80 tan p tan p2 tan z = 45 Let = GB and assume that z 0GB, therefore we get, ±80 tan GB p tan GB p2 tan GB z = 45 35 tan(av(0)) tan GB p2 tan (0.) = 90 tan GB p2 5.7 39.3 tan GB GB p2 p 2 = 0.88 p 2.22GB The requirement for 60 phase margin: p2 2.2GB if z 0GB If 60 phase margin is required, then the following relationships apply: gm6 Cc > 0g m Cc g m6 > 0gm and g m6 C2 > 2.2g m Cc Cc > 0.22C2

Chapter 6 Section 2 (6/24/06) Page 6.27 RIGHTHALF PLANE ZERO Controlling the RightHalf Plane Zero Why is the RHP zero a problem? Because it boosts the magnitude but lags the phase the worst possible combination for stability. jω 3 jω 2 jω jω 06062603 80 > θ > θ 2 > θ 3 θ θ θ3 2 z σ Loop Gain 0dB 80 Loop Phase Shift 360 RHP Zero Lag RHP Zero Boost log 0 ω log 0 ω Solution of the problem: The compensation comes from the feedback path through Cc, but the RHP zero comes from the feedforward path through Cc so eliminate the feedforward path! Chapter 6 Section 2 (6/24/06) Page 6.28 Use of Buffer to Eliminate the Feedforward Path through the Miller Capacitor Model: The transfer function is given by the following equation, V o (s) V in (s) = (g mi )(g mii )(R I )(R II ) s[r I C I R II C II R I g mii R I R II ] s2[r I R II C II (C I )] Using the technique as before to approximate p and p 2 results in the following and p Inverting HighGain Stage R I C I R II C II R I g mii R I R II g mii R I R II C V c I v OUT V in gmi v in C I R I V out V g mii V R I II C out II g mii p 2 C II (C I ) Comments: Poles are approximately what they were before with the zero removed. For 45 phase margin, p 2 must be greater than GB For 60 phase margin, p 2 must be greater than.73gb Fig. 43002

Chapter 6 Section 2 (6/24/06) Page 6.29 Use of Buffer with Finite Output Resistance to Eliminate the RHP Zero Assume that the unitygain buffer has an output resistance of R o. Model: R o Inverting HighGain Stage C V c I V out v OUT V in gmi v in C I R I R R o o V out g mii V R I II C II Fig. 43003 It can be shown that if the output resistance of the buffer amplifier, R o, is not neglected that another pole occurs at, p 4 R o [C I /(C I )] and a LHP zero at z 2 R o Closer examination shows that if a resistor, called a nulling resistor, is placed in series with that the RHP zero can be eliminated or moved to the LHP. Chapter 6 Section 2 (6/24/06) Page 6.220 Use of Nulling Resistor to Eliminate the RHP Zero (or turn it into a LHP zero) R z Inverting HighGain Stage v OUT V I R z V in g mi v in CI R I g mii V I R II C II Nodal equations: g mi V in V I R I sc I V I sc c s R z (V I V out ) = 0 g mii V I V o R II sc II V out sc c s R z (V out V I ) = 0 Solution: V out (s) V in (s) = a{ s[(/g mii ) R z ]} bs cs2 ds3 where a = g mi g mii R I R II b = (C II )R II (C I )R I g mii R I R II R z c = [R I R II (C I C II C I C II ) R z (R I C I R II C II )] d = R I R II R z C I C II V out Fig. 43004 W,J. Parrish, "An Ion Implanted CMOS Amplifier for High Performance Active Filters", Ph.D. Dissertation, 976, Univ. of CA., Santa Barbara.

Chapter 6 Section 2 (6/24/06) Page 6.22 Use of Nulling Resistor to Eliminate the RHP Continued If R z is assumed to be less than R I or R II and the poles widely spaced, then the roots of the above transfer function can be approximated as p ( g mii R II )R I g mii R II R I g mii p 2 C I C II C I C II g mii C II p 4 = R z C I and z = (/g mii R z ) Note that the zero can be placed anywhere on the real axis. Chapter 6 Section 2 (6/24/06) Page 6.222 Conceptual Illustration of the Nulling Resistor Approach R z R II V out The output voltage, V out, can be written as g m6 R II R z s R II R z V'' V' M6 R II R II R z s V = Fig. Fig. 43005 R g II m6 R z g m6 sc c R II R z s V out = V s when V = V = V. Setting the numerator equal to zero and assuming g m6 = g mii gives, z = (/g mii R z ) V

Chapter 6 Section 2 (6/24/06) Page 6.223 A Design Procedure that Allows the RHP Zero to Cancel the Output Pole, p 2 We desire that z = p 2 in terms of the previous notation. Therefore, (/g mii R z ) = g mii jω C II σ The value of R z can be found as p 4 p 2 p z Fig. 43006 R z = C II (/g mii ) With p 2 canceled, the remaining roots are p and p 4 (the pole due to R z ). For unitygain stability, all that is required is that A v (0) p 4 > A v (0) p = g mii R II R I = g mi and (/R z C I ) > (g mi / ) = GB Substituting R z into the above inequality and assuming C II >> results in g mi > g mii C I C II This procedure gives excellent stability for a fixed value of C II ( C L ). Unfortunately, as C L changes, p 2 changes and the zero must be readjusted to cancel p 2. Chapter 6 Section 2 (6/24/06) Page 6.224 Increasing the Magnitude of the Output Pole The magnitude of the output pole, p 2, can be increased by introducing gain in the Miller capacitor feedback path. For example, M0 M M8 M2 M9 V Bias C gd6 C r c M7 ds8 v OUT Iin R V Vs8 R 2 C 2 gm8vs8 g m6 V M6 V SS Fig. 6.25B The resistors R and R 2 are defined as V out C gd6 Iin R V R 2 C 2 gm8 V s8 g m8 V s8 g m6 V R = g ds2 g ds4 g ds9 and R 2 = g ds6 g ds7 where transistors M2 and M4 are the output transistors of the first stage. Nodal equations: I in = G V g m8 V s8 = G V g m8 s g m8 s V out and 0 = g m6 V G 2 sc 2 g m8s g m8 s V out V out B.K. Ahuja, An Improved Frequency Compensation Technique for CMOS Operational Amplifiers, IEEE J. of SolidState Circuits, Vol. SC8, No. 6 (Dec. 983) pp. 629633.

Chapter 6 Section 2 (6/24/06) Page 6.225 Increasing the Magnitude of the Output Pole Continued Solving for the transfer function V out /I in gives, V out I in = g m6 G G 2 s s g m8 C 2 G 2 G 2 g m6 G G 2 s 2 C 2 g m8 G 2 Using the approximate method of solving for the roots of the denominator gives and g m8 6 p = g m8 G 2 C 2 G 2 g m6 g m6 r ds 2 G G 2 p 2 g m6r ds 2 6 C 2 = g m8 G 2 g m8 r ds 2G 2 6 g m6 C 2 = g m8 r ds 3 p 2 where all the various channel resistance have been assumed to equal r ds and p 2 is the output pole for normal Miller compensation. Result: Dominant pole is approximately the same and the output pole is increased by g m r ds. Chapter 6 Section 2 (6/24/06) Page 6.226 Increasing the Magnitude of the Output Pole Continued In addition there is a LHP zero at g m8 /s and a RHP zero due to C gd6 (shown dashed in the model on Page 6.224) at g m6 /Cgd6. Roots are: g m6 g m8 r ds g m8 3C 2 g m6 r ds jω g m6 C gd6 σ Fig. 6.26A

Chapter 6 Section 2 (6/24/06) Page 6.227 Concept Behind the Increasing of the Magnitude of the Output Pole r ds7 GB C 0 M8 c M6 C II g m8 r ds8 3 r ds7 M6 C II Fig. Fig. 43008 R out = r ds7 3 3 g m6 g m8 r ds8 g m6 g m8 r ds8 Therefore, the output pole is approximately, p 2 g m6g m8 r ds8 3C II Chapter 6 Section 2 (6/24/06) Page 6.228 FINDING ROOTS BY INSPECTION Identification of Poles from a Schematic.) Most poles are equal to the reciprocal product of the resistance from a node to ground and the capacitance connected to that node. 2.) Exceptions (generally due to feedback): a.) Negative feedback: C 3 C 2 A C 2 A R C b.) Positive feedback (A<): R C C 3 (A) RootID0 C 3 C 2 A C 2 A R C R C C 3 (A) RootID02

Chapter 6 Section 2 (6/24/06) Page 6.229 Identification of Zeros from a Schematic.) Zeros arise from poles in the feedback path. F(s) v in Σ A(s) RootID03 If F(s) = s p, then V out V in = A(s) A(s)F(s) = 2.) Zeros are also created by two paths from the input to the output and one of more of the paths is frequency dependent. A(s) A(s) s p A(s) s p = s p A(s) R II v'' v' M6 Fig. 205 Chapter 6 Section 2 (6/24/06) Page 6.230 OTHER FORMS OF COMPENSATION Feedforward Compensation Use two parallel paths to achieve a LHP zero for lead compensation purposes. RHP Zero A LHP Zero A LHP Zero using Follower V i V out V i V out Vi V out Inverting High Gain Amplifier C II R II Inverting High Gain Amplifier C II R II V i A g mii V i C II R II Vout Fig.43009 V out (s) V in (s) = AC c s g mii /A C II s /[R II ( C II )] To use the LHP zero for compensation, a compromise must be observed. Placing the zero below GB will lead to boosting of the loop gain that could deteriorate the phase margin. Placing the zero above GB will have less influence on the leading phase caused by the zero. Note that a source follower is a good candidate for the use of feedforward compensation.

Chapter 6 Section 2 (6/24/06) Page 6.23 SelfCompensated Op Amps Self compensation occurs when the load capacitor is the compensation capacitor (can never be unstable for resistive feedback) db v in R out(must be large) G m R out C L A v (0) db Increasing C L 20dB/dec. Fig. 4300 Voltage gain: v in = A v (0) = G m R out Dominant pole: p = R out C L Unitygainbandwidth: GB = A v (0) p = G m CL 0dB Stability: Large load capacitors simply reduce GB but the phase is still 90 at GB. ω Chapter 6 Section 2 (6/24/06) Page 6.232 CMOS OP AMP SLEW RATE Slew Rate of a TwoStage CMOS Op Amp Remember that slew rate occurs when currents flowing in a capacitor become limited and is given as I lim = C dv C dt where v C is the voltage across the capacitor C. v in >>0 M3 M VBias I 5 M4 M2 M5 V SS Positive Slew Rate I5 Assume a virtural ground M6 I 6 I CL C L I 7 M7 v in <<0 SR = min I 5, I 6I 5 I 7 C L = I 5 because I 6 >>I 5 M3 M VBias I 5 M4 M2 M5 SR = min I 5 Assume a virtural ground M6 I 6 =0 ICL C L I 7 M7 V SS Negative Slew Rate Fig. 4005 I 5, I 7I 5 C L = I 5 if I 7 >>I 5. Therefore, if C L is not too large and if I 7 is significantly greater than I 5, then the slew rate of the twostage op amp should be, I 5 /.

Chapter 6 Section 3 (6/24/06) Page 6.3 SECTION 6.3 TWOSTAGE OP AMP DESIGN A DESIGN PROCEDURE FOR THE TWOSTAGE CMOS OP AMP Unbuffered, TwoStage CMOS Op Amp M3 M4 M6 Notation: M M2 v in VBias M5 S i = W i L i = W/L of the ith transistor V SS M7 C L Fig. 6.3 Chapter 6 Section 3 (6/24/06) Page 6.32 DC Balance Conditions for the TwoStage Op Amp For best performance, keep all transistors in saturation. M4 is the only transistor that cannot be forced into saturation by internal connections or external voltages. Therefore, we develop conditions to force M4 to be in saturation..) First assume that V SG4 = V SG6. This will cause proper mirroring in the M3M4 mirror. Also, the gate and drain of M4 are at the same potential so that M4 is guaranteed to be in saturation. 2.) If V SG4 = V SG6, then I 6 = S 6 S 4 I 4 3.) However, I 7 = S 7 S 5 I 5 = S 7 S 5 (2I 4 ) M3 V SG4 M4 M M2 v in I 5 VBias M5 I 4 V SS V SG6 M6 I 6 C L I 7 M7 Fig. 6.3A S 6 4.) For balance, I 6 must equal I 7 S 4 = 2S 7 S 5 called the balance conditions 5.) So if the balance conditions are satisfied, then V DG4 = 0 and M4 is saturated.

Chapter 6 Section 3 (6/24/06) Page 6.33 Design Relationships for the TwoStage Op Amp Slew rate SR I 5 = (Assuming I 7 >>I 5 and C L > ) Firststage gain A v = Secondstage gain A v2 = g m 2g m g ds2 g ds4 = I 5 ( 2 4 ) g m6 g m6 g ds6 g ds7 = I 6 ( 6 7 ) Gainbandwidth GB g m = Output pole p g m6 2 = C L RHP zero z g m6 = 60 phase margin requires that g m6 = 2.2g m2 (C L / ) if all other roots are 0GB. I 5 Positive ICMR V in(max) = 3 V T03 (max) V T(min) ) Negative ICMR V in(min) = V SS I 5 V T(max) V DS5 (sat) Chapter 6 Section 3 (6/24/06) Page 6.34 Op Amp Specifications The following design procedure assumes that specifications for the following parameters are given.. Gain at dc, A v (0) 2. Gainbandwidth, GB 3. Phase margin (or settling time) 4. Input commonmode range, ICMR 5. Load Capacitance, C L 6. Slewrate, SR 7. Output voltage swing 8. Power dissipation, P diss M3 M4 GB = g m v in M M2 VBias Max. ICMR and/or p 3 V SG4 M5 V SS 0.2C L (PM = 60 ) V out (max) V SG6 M6 g m6 or I 6 Proper Mirroring V SG4 =V SG6 M7 C L Min. ICMR I 5 I5 = SR V out (min) Fig. 6002

Chapter 6 Section 3 (6/24/06) Page 6.35 Unbuffered Op Amp Design Procedure This design procedure assumes that the gain at dc (A v ), unity gain bandwidth (GB), input common mode range (V in (min) and V in (max)), load capacitance (C L ), slew rate (SR), settling time (T s ), output voltage swing (V out (max) and V out (min)), and power dissipation (P diss ) are given. Choose the smallest device length which will keep the channel modulation parameter constant and give good matching for current mirrors.. From the desired phase margin, choose the minimum value for, i.e. for a 60 phase margin we use the following relationship. This assumes that z 0GB. > 0.22C L 2. Determine the minimum value for the tail current (I 5 ) from the largest of the two values. I 5 = SR. Cc or I 5 0 V SS 2. Ts 3. Design for S 3 from the maximum input voltage specification. I 5 S 3 = K' 3 [ V in (max) V T03 (max) V T (min)]2 4. Verify that the pole of M3 due to C gs3 and C gs4 (= 0.67W 3 L 3 C ox ) will not be dominant by assuming it to be greater than 0 GB gm3 2Cgs3 > 0GB. Chapter 6 Section 3 (6/24/06) Page 6.36 Unbuffered Op Amp Design Procedure Continued 5. Design for S (S 2 ) to achieve the desired GB. g m = GB. S g m 2 2 = K' I 5 6. Design for S 5 from the minimum input voltage. First calculate V DS5 (sat) then find S 5. I 5 2I 5 V DS5 (sat) = V in (min) V SS V T (max) 00 mv S 5 = K' 5 [V DS5 (sat)]2 7. Find S 6 by letting the second pole (p 2 ) be equal to 2.2 times GB and assuming that V SG4 = V SG6. g m6 = 2.2g m2 (C L / ) and 8. Calculate I 6 from g m6 g m4 = 2K P 'S 6 I 6 2K P 'S 4 I 4 = S 6 S 4 I 6 I4 = S 6 S 4 S 6 = g m6 g m4 S 4 I g m6 2 6 = 2K' 6 S 6 Check to make sure that S 6 satisfies the V out (max) requirement and adjust as necessary. 9. Design S 7 to achieve the desired current ratios between I 5 and I 6. S 7 = (I 6 /I 5 )S 5 (Check the minimum output voltage requirements)

Chapter 6 Section 3 (6/24/06) Page 6.37 Unbuffered Op Amp Design Procedure Continued 0. Check gain and power dissipation specifications. 2g m2 g m6 A v = I 5 ( 2 4 )I 6 ( 6 7 ) P diss = (I 5 I 6 )( V SS ). If the gain specification is not met, then the currents, I 5 and I 6, can be decreased or the W/L ratios of M2 and/or M6 increased. The previous calculations must be rechecked to insure that they are satisfied. If the power dissipation is too high, then one can only reduce the currents I 5 and I 6. Reduction of currents will probably necessitate increase of some of the W/L ratios in order to satisfy input and output swings. 2. Simulate the circuit to check to see that all specifications are met. Chapter 6 Section 3 (6/24/06) Page 6.38 DESIGN EXAMPLE Example 6.3 Design of a TwoStage Op Amp Using the material and device parameters given in Tables 3. and 3.2, design an amplifier similar to that shown in Fig. 6.3 that meets the following specifications. Assume the channel length is to be μm and the load capacitor is C L = 0pF. Av > 3000V/V = 2.5V V SS = 2.5V GB = 5MHz SR > 0V/μs 60 phase margin V out range = ±2V ICMR = to 2V P diss 2mW Solution.) The first step is to calculate the minimum value of the compensation capacitor, > (2.2/0)(0 pf) = 2.2 pf 2.) Choose as 3pF. Using the slewrate specification and calculate I 5. I 5 = (3x0 2 )(0x06) = 30 μa 3.) Next calculate (W/L) 3 using ICMR requirements. (W/L) 3 = 30x0 6 (50x0 6 )[2.5 2.85 0.55] 2 = 5 (W/L) 3 = (W/L) 4 = 5

Chapter 6 Section 3 (6/24/06) Page 6.39 Example 6.3 Continued 4.) Now we can check the value of the mirror pole, p 3, to make sure that it is in fact greater than 0GB. Assume the C ox = 0.4fF/μm 2. The mirror pole can be found as p g m3 2K p S 3 I 3 3 2C gs3 = 2(0.667)W 3 L 3 C ox = 2.8x0 9 (rads/sec) or 448 MHz. Thus, p 3, is not of concern in this design because p 3 >> 0GB. 5.) The next step in the design is to calculate g m to get g m = (5x0 6 )(2)(3x0 2 ) = 94.25μS Therefore, (W/L) is (W/L) = (W/L) g m 2 2 = 2K N I = (94.25)2 2 0 5 = 2.79 3.0 (W/L) = (W/L) 2 = 3 6.) Next calculate V DS5, 30x0 V DS5 = () (2.5) 6 0x06 3.85 = 0.35V Using V DS5 calculate (W/L) 5 from the saturation relationship. (W/L) 5 = 2(30x06) (0x06)(0.35)2 = 4.49 4.5 (W/L) 5 = 4.5 Chapter 6 Section 3 (6/24/06) Page 6.30 Example 6.3 Continued 7.) For 60 phase margin, we know that g m6 0g m 942.5μS Assuming that g m6 = 942.5μS and knowing that g m4 = 50μS, we calculate (W/L) 6 as (W/L) 6 = 5 942.5x0 6 (50x06) = 94.25 94 8.) Calculate I 6 using the smallsignal g m expression: (942.5x06)2 I 6 = (2)(50x06)(94.25) = 94.5μA 95μA If we calculate (W/L) 6 based on V out (max), the value is approximately 5. Since 94 exceeds the specification and maintains better phase margin, we will stay with (W/L) 6 = 94 and I 6 = 95μA. With I 6 = 95μA the power dissipation is P diss = 5V (30μA95μA) = 0.625mW.

Chapter 6 Section 3 (6/24/06) Page 6.3 Example 6.3 Continued 9.) Finally, calculate (W/L) 7 (W/L) 7 = 4.5 95x06 30x06 = 4.25 4 (W/L) 7 = 4 Let us check the V out (min) specification although the W/L of M7 is so large that this is probably not necessary. The value of V out (min) is 2 95 V out (min) = V DS7 (sat) = 0 4 = 0.35V which is less than required. At this point, the firstcut design is complete. 0.) Now check to see that the gain specification has been met (92.45x06)(942.5x06) A v = 5x06(.04.05)95x06(.04.05) = 7,697V/V which exceeds the specifications by a factor of two..an easy way to achieve more gain would be to increase the W and L values by a factor of two which because of the decreased value of would multiply the above gain by a factor of 20..) The final step in the hand design is to establish true electrical widths and lengths based upon L and W variations. In this example L will be due to lateral diffusion only. Unless otherwise noted, W will not be taken into account. All dimensions will be rounded to integer values. Assume that L = 0.2μm. Chapter 6 Section 3 (6/24/06) Page 6.32 Example 6.3 Continued Therefore, we have, W = W 2 = 3( 0.4) =.8 μm 2μm W 3 = W 4 = 5( 0.4) = 9μm W 5 = 4.5( 0.4) = 2.7μm 3μm W 6 = 94( 0.4) = 56.4μm 56μm W 7 = 4( 0.4) = 8.4 8μm The figure below shows the results of the firstcut design. The W/L ratios shown do not account for the lateral diffusion discussed above. The next phase requires simulation. 5μm μm M3 = 2.5V M4 5μm μm M6 = 3pF 94μm μm 30μA 4.5μm μm v in M8 M 3μm μm M5 3μm μm 30μA 4.5μm μm M2 V SS = 2.5V 95μA M7 4μm μm C L = 0pF Fig. 6.33

Chapter 6 Section 3 (6/24/06) Page 6.33 ELIMINATING THE RHP ZERO Incorporating the Nulling Resistor into the Miller Compensated TwoStage Op Amp Circuit: M V A M0 V C v in M3 C M M M4 V B v in M2 M8 M6 C L vout I Bias M2 M9 M5 M7 We saw earlier that the roots were: p g m2 g m = A v C = c A v p g m6 2 = C L p 4 = R z C I z = R z /g m6 where A v = g m g m6 R I R II. (Note that p 4 is the pole resulting from the nulling resistor compensation technique.) V SS Fig. 6003 Chapter 6 Section 3 (6/24/06) Page 6.34 Design of the Nulling Resistor (M8) For the zero to be on top of the second pole (p 2 ), the following relationship must hold R C L C c z = g m6 = C L 2K P S 6 I 6 The resistor, R z, is realized by the transistor M8 which is operating in the active region because the dc current through it is zero. Therefore, R z, can be written as R v DS8 z = i D8 V DS8 =0 = K P S 8 (V SG8 V TP ) The bias circuit is designed so that voltage V A is equal to V B. W V GS0 V T = V GS8 V T V SG = V SG6 In the saturation region 2(I 0 ) V GS0 V T = K' P (W 0 /L 0 ) = V GS8 V T K P S 0 R z = K P S 8 2I 0 = S 0 S 8 2K P I 0 W 8 Equating the two expressions for R z gives L 8 = L = I 0 W 6 I 6 L 6 C L S 0 S 6 I 6 I 0

Chapter 6 Section 3 (6/24/06) Page 6.35 Example 6.32 RHP Zero Compensation Use results of Ex. 6.3 and design compensation circuitry so that the RHP zero is moved from the RHP to the LHP and placed on top of the output pole p 2. Use device data given in Ex. 6.3. Solution The task at hand is the design of transistors M8, M9, M0, M, and bias current I 0. The first step in this design is to establish the bias components. In order to set V A equal to V B, thenv SG must equal V SG6. Therefore, S = (I /I 6 )S 6 Choose I = I 0 = I 9 = 5μA which gives S = (5μA/95μA)94 = 4.8 5. The aspect ratio of M0 is essentially a free parameter, and will be set equal to. There must be sufficient supply voltage to support the sum of V SG, V SG0, and V DS9. The ratio of I 0 /I 5 determines the (W/L) of M9. This ratio is (W/L) 9 = (I 0 /I 5 )(W/L) 5 = (5/30)(4.5) = 2.25 2 Now (W/L) 8 is determined to be (W/L) 8 = 3pF 94 95μA 3pF0pF 5μA = 5.63 6 Chapter 6 Section 3 (6/24/06) Page 6.36 Example 6.32 Continued It is worthwhile to check that the RHP zero has been moved on top of p 2. To do this, first calculate the value of R z. V SG8 must first be determined. It is equal to V SG0, which is V SG0 = Next determine R z. 2I 0 K P S 0 V TP = 2 5 50 0.7 =.474V R z = K P S 8 (V SG0 V TP ) = 0 6 50 5.63(.474.7) = 4.590k The location of z is calculated as z = (4.590 x 03)(3x0 2 3x0 ) 2 942.5x06 The output pole, p 2, is = 94.46x0 6 rads/sec p 2 = 942.5x06 0x02 = 94.25x0 6 rads/sec Thus, we see that for all practical purposes, the output pole is canceled by the zero that has been moved from the RHP to the LHP. The results of this design are summarized below. W 8 = 6 μm W 9 = 2 μm W 0 = μm W = 5 μm

Chapter 6 Section 3 (6/24/06) Page 6.37 An Alternate Form of Nulling Resistor To cancel p 2, z = p 2 R z = C L g m6a C C = g m6b Which gives g m6b = g m6a C c C L In the previous example, g m6a = 942.5μS, = 3pF and C L = 0pF. Choose I 6B = 0μA to get or g m6b = g m6a C L W 6B L 6B = 3 I 3 2 6A W 6A I 6B L 6A = 3 2K P W 6B I 6B L 6B 3 2 = M M2 v in C L VBias M3 M4 M5 2K P W 6A I D6 L 6A 95 0 (94) = 47.6 W 6B = 48μm M M6B V SS M8 M0 M9 M6 C L M7 Fig. 6.34A Chapter 6 Section 3 (6/24/06) Page 6.38 Programmability of the TwoStage Op Amp The following relationships depend on the bias current, I bias, in the following manner and allow for programmability after fabrication. A v (0) = g mi g mii R I R II I Bias GB = g mi I Bias P diss = ( V SS )(K K 2 )I Bias I bias SR = K I Bias I Bias R out = 2K 2 I Bias I Bias p = g mii R I R II I 2 Bias I I.5 Bias Bias z = g mii I Bias Illustration of the I bias dependence 03 02 0 00 0 02 P diss and SR v in M M2 IBias K IBias K 2IBias 03 0 00 I Bias Fig. 6005 I Bias (ref) p Ao and R out GB and z M3 M4 M5 V SS M6 M7 Fig. 6.304D

Chapter 6 Section 3 (6/24/06) Page 6.39 Simulation of the Electrical Design Area of source or drain = AS = AD = W[L L2 L3] where L = Minimum allowable distance between the contact in the S/D and the polysilicon (5μm) L2 = Width of a minimum size contact (5μm) L3 = Minimum allowable distance from contact in S/D to edge of S/D (5μm) AS = AD = Wx5μm Perimeter of the source or drain = PD = PS = 2W 2(LL2L3) PD = PS = 2W 30μm Illustration: L3 L2 L L L2 L3 Poly W Diffusion Diffusion L Fig. 6.35 Chapter 6 Section 3 (6/24/06) Page 6.320 POWER SUPPLY REJECTION RATIO OF THE TWOSTAGE OP AMP What is PSRR? V dd PSRR = A v(v dd =0) A dd (V in =0) How do you calculate PSRR? You could calculate A v and A dd and divide, however V in V 2 V V out V ss V SS Fig.800 V dd V 2 V 2 V V out V ss V SS V A v (V V 2 ) ±A dd V dd V out Fig. 8002 V out = A dd V dd A v (V V 2 ) = A dd V dd A v V out V out (A v ) = A dd V dd V out V dd = A dd A dd A v A v = (Good for frequencies up to GB) PSRR

Chapter 6 Section 3 (6/24/06) Page 6.32 Approximate Model for PSRR V dd M3 M4 M6 V out V out V out V dd 0dB R out ω VBias M M5 M2 C I M7 C II V dd Rout Other sources of PSRR besides V SS Fig. 8005.) The M7 current sink causes V SG6 to act like a battery. 2.) Therefore, V dd couples from the source to gate of M6. 3.) The path to the output is through any capacitance from gate to drain of M6. Conclusion: The Miller capacitor couples the positive power supply ripple directly to the output. Must reduce or eliminate. Chapter 6 Section 3 (6/24/06) Page 6.322 Approximate Model for PSRR M3 M4 M6 V out r ds7 M M2 C I C II V ss Z out VBias M5 What is Z out? Z out = V t I t I t = g mii V = g g mi V t mii G I sc I s Thus, Z out = G Is(C I ) g mi g MII V r ds7 out Z out V ss = = s(c I ) G I g mi g mii r ds7 G I s( C I ) G I Pole at C I The negative PSRR is much better than the positive PSRR. M7 VBias connected to V SS r ds7 V ss V SS C II C gd7 Path through C gd7 is negligible Fig. 80 r ds6 r ds7 C I R I V g mii V V out g mi V out I t V t Fig.802

Chapter 6 Section 4 (6/24/06) Page 6.4 SECTION 6.4 CASCODE OP AMPS INTRODUCTION Why Cascode Op Amps? Control of the frequency behavior Can get more gain by increasing the output resistance of a stage In the past section, PSRR of the twostage op amp was insufficient for many applications A twostage op amp can become unstable for large load capacitors (if nulling resistor is not used) The cascode op amp leads to wider ICMR and/or smaller power supply requirements Where Should the Cascode Technique be Used? First stage Good noise performance Requires level translation to second stage Degrades the Miller compensation Second stage Self compensating Increases the efficiency of the Miller compensation Increases PSRR Chapter 6 Section 4 (6/24/06) Page 6.42 SINGLE STAGE CASCODE OP AMPS Simple Single Stage Cascode Op Amp V PBias2 M3 MC3 M4 MC4 v o Implementation of the M3 floating voltage VBias which must equal MB3 2V ON V T. V PBias2 MC3 MB4 M4 MC4 MC MC2 M M2 V Bias vin v in 2 2 V NBias M5 V SS MB5 MC MC2 M M2 VBias MB MB2 vin v in 2 2 V NBias R out of the first stage is R I (g mc2 r dsc2 r ds2 ) (g mc4 r dsc4 r ds4 ) M5 V SS 0606270 Voltage gain = v o v in = g m R I [The gain is increased by approximately 0.5(g MC r dsc )] As a single stage op amp, the compensation capacitor becomes the load capacitor.

Chapter 6 Section 4 (6/24/06) Page 6.43 Example 6.5 SingleStage, Cascode Op Amp Performance Assume that all W/L ratios are 0 μm/ μm, and that I DS = I DS2 = 50 μa of single stage op amp. Find the voltage gain of this op amp and the value of C I if GB = 0 MHz. Use the model parameters of Table 3.2. Solution The device transconductances are g m = g m2 = g mi = 33.7 μs g mc2 = 33.7μS g mc4 = 223.6 μs. The output resistance of the NMOS and PMOS devices is 0.5 M and 0.4 M, respectively. R I = 25 M A v (0) = 8290 V/V. For a unitygain bandwidth of 0 MHz, the value of C I is 5.28 pf. What happens if a 00pF capacitor is attached to this op amp? GB goes from 0MHz to 0.53MHz. Chapter 6 Section 4 (6/24/06) Page 6.44 Enhanced Gain, Single Stage, Cascode Op Amp M7 M8 M7 M8 M5 M3 A A A M6 M4 v OUT M5 V PB M3 V NB M5 M6 VDD M3 M4 M M2 M6 M4 v OUT v IN M V NB M9 M2 v IN V NB M M9 M2 M0 From inspection, we can write the voltage gain as, 06062702 A v = v OUT v IN = g m R out where R out = (Ar ds6 g m6 r ds8 ) (Ar ds2 g m4 r ds4 ) Since A g m r ds the voltage gain would be equal to 00,000 to 500,000.

Chapter 6 Section 4 (6/24/06) Page 6.45 TWOSTAGE, CASCODE OP AMPS TwoStage Op Amp with a Cascoded FirstStage MC3 R MC M v in 2 M3 MB3 VBias MB5 VBias MB MB2 M5 V SS MB4 MT 07070 M4 v o MC4 MC2 M2 v in 2 MT2 MT and MT2 are required for level shifting from the firststage to the second. The PSRR is improved by the presence of MT Internal loop pole at the gate of M6 may cause the Miller compensation to fail. p 3 p2 The voltage gain of this op amp could easily be 00,000V/V M6 M7 p jω σ z Fig. 6.52A Chapter 6 Section 4 (6/24/06) Page 6.46 TwoStage Op Amp with a Cascode SecondStage A v = g mi g mii R I R II where g mi = g m = g m2, g mii = g m6, and R I = 2 g ds2 g ds4 = ( 2 4 )I D5 R II = (g mc6 r dsc6 r ds6 ) (g mc7 r dsc7 r ds7 ) M M2 v in Comments: The secondstage gain has greatly increased improving the Miller compensation The overall gain is approximately (g m r ds )3 or very large Output pole, p 2, is approximately the same if is constant The zero RHP is the same if is constant PSRR is poor unless the Miller compensation is removed (then the op amp becomes self compensated) VBias M3 M4 M5 R z V SS VBP VBN M6 MC6 MC7 M7 C L Fig. 6.53

Chapter 6 Section 4 (6/24/06) Page 6.47 A Balanced, TwoStage Op Amp using a Cascode Output Stage = g m g m8 v in g m3 2 g m2g m6 v in g m4 2 R M4 M6 II = g M3 M8 V m 2 g m2 PB2 M7 2 kv in R II = g m k R II v in where M M2 V M9 v in NB2 C L R II = (g m7 r ds7 r ds6 ) (g m2 r ds2 r ds ) M2 and M5 V NB k = g m8 g m3 = g m6 g m4 This op amp is balanced because the draintoground loads for M and M2 are identical. TABLE Design Relationships for Balanced, Cascode Output Stage Op Amp. Slew rate = I out C L GB = g mg m8 g m3 C L A v = g m g m8 2 g m2g m6 R II V in (max) = I 5 /2 3 V SS M0 M 06062703 g m3 V TO3 (max) V T (min) V in (min) = V SS V DS5 /2 V T (min) g m4 I 5 Chapter 6 Section 4 (6/24/06) Page 6.48 Example 6.52 Design of Balanced, Cascoded Output Stage Op Amp The balanced, cascoded output stage op amp is a useful alternative to the twostage op amp. Its design will be illustrated by this example. The pertinent design equations for the op amp were given above. The specifications of the design are as follows: = V SS = 2.5 V Slew rate = 5 V/μs with a 50 pf load GB = 0 MHz with a 25 pf load A v 5000 Input CMR = V to.5 V Output swing = ±.5 V Use the parameters of Table 3.2 and let all device lengths be μm. Solution While numerous approaches can be taken, we shall follow one based on the above specifications. The steps will be numbered to help illustrate the procedure..) The first step will be to find the maximum source/sink current. This is found from the slew rate. I source /I sink = C L slew rate = 50 pf(5 V/μs) = 250 μa 2.) Next some W/L constraints based on the maximum output source/sink current are developed. Under dynamic conditions, all of I 5 will flow in M4; thus we can write Max. I out (source) = (S 6 /S 4 )I 5 and Max. I out (sink) = (S 8 /S 3 )I 5 The maximum output sinking current is equal to the maximum output sourcing current if S 3 = S 4, S 6 = S 8, and S 0 = S

Chapter 6 Section 4 (6/24/06) Page 6.49 Example 6.52 Continued 3.) Choose I 5 as 00 μa. This current (which can be changed later) gives S 6 = 2.5S 4 and S 8 = 2.5S 3 Note that S 8 could equal S 3 if S = 2.5S 0. This would minimize the power dissipation. 4.) Next design for ±.5 V output capability. We shall assume that the output must source or sink the 250μA at the peak values of output. First consider the negative output peak. Since there is V difference between V SS and the minimum output, let V DS (sat) = V DS2 (sat) = 0.5 V (we continue to ignore the bulk effects). Under the maximum negative peak assume that I = I 2 = 250 μa. Therefore 2I 2I 2 500 μa 0.5 = K' N S = K' N S 2 = (0 μa/v2)s which gives S = S 2 = 8.2 and S 9 = S 0 = 8.2. For the positive peak, we get 2I 6 2I 7 500 μa 0.5 = K' P S 6 = K' P S 7 = (50 μa/v2)s 6 which gives S 6 = S 7 = S 8 = 40 and S 3 = S 4 = (40/2.5) = 6. Chapter 6 Section 4 (6/24/06) Page 6.40 Example 6.52 Continued 5.) Now we must consider the possibility of conflict among the specifications. First consider the input CMR. S 3 has already been designed as 6. Using ICMR relationship, we find that S 3 should be at least 4.. A larger value of S 3 will give a higher value of V in (max) so that we continue to use S 3 = 6 which gives V in (max) =.95V. Next, check to see if the larger W/L causes a pole below the gainbandwidth. Assuming a C ox of 0.4fF/μm 2 gives the firststage pole of g m3 2K P S 3 I 3 p 3 = C gs3 C gs8 = (0.667)(W 3 L 3 W 8 L 8 )C ox = 33.5x0 9 rads/sec or 5.275GHz which is much greater than 0GB. 6.) Next we find g m (g m2 ). There are two ways of calculating g m. (a.) The first is from the A v specification. The gain is A v = (g m /2g m4 )(g m6 g m8 ) R II Note, a current gain of k could be introduced by making S 6 /S 4 (S 8 /S 3 = S /S 3 ) equal to k. g m6 g m4 = g m g m3 = 2K P S 6 I 6 2K P S 4 I 4 = k Calculating the various transconductances we get g m4 = 282.4 μs, g m6 = g m7 = g m8 = 707 μs, g m = g m2 = 707 μs, r ds6 = r d7 = 0.6 M, and r ds = r ds2 = 0.2 M. Assuming that the gain A v must be greater than 5000 and k = 2.5 gives g m > 72.43 μs.