Statistical Logic Cell Delay Analysis Using a Current-based Model

Statistical Logic Cell Delay Analysis Using a Current-based Model Hanif Fatei Shahin Nazarian Massoud Pedra Dept. of EE-Systes, University of Southern California, Los Angeles, CA 90089 {fatei, shahin, pedra}@usc.edu Abstract A statistical odel for the purpose of logic cell tiing analysis in the presence of process variations is presented. A new current-based cell delay odel is utilized, which can accurately copute the output wavefor for input wavefors of arbitrary shapes subjected to noise. The cell parasitic capacitances are pre-characterized by lookup tables to iprove the accuracy. To capture the effect of process paraeter variations on the cell behavior, the output voltage wavefor of logic cells is odeled by a stochastic Markovian process in which the voltage value probability distribution at each tie instance is coputed fro that of the previous tie instance. Next the probability distribution of α%v dd crossing tie, i.e., the hitting tie of the output voltage stochastic process is coputed. Experiental results deonstrate the high accuracy of our cell delay odel copared to Monte-Carlo-based SPICE siulations. Categories and Subject Descriptors: B.8. [Perforance and Reliability]: Perforance Analysis and Design Aids General Ters Algoriths, Measureent, Perforance, Design, Reliability Keywords Statistical gate tiing analysis, Crosstalk noise, Process variations. Introduction The downscaling of process technologies to 90n and below results in a significant increase in the device and interconnect anufacturing process variations of VLSI circuits. These effects can produce excessive tiing uncertainty, which in turn requires sophisticated tiing analysis techniques and tools to reduce the uncertainty. As the nuber of sources of variations increases, corner-based static tiing analysis (STA) techniques coputationally becoe very expensive. Moreover, with decreasing size of transistors and interconnect width, the variation of electrical characteristics is getting proportionally higher. The process corner approach, which used to work well, ay thus result in inaccurate estiates and suboptial designs. Statistical static tiing analysis (SSTA) has been used to address the above-entioned shortcoing of the STA. The fact that the interconnect delay ay doinate the cell delay in odern VLSI circuits has drawn attention toward producing faster and ore accurate interconnect delay odels. However, the conventional logic cell delay odels have not iproved as uch. They generally use the concept of voltage-based cell delay odeling, Perission to ake digital or hard copies of all or part of this work for personal or classroo use is granted without fee provided that copies are not ade or distributed for profit or coercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific perission and/or a fee. DAC 006, July 4 8, 006, San Francisco, California, USA. Copyright 006 ACM -59593-38-6/06/0007 $5.00. eaning the cell is pre-characterized with -D lookup tables with input slew and output load as the keys to the tables and the output slew and gate delay as the output of the tables. These look-up tables are inherently incopatible with the arbitrary shapes of a noiseaffected input wavefor, and hence, fall apart in processing noisy inputs. Current-based logic cell delay odeling has been introduced as an alternative approach to cope with the shortcoings of the conventional approaches. Authors in [] describe a current-based odel in which a pre-characterized current source is utilized. They odel the parasitics of the logic cell with a single constant capacitance at the output node. The parasitic effects are not odeled accurately in [] e.g., the Miller and input parasitic effects are ignored. Keller et al in [] present the ost recent and accurate current-based odel (referred to as KTV, for Keller, Tseng, and Verghese, throughout this paper) in handling noisy wavefors of arbitrary shapes. Siilar to [], a pre-characterized current source is used. The parasitic coponents, naely the Miller and the output capacitances, are assued to be constant regardless of the input and output voltage values. Based on our observation, these capacitive effects can vary significantly depending on cell input and output voltages. The assuption of fixed values can give rise to large inaccuracy especially for coplex cells. Furtherore, this odel does not address the effect of process variations. On the other hand, the existing statistical gate-delay odels such as [3] and [4] rely on the conventional voltage-based cell delay odeling. This class of gate delay odeling approaches cannot handle the noisy input wavefors accurately. Therefore, the statistical gate delay analysis is restricted to noiseless rap input. The objective of the present work is to devise an accurate statistical logic cell delay odel to handle noisy inputs in the presence of process variations. The existing cell delay analysis techniques either do not accurately odel the parasitic and non-linear behavior of logic cells or do not handle the process variations properly. To address the first weakness, a new current-based odel in which the cell parasitics are pre-characterized as a function of the input and the output voltage values is presented. To address the second shortcoing, a atheatical ethod is presented whereby first the sensitivities of cell odel eleents with respect to the sources of variation are characterized. The output voltage is then represented by a stochastic Markovian process. Finally, using the probability distribution of output voltage values at each tie instance, the distribution of α%v dd crossing tie of the output voltage is accurately calculated. The reainder of this paper is organized as follows. In section our current-based logic cell circuit odel is described. Section 3 describes our statistical approach to consider process variations effects. Section 4 and 5 explain the experiental results and conclusions respectively.

. Current-based Cell Delay Modeling The ain otivation for us to create a new odel is that the existing current-based odels soeties exhibit rather large errors copared to SPICE. It is crucial to use a highly accurate circuit odel for considering the effect of process variations because the circuit odel error ay doinate the error of ignoring process variations. In such a case the analysis would not benefit fro consideration of process variations.. The proposed cell delay odel Our odel shown in Figure coprises of two ain coponents, naely, ) parasitic capacitances to odel the parasitic behavior at input and output nodes and the Miller effect between the nodes, and ) a current source at the output node to odel the nonlinear behavior of the logic cell. Each coponent is a function of the input and output voltages. As a result, the proposed cell odel is represented by the following KCL equation: Vo Vi io I( Vi, Vo ) ( Co ( Vi, Vo ) CM ( Vi, Vo )) CM ( Vi, Vo ) = 0 I(V i,v o ) is deterined for each logic cell by sweeping the DC values of input and output voltages and easuring the current sourced by the cell output pin in SPICE. A -D lookup table is constructed to store I(V i,v o ) values. In addition, C M (V i,v o ) and C o (V i,v o ) values are also characterized through a series of SPICE-based transient siulations, where saturated rap input and output voltages are applied to the input and/or output nodes and output current is onitored. -D lookup tables are used to store C M (V i,v o ) and C o (V i,v o ) values. V i i i C M(V i,v o) C o(v i,v o) C i(v i) I(V i,v o) Figure. Our proposed current-based circuit odel of a logic cell. Precise estiation of the output load is crucial for accurate delay calculation of a logic cell. The input parasitic capacitances of fan-out cells should be considered as part of the load for delay calculation of the driver cell. A transient analysis based on Equation () is used to deterine C i. Vi Vo ii = ( Ci ( Vi, Vo ) CM ( Vi, Vo )) CM ( Vi, Vo ) Although C i is in fact a function of the input and output voltage values, in practice an input-voltage-dependent C i is all that can be efficiently utilized. This is because when calculating the delay of a logic cell, the output voltage values of its fanout cells are unknown. Equation () can be rewritten by substituting the output current, i o, as a function of the output load and output voltage. Arbitrary (e.g., RLC) loads can be handled by our odel; however, without loss of generality, we consider a capacitive load, C L fro here on to siplify the presentation: V o Vo Vo Vi CL Co I( Vi, Vo ) CM CM = 0 Equation (3) can be rewritten w.r.t to output voltage values: Vo ( tk ) = Vo ( tk ) ( CM ( Vi ( tk ) Vi ( tk )) I( Vi, Vo ) ) (4) C C C L o M 3. Proposed Statistical Cell Delay Model As stated earlier, it is essential to account for the variations of physical paraeters in the logic cell odel. In this paper we consider L int, V TH0, T OX, and W int as the physical paraeters of interest. The logic cell eleents (i.e., the current source and capacitive parasitics) i o V o () (3) () are represented as a function of physical paraeters of the cell to capture the process variations. More precisely, a first order (FO) odel [5] is utilized to express any logic cell eleent E as a function of the physical paraeters: E = e e X e X (5) 0... Here, e o is the noinal value of E whereas e i is the sensitivity coefficient of eleent E with respect to physical paraeter X i. X i is the variation of X i and denotes the nuber of sources of variation. We assue that X i s have independent Gaussian probability distributions. (Paraeter distribution independence can be achieved by principal coponent analysis (PCA) [6],[7].) By using the best ean squared error fit, e i s are derived fro a series of Monte-Carlobased SPICE siulations. These sensitivity values are stored in -D look-up tables (c.f. Figure.) Figure. The sensitivity-based look-up tables to odel a physical paraeter variation. Equation (4) shows how to copute the output voltage when the cell is operating under the noinal condition. By applying rando variables associated with each cell eleent, this equation can be utilized to express the output voltage wavefor distribution in the presence of process variations as detailed next. We define Stochastic First Order (SFO) odeling for of a signal wavefor W(t) as an ordered set of N FO expressions f i ( N) where f i gives the variational linear for of W(t i ) and t i denotes the i th sapling point. A SSTA calculator propagates the SFO for of the voltage wavefors at the priary inputs throughout the circuit in linear-tie in the circuit size. The key task is thus how to propagate the SFO at the input of a logic gate, {f k }, to its output node (adopting the single input change odel), thus calculating the SFO of the output voltage wavefor, {g k }. To do this, we utilize Equation (4) as follows: ( ) C f f h g g g g X (6) M k k k k = k k,0 k, j j CL Co CM j= where h k denotes the FO for of current source of Figure as looked up by the noinal values of f k and g k. Notice that C o and C M are in the FO fors. In addition, C L has been cast into the FO for. The right hand side of Equation (6) exploits the fact that the division, ultiplication and suation of FO expressions can be perfored and the result cast into a FO for. For exaple, this ay be approxiately done by linearization with respect to X i s based on Taylor series expansion. Equation (4) can be used recursively, eaning that the output voltage at each tie instance can be written as a linear function of the sources of variation. Therefore, V o (t i ) which is the suation of the noral distributions of process paraeters is odeled by a noral distribution. The fact that the distribution of the output voltage at each tie instance can be coputed fro that at the previous tie instance leads us to the concept of a stochastic Markovian process [8] as explained next. Definition : A stochastic process x(t) is called a Markovian process if the following is satisfied for every n and t <t < <t n : e0 e e e3 e4

( ( ) ( ),..., ( )) ( ( ) ( )) P X t x X t X t = P X t x X t (7) n n n- n n n- V o (t) is a Markovian stochastic process. We use this property to copute the distribution of any α%v dd crossing tie of V o (t). 3. Coputing the delay distribution As stated earlier, the current-based cell odel enables one to copute the output voltage distribution at each tie instance. However, the proble of interest is to copute the distribution of the delay or in general the distribution of any α%v dd crossing tie of the output voltage. For siplicity we noralize V o with respect to V dd. The proble can be stated as follows. Proble Stateent: Given the stochastic Markovian process V o (t i ), calculate the hitting tie probability (defined as follows:) P(T α t n ) where T α =inf {t i : V o (t i )=α} (8) By definition T α is the first tie that process V o reaches the value of α.. The hitting tie probability in Equation (8) is used to characterize the distribution of any α% crossing tie of the output voltage. By finding the hitting probability, we copute the cell delay distribution in the presence of the process variations. Lea : For a Markovian process X(t i ), P X ( t ) < α X ( t ) < α,..., X ( t ) < α = P X ( t ) < α X ( t ) < α ( n n- ) ( n n- ) This lea follows fro the Markovian process property. Theore : The hitting tie probability for the Markovian process V o (t i ) is coputed as follows: P ( T t ) = Λ where α n n ) < α V ( ti ) < α ) n if i : 0 (9) Λ = 0 otherwise Proof: P(T α t n ) = - P(T α > t n ). Without loss of generality, we assue that the output voltage is aking a low to high signal transition. Therefore, the event (T α > t n )) is equivalent to the joint event (V(t ) < α V(t ) < α V(t n ) < α), which siply states that all V o values up to t n are below α: ( α > n ) = ( ( ) < α, ( ) < α,..., ( n P ( V ( tn ) α V ( tn ) α,..., V ( t ) α ) P ( V ( tn ) α,..., V ( t ) α ) P ( V ( tn ) α V ( tn ) α ) P ( V ( tn ) α,..., V ( t ) α ) (Lea ) P ( V ( tn ) < α V ( tn P ( V ( tn ) < α V ( tn ) < α,..., V ( t P ( V ( tn ) < α,..., V ( t P ( V ( tn ) < α V ( tn P ( V ( tn ) < α V ( tn... P ( V ( t ) < α V ( t P ( V ( t P T t P V t V t V t = < < < < < = < < < < = = (0) Using the conditional probability and for P(V(t i- ) < α) > 0: ) < α V ( ti P ( V ( t ) ( ) ( - i < α V ti-) < α = () P V ( t Substituting equation () in Equation produces the desired result and concludes the proof. Equation (9) enables us to calculate the distribution of any α% crossing tie of the output voltage. The reainder of this section focuses on the calculation of probability in Equation (). The ter P(V(t i )<α) for i n can be directly calculated fro the probability distribution of the voltage at each tie instance. Definition : The bivariate noral distribution is given by: i- z P( x, x ) = exp ( ) πσ σ ρ ρ ( x µ ) ρ x µ x µ x µ σ σ σ σ ( )( ) ( ) where z = σ ρ = corr( X, X ) = and σ = cov( X, X ) σ σ () The distribution of the V o (t i ) and V o (t i- ) are correlated noral distributions (because each is a weighted linear suation of the noral distributions associated with the process.) In order to calculate the joint probability of V o (t i ) and V o (t i- ) fro Equation (), the following lea is applied to find their covariance. Lea : Suppose that the distribution of the voltage values at ties t i and t i- is given in first-order for as follows: (3) V ( t ) = a a X ; V ( t ) = b b X o i 0 i i o i 0 i i where is the nuber of sources of variation. X i s are noralized to N(0,) by appropriate coefficient scaling. The covariance of V o (t i ) and V o (t i- ) can be calculated as follows: = cov ( V ( t ), V ( t )) = E( ( V ( t ) E( V ( t ))) ( V ( t ) E( V ( t )))) σ o i o i o i o i o i o i = E ( ai Xi) ( bi Xi) = E aibi Xi E aibj X i X j j< i ( ) ( ) ( ) ( ) = a b because E X = and E X X = E X E X = 0. i i i i j i j Equation (9) along with definition and lea provide coplete inforation for coputing the probability distribution of any α% crossing tie of the output voltage. It is possible to encounter ultiple α% crossing ties. The procedure explained above can be used to iteratively find all α% crossing ties. More precisely, after the first α% crossing, a new Markovian process is considered that starts fro this hitting tie. Assuing low to high transition for the output voltage, the wavefor reaches the second hitting tie fro a higher voltage than α. The event (T α > t n ) is thus equivalent to the event (V(t ) > α V(t ) > α V(t n ) > α). Equation (9) can be easily odified to calculate the distribution of the second hitting tie for the new process, and so on. It can be shown that, for known and sall nuber of sources of variation, the algorith coplexity is O(n k ) where the pdf of the output voltage at each tie instance is discretized with k saple points. 4. Experiental Results To evaluate the proposed current-based odeling approach, it was copared with Hspice [9]. The set of experients involved various logic cells, including siple inverter and NAND gates, as well as coplex cells such as AOI (And-Or-Invert). Figure 3 shows coparison with Hspice for soe exaples of crosstalk-induced noisy wavefors given to a iniu size inverter in 30n cell library. The equivalent output wavefors generated by our odel atch the Hspice results closely. Next coparison with the KTV odel [] is presented. Figure 4 illustrates the absolute delay errors w.r.t. to Hspice for a iniu size inverter in our 30n cell library. The input line to the inverter is coupled by a 50fF capacitance and is under attack by an aggressor line. Both the victi and aggressor are driven by iniu size inverters. The cell under consideration has a FO4 load. The signal arrival tie of the input of the victi line driver is set to 0ps while that of the aggressor (i.e., the noise injection tie) is swept fro

00ps to 00ps with a tie step of ps. Copared to KTV, the accuracy of delay calculation for the iniu size inverter is iproved by 8.8% (7.3%) on average (ax), respectively. Figure 5 shows the absolute delay error trend for a siilar experient perfored on AOI cell with size 0x. The coupling value is 80fF. The accuracy iproveent in this case is 5.% (93.4%) on average (ax.).4. 0.8 0.6 0.4 0. 0 noisy input output (Our odel) output (Hspice) 0 5E-0 E-09.5E-09 E-09.5E-09 3E-09 Tie (sec) Figure 3. The actual and equivalent wavefors by our odel for soe crosstalk-induced noisy wavefors. 4.00E- 3.80E- 3.60E- 3.40E- 3.0E- 3.00E-.80E-.60E-.40E-.0E- delay error vs. HSpice (sec) Our odel KTV odel.00e- E-0.E-0.4E-0.6E-0.8E-0 Noise injection tie at cell input (sec) E-0 Figure 4. Absolute errors in calculated delay for a in size inverter E- 9E- 8E- 7E- 6E- 5E- 4E- 3E- E- delay error vs. HSpice (sec) KTV odel E- Our odel 0 E-0.E-0.4E-0.6E-0.8E-0 E-0.E-0.4E-0 Noise injection tie (sec) Figure 5. Absolute errors in calculated delay for an AOI size 0x. As discussed earlier, the shape of the wavefor greatly ipacts the delay calculation, therefore, delay and output slew etrics ay not be sufficient to odel the wavefor shape. Our current-based odel is capable of producing output wavefors whose shapes are very close to those produced by Hspice. Mean square error (MSE) is a good etric to copare wavefor shapes. Figure 6 shows MSE for our cell odel and KTV copared to Hspice. It is seen that this value is lower for our odel copared to KTV in ost of the cases. In fact, the average MSE iproveent for the inverter (AOI) for the aforeentioned experient setup is.3% (4.5%.) Next, we evaluate our statistical analysis ethodology in handling the effect of the process variations on cell output wavefor and, ore specifically, the cell delay. We perfored extensive Hspice based Monte-Carlo siulations to calculate the 50% cell delay distribution over our test-cases, naely, the iniu size inverter as well as the AOI cell with the sae experiental setup explained before. We assued 3σ variation of 5% for the sources of variation [0]. We also calculated the delay distribution using the atheatical approach presented in section 3. For each arrival tie of the aggressor (noise injection tie) we copared the ean and the variance of the 50% delay coputed by our proposed atheatical approach and that of Monte-Carlo siulation. The average and axiu error results over all noise injection ties are reported in Table..E-09.09E-09.07E-09.05E-09.03E-09.0E-09 9.90E-0 9.70E-0 9.50E-0 MSE vs. Hspice KTV odel 9.30E-0 9.0E-0 Our odel.00e-0.0e-0.40e-0.60e-0.80e-0.00e-0 Noise injection tie at cell input (sec) Figure 6. Wavefor siilarity (ean square error) coparison to Hspice for our odel and the KTV odel. Table : Average and axiu percentage error by our atheatical ethod and Monte-Carlo. Error % Mean Variance Avg error Max error Avg error Max error Inverter.% 3.9%.5% 4.4% AOI.4% 4.5%.7% 4.9% 5. Conclusions A statistical logic cell delay odel for the purpose of cell tiing analysis was presented. A new current-based cell delay odel was developed to accurately capture various cell parasitic and nonlinear effects in the coputation of output voltage wavefor in the presence of crosstalk-induced noise. A novel statistical analysis ethodology was also presented to capture the effect of process variations on the cell output wavefor. The cell output voltage wavefor was odeled by a Markovian stochastic process. Consequently the distribution of cell tiing paraeters such as α% crossing tie was coputed. Experiental results showed the high accuracy of our cell delay odel copared to the existing cell delay odels. Coparison with Monte-Carlo-based SPICE siulations shows the high accuracy of the presented atheatical approach in dealing with process variations. References [] J.F. Croix, D.F. Wong, Blade and razor: cell and interconnect delay analysis using current-based odels, Proc. DAC, pp. 386-389, 003. [] I. Keller, K. Tseng, N. Verghese, A robust cell-level crosstalk delay change analysis, Proc. ICCAD, pp.47-54, 004. [3] K. Okada, K. Yaaoka, H. Onodera, A statistical gate-delay odel considering intra-gate variability, Proc. ICCAD, pp. 908-93, 003. [4] A.Agarwal, F.Dartu, D.Blaauw, Statistical gate delay odel considering ultiple input switching, Proc. DAC, pp. 658-663, 004. [5] C.Visweswariah, K.Ravindran, K.Kalafala, S.G.Walker, S. Narayan, First-order increental block-based statistical tiing analysis, Proc. DAC, pp. 33-336, 004. [6] H. Chang, V. Zolotov, C. Visweswariah, S. Narayan, Paraeterized Block-Based Statistical Tiing Analysis with Non-Gaussian Paraeters and Nonlinear Delay Functions, Proc. DAC, pp. 7-76, 005. [7] H. chang, S. Sapatnekar, Statistical Tiing Analysis Considering Spatial Correlations Using a Single PERT-like Traversal, Proc. ICCAD, pp. 6-65, 003. [8] G.F. Lawler, Introduction to Stochastic Process, Chapan & Hall, 000.

[9] Hspice: The golden standard for Accurate Circuit Siulation, http://www.synopsys.co/products/ixedsignal/hspice/hspice.htl. [0] S. Nassif, Modeling and Analysis of Manufacturing Variations, Proc. CICC, pp. 3-8, 00.