Ausha eade et al. t. Jural f Egeerg esearch ad Applicats SSN: 8-96, l. 6, ssue, (Part - 5) February 06, pp.7-78 ESEACH ACE www.ijera.cm OPEN ACCESS Aalys f a Psitive Output Super-ift u Bst Cverter Ausha eade*, ahul Jueja**, Mah Kurwale***, Prashat Debre**** *(Departmet f Electrical Egeerg,.. M. Nagpur Uiversity, Nagpur) ** (Departmet f Electrical Egeerg,.. M. Nagpur Uiversity, Nagpur) *** (Departmet f Electrical Egeerg,.. M. Nagpur Uiversity, Nagpur) **** (Departmet f Electrical Egeerg,.. M. Nagpur Uiversity, Nagpur) ABSAC h paper presets a DC-DC cvers techique usg Psitive Output Super-lift u Bst Cverter circuit. recet treds, varius dustries DC-DC cvers has gaed greater imprtace fr varius applicats. h DC-DC cvers ca be cveietly btaed by Super-lift u Bst cverter. By emplyg vltage lift techique, utput vltage creased stage by stage arithmetic prgress. But by usg Super-lift techique, utput vltage creased gemetric prgress. Super-lift u cverters are geerally useful fr high utput vltage applicats ver the years. hese cverters ehace the vltage trasfer ga very effectively. A extesive simulat f Super-lift u Bst Cverter carried ut the bas f referece values MAAB/Simul evirmet. rder t calculate the cverter parameters MAAB prgram has bee used. Keywrds - Arithmetic Prgress, DC-DC Cverter, Gemetric Prgress, Super-ift, ltage Ga. NODUCON DC-DC Cverter circuit desig, vltage lift () ad super-lift (S) techique are ppular methd widely used fr bstg the vltage []. recet years these techiques have bee successfully emplyed DC-DC cverters ad have peed varius pprtuities t desig high vltage ga cverters. Hwever vltage lift techique the utput vltage creases stage by stage arithmetic prgress ad that super-lift techique the utput vltage creases gemetric prgress []. pwer series, the vltage trasfer ga effectively ehaced due t th techique []. hese cverters are geerally termed as; psitive utput Super-ift u Bst cverters rder t srt these cverters differet frm extg vltage lift cverters []. he series f these psitive utput super-lift cverters ca be divided t ma series ad addital series. Each ma series circuit ctas e switch S, ductrs, (-) dides ad capacitrs. he cduct duty rati, switchg frequecy f (perid =/f), the lad restive utput curret. Fr creasg the stages ly passive elemets are creased where as the umber switch t chaged ad ept ly e[5]-[7]. Assumg pwer lss durg cvers prcess, * = *. he vltage trasfer ga G: G = /. he sect describes the cmplete aalys f the Ma series circuit lie Elemetary circuit, e-lift Circuit ad riple- ift circuit. Sect reflects the varius stages f Psitive Output Super-ift Cverter. t als cvers vltage ga f varius DC- DC cverters. Sect ctas the mathematical www.ijera.cm calculat fr varius circuit parameters f Elemetary circuit f a Psitive Output Super-ift u Cverter usg a MAAB Prgram. Sect shws the simulated results f the Elemetary circuit, e-lift circuit ad riple-ift circuit f Psitive Output Super- ift u Cverter.. MAN SEES Psitive utput super-lift cverters are beg shw fr first three stages. Fr simplicity t expla, the Super- ift u cverter circuits are called as Elemetary circuit, e-lift circuit ad riple-lift circuit, respectively. hese series may be umbered as =,,.. Elemetary circuit f Psitive Output S Cverter he elemetary circuit alg with its equivalet circuits durg switch- ad switch-ff perid shw Fig.. he vltage acrss capacitr C charged t durg switch- perid. he curret flwg thrugh ductr i ad creases with put vltage durg switch- perid. he ductr curret i decreases with vltage ( - ) durg switch-ff perid (-). herefre the ripple f the ductr curret i ; * * ( ) i. () he vltage trasfer ga:. () 7 P a g e
Ausha eade et al. t. Jural f Egeerg esearch ad Applicats SSN: 8-96, l. 6, ssue, (Part - 5) February 06, pp.7-78 www.ijera.cm G he put curret i equal t ( i ic ) i i C ff i ff ic ff C ( ) ic ff i f ductace large eugh the i early equal t its average curret herefre i ff ic ff, i www.ijera.cm. () ic ad average put curret : i ( ) iff ( ) i ( ). () Csiderg =/f ad. he variat rati f ductr curret i : i / ( ) ( ). (5) ( ) f he ripple vltage f utput : Q ( ) ( ) v C C fc herefre, the variat rati f utput vltage : /. (6) fc C S D c D C c C C C C c Fig.. Elemetary circuit f Psitive Output Superlift u Bst Cverter : Elemetary Circuit diagram; Equivalet Circuit diagram durg switch- perid; Equivalet Circuit diagram durg Switch-ff perid.. e-ift Circuit f Psitive Output S Cverter he e-lift circuit btaed by addg ( -D - D -D 5 -C -C ) t the elemetary circuit. ts circuit diagram alg with its equivalet circuit durg switch- ad switch-ff shw Fig.. he capacitr C charged t put vltage. he vltage acrss capacitr C give by = ((- )/(-)) as described previus sect. he vltage acrss capacitr C charged t. he curret ductr creases with vltage durg the switch- perid ad it decreases with vltage ( - ) durg switch-ff perid (-). he ripple ductr curret i ( ) i. (7). (8) he vltage trasfer ga G. (9) Hece, the expresss fr ripples ductr curret ad curret thrugh ductr are btaed as- i i S, the variat rati f ductr curret i i / ( ) ( ). (0) ( ) f he variat rati f ductr curret i : i / ( ) ( ) ( ) ( ) ( ) f. () Ad variat rati f utput vltage : v /... () fc 75 P a g e
Ausha eade et al. t. Jural f Egeerg esearch ad Applicats SSN: 8-96, l. 6, ssue, (Part - 5) February 06, pp.7-78 www.ijera.cm D D D D 5 C C c www.ijera.cm D C C C C c C C S C c C C C c c c Fig.. e-ift Circuit f Psitive Output Super-lift u Bst Cverter: e-lift circuit diagram; Equivalet Circuit diagram durg Switch-; Equivalet circuit diagram durg Switch-ff.. riple-ift Circuit f Psitive Output S Cverter he riple-lift circuit btaed by addg ( - D 6 -D 7 -D 8- C 5 -C 6 ) t the e-lift circuit. ts circuit diagram alg with its equivalet circuit diagram durg switch- ad switch-ff are shw Fig.. he capacitr C charged t, the vltage acrss capacitr C =((-)/(-)), ad vltage acrss capacitr C =((-)/(-)). Durg switch- perid, the curret flwg thrugh ductr creases with vltage ad durg switch-ff perid (-) it decreases with vltage ( - ). Nw the ripple f ductr curret i : i ( ). (). () he vltage trasfer ga : G. (5) Hece, the expresss fr ripples ductr curret ad curret thrugh ductr are btaed as: i i ( ) i Nw, the variat rati f curret i thrugh ductr : 6 i / ( ) ( ). (6) 5 ( ) f he variat rati f curret i thrugh ductr i / ( ) ( ) ( ) ( ) ( ) ( ) f. (7) he variat rati f curret i thrugh ductr i / ( ) ( ) ( ) ( ) ( ) f. (8) he, variat rati f utput vltage : v /. (9) fc D D C D C C 6 D C C C5 C D 5 D 6 C C S D 7 D 8 C C C C 5 C 6 C C6 C C C C 5 C5 C 6 C6 C C 6 C6 Fig..riple-ift Circuit f Psitive Output Super-lift u Bst Cverter: riple-ift circuit diagram; (b ) Equivalet circuit Diagram durg Switch-; Equivalet circuit diagram durg Switch-ff. 76 P a g e
Ausha eade et al. t. Jural f Egeerg esearch ad Applicats SSN: 8-96, l. 6, ssue, (Part - 5) February 06, pp.7-78 www.ijera.cm. SUMMAY OF POSE OUPU SUPE-F UO BOOS CONEES arius stages f Psitive Output Super-lift u Bst cverters ca be arraged ascedg patter as shw Fig.. www.ijera.cm Ma Series Qutuple-ift Circuit Quadruple-ift Circuit riple-ift Circuit e-ift Circuit Elemetary circuit Fig.. arius stages f Psitive Output Super-lift u Bst cverter. Frm aalys f previus sect, fr calculatg the utput vltage ad vltage trasfer ga f Super-ift Cverter the cmm frmula give belw- G ( umber f stages) rder t shw the advatage f Super-ift u Bst Cverter, fllwg cmpar made with respect t vltage trasfer gas f varius cverters. Buc Cverter, G Frward Cverter, G N (N trasfrmer turs rati) Cu-Cverter, G Fly-bac Cverter, G N (N trasfrmer turs rati) Bst Cverter, G v Psitive Output u Cverter, G. MAHEMACA ESU Frm the desig pt f view varius circuit parameters are eed t be calculated. Hecefrth mathematical calculats fr a Elemetary Circuit f a Psitive Output Super-ift u Cverter ca be give by a MAAB prgram as give belw. Similarly, fr the calculat f parameters fr e- ift Circuit ad riple-ift Circuit ca be frmed. MAAB Prgram fr Elemetary Circuit:- clc clear all =0e; f=00e;% switchg frequecy v=60;%output vltage =0.5;% duty rati di=0.0;% ripple curret dv=0.005;% ripple vltage =/f v=v*((-)/(-))%put vltage =(v*)/(di*f) x=(*(-)^*)/(*(-)*f*)%variat ductr curret rati i=(di/)/x =(-)*i C=(*v)/(f**dv) =(dv*c)/((-)*) y=(dv/)/v%variat utput vltage rati p=v*%put pwer p=v*% utput pwer Prgram Output :- =.0000e-005 v =0 = 0.000 x =.500 i = 0.000 =0.0060 C =.0000e-006 = 0.000 y =.667e-005 p =0.00 p = 0.00 hus parameters fr Super ift cverters are give able give belw:- able Calculated Parameters usg MAAB Prgram. Parameters C = C P P ut alues 0mH μf 0.00 0.00. SMUAON ESU verify the desig ad calculat results, MAAB sftware used fr Super-ift u cverter desig. MAAB Prgram parameters fr Simulat are csidered as =0, = = =0mH, all the capacitrs i.e. C -C 8 =μf ad =0Ω fr =0.5 ad f=00hz. Switchg Pulses 0-0. 0.0 0.0 0.0 Fig.5. Wavefrm f Switchg pulses. 77 P a g e
Ausha eade et al. t. Jural f Egeerg esearch ad Applicats SSN: 8-96, l. 6, ssue, (Part - 5) February 06, pp.7-78 www.ijera.cm 0 9 0. 0. 0. 0. 0. 0.5 0.6 0.7 0.8 0.9 0.5 Fig.6. Wavefrm f put ltage t Psitive Output Super-lift cverter. 70 60 50 0. 0. 0. 0. 0. 0.5 0.6 0.7 0.8 0.9 0.5 Fig.7. Wavefrm f Output ltage fr st stage that fr Elemetary circuit f Psitive Output Superlift Cverter. 00 90 80 70 60 50 0. 0. 0. 0. 0. 0.5 0.6 0.7 0.8 0.9 0.5 Fig.8. Wavefrm f Output ltage fr d stage i.e. fr e-lift Circuit f Psitive Output Super-lift Cverter. 600 550 500 50 00 0. 0. 0. 0. 0. 0.5 0.6 0.7 0.8 0.9 0.5 Fig.9. Wavefrm f Output ltage fr rd stage i.e. fr riple-ift circuit f Psitive Output Super-ift Cverter. able Cmpar t heretical ad simulated esults f a Psitive Output Super-ift u Cverter. N. f Stages put vltage heretically calculated Output ltage Simulated Output ltage www.ijera.cm 0 0 0 60 80 50 59.78 79. 57.6 hus the utput vltages f Psitive Output Super-ift Cverter fr varius stages are btaed. We have als bserved that the utput vltage creases with addit f every stage t elemetary circuit. Fig.5 shws the wavefrm f switchg pulse f MOSFE. Fig.6 shws the put vltage wavefrm fr the Super-ift u cverter circuit. Fig.7 shws the utput vltage wavefrm f the Elemetary circuit f Psitive Output Super-ift u cverter. Fig.8 shws the wavefrm f Output ltage f e-ift Circuit f Psitive Output Super- ift u Cverter. Fig.9 shws the utput vltage wavefrm f the riple-ift circuit f Psitive Output Super-ift u cverter. hus btaed simulated utput vltage values f a Elemetary circuit, e-lift circuit ad riplelift circuit. he simulat results are shw able. he simulated vltage values are early equal t the theretically calculated results.. CONCUSON Psitive Output Super lift Cverter has bee successfully aalyzed ad simulated. t largely creases utput vltage ad vltage trasfer ga pwer circuit. he simulat results ad theretical results verified the desig ad calculats. t has bee bserved that the utput vltage has creased gemetric prgress. he circuit parameters ca be calculated by usg the MAAB prgram fr varius applicats. EFEENCES [] Silpa. N ad Chitra. J, A mprved u Cverter fr High ltage Applicats, teratal Jural f Emergg echlgy ad Advaced Egeerg, lume, ssue 5, May 0. [] Fag u ad Hg Ye, Super-lift Bst Cverter, E Pwer Electr, l. 7, ssue 7, 0. [] Muhammad H. ashid, Pwer Electrics Hadb, Device, Circuit ad Applicats, hird Edit, 0. [] Yef Bervich, Br Axelrd, tem Madar, Avraham wima, mprved u Cverter Mdificats with creasg ltage ati, E Pwer Electr, l. 8, ssue, 05. [5] Fag u, Psitive Output Super-ift Cverters, EEE rasacts Pwer Electrics, l. 8, N., Jauary 00, 05-. [6] u F.. Negative Output u-cverters, ltage ift echique, EE Prceedgs Electric Pwer Applicats, l. 6, N., March 999, 08-. [7] u F.. Duble Output u-cverters, Advaced ltage ift echique, EE Prceedgs Electric Pwer Applicats, l. 7, N. 6, Nvember 000, 69-85. 78 P a g e