ESE 570 MOS INVERTERS DYNAMIC CHARACTERISTICS 1
Usually Cdb >> Cgd & Csb >> Cgs extrinsic parasitic caps n = fan-out 1 # dbn Cload = C + #C# dbp +#C# gdn +#C# gdp +# C # int + ncgb Parasitic Caps updated 6Feb15 Kenneth Intrinsic R. Laker, University of Pennsylvania, # C# # + C dbp + Cint + n Cgb i i dbn Cgb = Cgbn+ Cgbp worst case
Cload Cdbn + Cdbp + Cint + ncgb where n = fan-out 1 3
t 0 0 V50% = / 4
0 0 V50% = / 5
0 V10% = 0.1 V90% = 0.9 6
MOS Inverter Dynamic Performance 1. ANALYSIS (OR SIMULATION): For a given MOS inverter schematic + Cload, estimate (or determine) the propagation delays τphl and/or τplh, OR the rise/fall times τrise and/or τfall.. DESIGN: For given specs for the propagation delays τphl and/or τplh, OR the rise/fall times τrise and/or τfall + Cload, determine the MOS inverter schematic. METHODS: 1. Average Current Model >PHL C load 8V HL 5V OH V 50%p 6 =C load I avg, HL I avg, HL. Differential Equation Model i C =C load d V out d V out dt=c load dt ic where dt > PHL 3. 1st Order RC Delay Model Assume Vin ideal >PHL 0.69 C load Rn 7
CALCULATION OF PROPOGATION DELAY TIMES C load 8V HL C load 5V DD V DD /6 > PHL = =C load R eff, HL I avg, HL I avg, HL C load 8V LH C load 5V DD / 06 > PLH = =C load R eff, LH I avg, LH I avg, LH t 0 0 0, t 0 0, /)] /)] 8
CALCULATION OF RISE & FALL TIMES 0 (0.9 0.1) (0.9 0.1) ic = idp - idn 0.1)] 0, 0, 0.9)] 9
Calculating Propagation Delays By Solving the Circuit Differential Equation Let's assume Vin is an ideal step-input. Two Cases 1. Vin abruptly rises => Vout falls => > PHL. Vin abruptly falls => Vout rises => > PLH idp - idn 10
1) Vin ABRUPTLY RISES CASE ->> PHL Vin(t = t0) = 0 -> Vin(t < t0) = 0 and Vout (t < t0) = LIN V50% Vout < - VT0n i Dp 0 V out =V DD V T0n C load d V out d V out i Dn dt =C load 5 6 dt i Dn V50%= / t sat 11
CMOS Static Inverter Characteristics Recall 1
1) Vin ABRUPTLY RISES CASE ->> PHL Vin(t = t0) = 0 -> V50%= / C load d V out d V out i Dn dt =C load 5 6 dt i Dn V out =0.5V DD t=t50% 50 > phl = t=t dt =C load V 0 out =V DD t sat 1 5 6dV out =C load Reff, HL i Dn 0.5V 1 1 5 6dV out 1C load V V 5 6 dv out i Dn i Dn tsat - t0 t50% - tsat V DD V T0n.=C load V DD nmos SAT DD DD T0n nmos LIN = t50% - t0 13
1) Vin ABRUPTLY RISES CASE => > PHL cont. t0 < t < tsat i = k n 5V V 6 = i Dn in T0n C kn dv out 5V in V T0n 6 = C load dt for Vin = and V DD V T0n V out V DD V50%= / dv out dv out => dt =C load i Dn= C load i Dn dt t sat tt'1sat V DD V T0n t dt =C load V 0 C load tt1sat ' t dt = k 0 n ' 1 sat t t 0 = DD 1 5 6dV out i Dn V DD V T0n 5V DD V T0n 6 V DD dv out C load V T0n k n 5V DD V T0n 6 14
1) Vin ABRUPTLY RISES CASE => > PHL cont. tsat < t < t50% kn i Dn= [5V in V T0n 6V out V out ]= i C kn dv out [5V DD V T0n 6V out V out ]= C load dt 0 V50%= / t50% 50p tt t sat ' 1 sat V50% 50p dt=c load V tsat DD V T0n 1 5 6dV out i Dn - 0.5 tsat V out V DD V T0n Vin = and Vout = V 0.5V 50% DD VT0n V = V- V out DD T0n 15
1) Vin ABRUPTLY RISES CASE => > PHL cont. Vout = V50% = 0.5 tsat tt t 0 = tsat / / ' 1 sat Vout = VDD- VT0n C load V T0n k n 5V DD V T0n 6 tsat / / / Rn 16
1) Vin ABRUPTLY RISES CASE > PHL => cont. / Recall from static CMOS Inverter: k n k 'n 5W / L6n =n 5W / L6n k R= = ' = k p k p 5W / L6 p = p 5W / L6 p DESIGN: (1) Vth kr; () τphl kn; (3) kr & kn kp 17
SOMETIMES USED APPROXIMATION FOR τphl C load tt=t =t'50% > PHL= t=t dt 1 0. kn 5V DD V T0n 6 V out =V DD dv out C load 50.5V DD 6 k n 5V DD V T0n 6 > PHL t sat V out =0.5 V DD C load V DD k n 5V DD V T0n 6 R n C load Δ is less than 10% 18
= 5 V, VGSn = 5 V and VDSn 4V => idn = idnsat = 5mA V V50% = 0.5 =.5 19
Example 6.1 cont. 1 pf V 455 16V.= [ 1ln 5 16] 3 5V 0.65 x 10 A/V 55 16V 55 16V 1 pf 16.= [ 1ln 5 16]=0.5 ns 3 5 0.65 x 10 A/V 546 4 UNITS: F F C /V = V= V =s A/V A C /s 0
COMPARISON WITH SOMETIMES USED APPROXIMATION FOR τphl = 0.5 ns Approximation for τphl 1 x 10 1 F 5V > PHL = =0.5 ns k n 5V DD V T0n 6 10 A 54 V 6 4V C load V DD where k n = i Dnsat 10 ma 3 = =0.65 x 10 A /V 5V DD V T0n 6 54 V 6 1
DD DD DD DD 0.99 ma A
Example 6. cont. 4.04 ns -3 0.99 x 10 A DD tsat tsat -6.5 x 10-10 s/v Vout Vout = 4.0V Vout = 4.5V tsat 0.31 ns 3
Example 6. cont. 0.31 ns tsat tsat Vin = 5 V 0.5 V tsat 0.5 V Vin = 5 V 3.39 ns tsat tsat 3.39 ns + 0.31 ns = 3.70 ns 4
) Vin ABRUPTLY FALLS CASE => > PLH Vout (t < t0) = 0, Vin(t = t0) = -> 0 SAT 0 < Vout - VT0p LIN - VT0p < Vout / V50%= / i Dn 0 tsat C load d V out d V out i Dp dt =C load 5 6 dt i Dp 5
CMOS Static Inverter Characteristics Recall i Dn 0 6
) Vin ABRUPTLY FALLS CASE => > PLH V50%= / C load tsat d V out d V out i Dp dt =C load 5 6 dt i Dp V out =V50% 50p t=t 50p 50% > PLH = t=t dt=c load V 0 V T0p.=C load 0 5 1 out =0 5 1 i Dp 6dV out =C load R eff, LH V50% 50p 6 dv out 1C load V 5 i Dp tsat - t0 pmos SAT 1 6dV out = t - t 50% 0 i Dp t50% - tsat T0p pmos LIN 7
) Vin ABRUPTLY FALLS CASE > PLH => cont. /. R p C load Recall from static CMOS Inverter: k n k 'n 5W / L6n =n 5W / L6n k R= = ' = k p k p 5W / L6 p = p 5W / L6 p DESIGN: (1) Vth kr; () τplh kp; (3) kr & kp kn 8
SOMETIMES USED APPROXIMATION FOR τplh C load t =t sat > PLH = t =t dt 0 kp 5V DD V T0p 6. V50%= / tsat > PLH V out =0.5 V DD V out =0 dv out C load 50.5V DD 6 k p 5V DD V T0p 6 C load V DD k p 5V DD V T0p 6 R p C load Δ is less than 10% 9
Inverter Dynamic Performance Quick Review 1. ANALYSIS (OR SIMULATION): For a given MOS inverter schematic + Cload, estimate (or determine) the propagation delays τphl and/or τplh, OR the rise/fall times τrise and/or τfall.. DESIGN: For given specs for the propagation delays τphl and/or τplh, OR the rise/fall times τrise and/or τfall + Cload, determine the MOS inverter schematic. METHODS: 1. Average Current Model >PHL C load 8V HL 5V OH V 50%p 6 =C load I avg, HL I avg, HL. Differential Equation Model d V out d V out i C =C load dt=c load dt ic st 3. 1 Order RC Delay Model >PHL 0.69 C load R n Assume Vin ideal 30
Quick Review τplh & τphl Differential Equation Model CONDITIONS for Balanced CMOS Propagation Delays, i.e. =n W W => 5 L 6 = = 5 L 6 p n p i.e. Symmetrical Inverter 31
µp 3
7 33
ALTERNATIVE APPROXIMATE DELAY DESIGN FORMULAS Using the approximate delay formulas on slides 18 and 9: > PHL C load V DD k n 5V DD V T0n 6 R n C load Wn k n ==n C ox Ln Wn C load V DD L n >PHL =n C ox 5V DD V T0n 6 > PLH C load V DD k p 5V DD V T0p 6 R p C load Wp k p == p C ox Lp Wp C load V DD L p > PLH = p C ox 5V DD V T0p 6 34
35
Example 6.3 cont. t 5V out =1V 6 V out =1V dv out dt= C load i 5lin6 Dn t 5V =4 V 6 out V out =4V 0 8.11 36
Example 6.3 cont. 8.11 Wn = 8.11 (1 µm) = 8.11 µm 8.11 µm = 10.81 µm 37
µp 38
Design for Propagation Delays Using More Realistic Model for Cload Cload i i Cdbn + Cdbp + Cint + Cgb (Wn, Wp). Cload i i Cdbn(Wn) + Cdbp(Wp) + Cint + Cgb 39
Design for Propagation Delays Using More Realistic Model for Cload cont. Cdbn (Wn) = [Wn (Y + xj)] Cj0n Keqn + (Wn + Y) Cjswn Keqn(sw) Cdbp (Wp) = [Wp (Y + xj)] Cj0p Keqp + (Wp + Y) Cjswp Keqp(sw) Cload = α0 + αnwn + αpwp α0 = YCjswnKeqn + YCjswpKeqp + Cint + Cgb αn = (Y + xj)cj0nkeqn + CjswnKeqn αp = (Y + xj)cj0pkeqp + CjswpKeqp 40
Design for Propagation Delays Using More Realistic Model for Cload cont. µp C load > PHL =7 n Wn = α0 + (αn + (Wp/Wn) αp)wn C load > PLH =7 p and Wp where Cload = α0 + αnwn + αpwp Γn and ΓP are set largely by process parameters and V DD. const. 41
C load > PHL=7 n Wn Cload = α0 + αnwn + αpwp C load > PLH =7 p Wp Cload = α0 + αnwn + αpwp Multiply and divide αpwp by Wn Multiply and divide αnwn by Wp Cload = α0 + αnwn + (αpwp/wn)wn = α0 + [αn + αpr]wn Cload = α0 + (αnwn/wp)wp + αpwp = α0 + [αn/r + αp]wp where R = Wp/Wn = constant α0 + [αn + αpr]wn τphl? Γn Wn 1 =p W p (Recall: V th = when Lp=Ln) k R =n W n α0 + [αn/r + αp]wp τplh? Γp Wp 4
Design for Propagation Delays Using More Realistic Model for Cload cont. α0 + [αn/r + αp]wp α0 + [αn + αpr]wn τphl? Γn Wn τplh? Γp where R = aspect ratio = Wp/Wn Wp Hence increasing Wn and Wp will have diminishing influence on τphl and τplh as they become large, i.e. = > Limit PHL limit τphl = Γn [αn + αp R] Wn large R = constant = limit τplh = Γp [αn/r + αp] > Limit PLH Wp large R = constant absolute minimum delays α0 = f(cint, Cgb). P avg C load V DD f 43
Design for Propagation Delays Using More Realistic Model for Cload cont. = > Limit PHL limit τphl = Γn [αn + αp R] Wn large R = constant = limit τplh = Γp [αn/r + αp] > Limit PLH absolute minimum delays Wp large R = constant 44
Design for Propagation Delays Using More Realistic Model for Cload cont. 1.6 = 3.3 V External load cap = 100 ff R = Wp/Wn =.75 Ln = Lp = 0.8 µm 1.4 τphl (ns) 1. 1.0 0.8 0.6 0.4 0. Area x τphlproduct (norm) 0.0 0 5 10 15 0 5 nmos Channel Width Wn (µm) 5.0 4.5 4.0 3.5 minimum 3.0.5.0 0 4 8 1 16 0 nmos Channel Width Wn (µm) 45
Taking Into Account Non-Ideal Input Waveform ideal Vin non-ideal Vin Vout to ideal Vin Vout to non-ideal Vin 46
st 1 Order RC DELAY MODELS Equivalent circuits used for MOS transistors Ideal switch + effective ON resistance + load capacitance. Unit nmos has effective ON resistance Rn= Run/κn & capacitance Cd. Unit pmos has effective ON resistance Rp = Rup/κp & capacitance κpcd; where transistor scale factors κn 1 and κp 1, i.e. Wn = κnwun, Wp = κpwup Cgb = Cg and Cdb = Csb = Cd for the unit n,pmos transistors and scale with κn, κp. NMOS and pmos transistor at minimum gate length (L) Capacitance directly proportional to gate width (W) Conductance directly proportional to gate width (W) Resistance is inversely proportional to gate width (W) Example Unit Transistors Example Unit Dimensions: L un=lup =< ; W un =W up =4 < 47
st 1 Order RC Elmore Delay Model > PLH Step Source 1 t 0 0 V 1 506=0 > PHL Step Source 1 t 0 0 > PLH > PHL V 1 506=V DD > PLH Rn or Rp V1(0) V1(t) Cload V 1 5t6=V DD 51 e t / R p C load 6 V DD > / R V50% = =V 51 e 50p DD V DD V50% 1 > / R C 50p e = = V DD PLH PLH p nu load > PLH =ln 56C load R p =0.69C load R p (0 -> 50%) NOTE > D =R p C load (0 -> 63%) = 1 time constant V 1 506=V DD ALSO > PHL =ln 56C load R n=0.69 C load R n 48 C load 6
nmos 1st Order RC Delay Model Equiv. Rn ASSUME: bulk and s at GND Rn = Run/κn κncd ON/ OFF κn κncg κncd Where Wn = κnwun κn 1, usually κn = 1 Recall: > PHL R n=r un C load V DD k n 5V DD V T0n 6 0.69 R n C load V DD L un 0.69 =n C ox W un 5V DD V T0n 6 iff κn = 1 49
pmos 1st Order RC Delay Model Equiv. Rp ASSUME: bulk and s at s Rp = Rup/κp ON/ OFF κp κpcg Where Wp = κpwup d κp 1, usually κp = µn/µp usually κn = 1 Recall: κpcd > PHL κpcd C load V DD k p 5V DD V T0p 6 0.69 R p C load R up V DD Lup R p= ; p 0.69 = p C ox ; p W up 5V DD V T0p 6 Where, recall Lup = Lun and Wup = Wun 50
pmos 1st Order RC Delay Model Equiv. Rp Rn ASSUME: bulk and s at s κpcd Rp = Rup/κp ON/ OFF κp κpcg Where Wp = κpwup κp 1, usually κp = µn/µp usually κn = 1 V DD Lup R p 0.69= p C ox W p 5V DD V T0p 6 R up R p= ;p W p =n W n 5 6= 5 6 Lp = p Ln L un=lup κpcd d R n W un =W up V DD Lun 0.69 =n C ox W un 5V DD V T0n 6 V DD L up =n 0.69 = p C ox W up 5V DD V T0p 6 =p.=r n Iff VT0p = VT0n SYMMETRIC INVERTER 51
st 1 Order Delay Model - τphl Estimating τphl 1,κp κp A 1 Y κp 1,κ 1 1,κ p n = fanout κpcd R /κ R = nu R p p n κpcd Wp = κpwunit nκp Cg Y 1 where Wn=Wunit => κn=1, Rn=Run Cs = Cd Rn Cd ncg τphl κp = µn/ µp = Cd Rp = Rpu/κp = Rn 5
st 1 Order Delay Model - τphl Estimating τphl Reff,HL = Rn = Rnu Reff,LH = Rp = Rpu/κp = Rn κpcd Rp κpcd κpcd nκpcg Rn/κ Rnn Y Rn Cd ncg Rp = Rn τphl Cd nκpcg Y κ CndC nc κncg Cload = (1 + κp)(cd + ncg) > PHL 0.69C load R n =0.69511; p 65C d 1n C g 6 R n ELMORE DELAY MODEL 53
st 1 Order Delay Model - τplh Estimating τplh Reff,LH = Rp = Rpu/κp = Rn κpcd Rp = Rn τplh nκpcg κpcd Rn Cd κpc nc Cg nκpcg Y κnc C Y Cd Rp = Rn nc κncg Cload = (1 + κp)(cd + ncg) > PLH 0.69 C load R n =0.69511; p 65C d 1n C g 6 R n > PHL 0.69C load R n =0.69511; p 65C d 1n C g 6 R n 54
Propagation Delay Model Summary Average Current Model C load 8V HL C load 5V OH V 50 %p 6 > PHL = I avg, HL I avg, HL C load 8 V LH C load 5V 50 % p V OL 6 > PLH = I avg, LH I avg, LH > PHL Differential Equation Model > PLH APPROX: > PHL 1st Order RC Elmore Model C load V DD k n 5V DD V T0n 6 > PLH C load V DD k p 5V DD V T0p 6 > PHL 0.69 C load R n > PLH 0.69 C load R p 55
CMOS Ring Oscillator = SYM INV t τphl τphl1 τphl3 τplh3 τ τ PLH PLH1 SYM INV => τphl = τplh 56
CMOS Ring Oscillator cont. SYM INV => τphl = τplh = τp where 1 1 f= = T 6 >p 57
Estimation of Interconnect Parasitics 58
Estimation of Interconnect Parasitics cont. crosstalk Ideal FF value: FF = 1 FF -> Increase as t/h -> Increase, W/h <- Decrease and W/L Increase FF < 00) 1 < FF 0 (See plot of FF in Fig. 6.18 of V3 & V4 of Text) Actual(1FF< value: 59
Estimation of Interconnect Parasitics cont. crosstalk Cmf = CoxFt = 30 af/um, toxf = 0.6 um and Cpa = 1 to 10 pf Cmff = PP + FF PP = Cpp F/µm * Area FF = CFF F/µm * Perimeter 60
Estimation of Interconnect Parasitics cont. 0.3 = m (PP + FF) 0.9 = m 0.6 = m 0.6 = m C gb =1800 af / = m 0.3 = m 0.6 = m 0.3 = m Cmd 0.6 = m 61
DIGITAL CIRCUIT PATH DELAY 3 5 1 S1 4 O1 O S Delays through logic blocks Net-related delays Fanout to other logic blocks Interconnect (wiring) 6
st 1 Order RC Segment Delay (Elmore Delay Model) Step Source > PLH 1 t 0 0 V 1 506=0 V1(t) 1 = V 1 5t6=V DD 51 e t / R1 C 1 6 V DD t / R C V 50%p = =V DD 51 e 6 V DD V 50 %p 1 > / R C e = = V DD PLH Step Source > PHL 1 t 0 0 PLH 1 1 1 1 V 1 506=V DD > PLH =ln 56 R1 C 1=0.69 R 1 C 1 (1 -> 50%) NOTE > D =R 1 C 1 (0 -> 63%) = 1 time constant ALSO > PHL =ln 56 R 1 C 1=0.69 R 1 C 1 > PLH => PHL =0.69 > D 63
INTERCONNECT DELAY CALCULATIONS R3 RC Tree Network > PLH Step Source 1 t 0 0 R1 Lumped RC Model for a Wire Segment S Step Source V1(0) 1 t 0 0 > PHL R V3(0) R4 C 1 V4(0) C1 R6 V6(0) 6 3 R7 V7(0) R 8 7 C6 C7 C3 4 R5 C4 5 V5(0) C5 8 V (0) 8 C8 1. Lump total wire resistance of each wire segment into single Rj between nodes in network.. Lump total capacitance into single node capacitor to GND. 3. Model RC tree Topology: (a) Single input node S ; (b) All Ci between node i and GND; 4. Unique resistive path from source node S to any node k (k S). 64
INTERCONNECT DELAY CALCULATIONS RC Tree Network Step Source 1 R1 0 S R3 R C3 R4 C 1 C1 Elmore delay at node i 3 4 R5 C4 R6 6 R7 C6 R8 7 C7 5 C5 8 C8 N > PLH =0.69> Di =0.69 C k R ik where R ik = R j 3 R j :[ path5s 3 i6 path 5S 3 k 6] k =1 st 1 Order Time-Constant Model for the Net @ node i. Rik is the shared path resistance Elmore delay at node 7 >D7 = R1 C 11 R 1 C 1 R1 C 31R 1 C 41 R 1 C 5 15 R1 1R 6 6 C 615 R1 1R 6 1 R 7 6 C 7 15 R 1 1R 61 R7 6C 8 R78 R71 R7 R74 R75 R73 R77 R 76 65
INTERCONNECT DELAY CALCULATIONS Elmore delay at node i N >Di = C k Rik k =1 Rik = R j 3 R j :[ path5 S 3 i6 path5 S 3 k 6] Elmore delay at node 5 : > D5 =? 66
INTERCONNECT DELAY CALCULATIONS Elmore delay at node i N >Di = C k Rik k =1 Rik = R j 3 R j :[ path 5S 3 i6 path 5S 3 k 6] Elmore delay at node 5 R55 >D5 = R1 C 1 15 R11 R 6C 15 R11 R 6C 3 15 R11 R 1 R 4 6 C 4 15 R11 R 1 R4 1 R5 6C 5 R53 R5 R51 R54 1R 1 C 6 1R 1 C 7 1R 1 C 8 R56 R57 R58 Elmore delay at nodes 1 and 8 >D1= R1 C 11 R1 C 1R1 C 3 1R1 C 4 1 R1 C 51 R1 C 61 R1 C 71R1 C 8 >D8 = R1 C 1 1 R1 C 1R1 C 3 1R1 C 4 1 R1 C 5 15 R11 R6 6C 6 15 R11 R6 1 R7 6C 7 15 R1 1R 61R 7 1R 8 6C 8 67
INTERCONNECT DELAY CALCULATIONS RC Chain or Ladder Network S R1 1 C1 Wire Length L R3 R C Elmore delay at node N RN 3 C3 N O CN N N j k =1 j=1 k =1 > DN =0.69 C k R Nk = C j R k Let the RC Ladder Network be uniform, i.e. Ri = rl/n for all i N and Cj = cl/n for all j N such that N j cl rl L N 11 > DN = 5 6 5 6= 5rc1 rc13 rc1...1n rc6=rc L 5 6 N N j=1 N k =1 N rc L For large N, as N 3 (distributed RC line) > DN 3 > PLH =0.69 > DN 0.35 r c L 68
Practical Interconnect Length Rule-of-Thumb > PHLinv =0.69C load R n S > PLHwire =0.35 r c L rl/n rl/n rl/n rl/n cl/n cl/n cl/n cl/n Rn, κnc Rp, κpc > PLHtotal => PLHinv 1> PLHwire =0.69 C load R n10.35 r c L Let the goal be for the layout to enable > PLHtotal > PLHinv > PLHtotal > PLHinv > PLHwire > PLHinv 0.35 r c L 0.69C load R n 4 4 > PLHinv 0.69 C load R n L = 0.35 r c 0.35 r c 4 4 1 > PLHinv 1 0.69 C load R n L = 10 0.35 r c 10 0.35 r c 69
70
vin vout vin, vout 0 1 T P avg = 0 v 5t 6i 5t 6dt T v SDp 5t 6=V DD v out 5t 6 v DSn 5t 6=v out 5t 6 dt 1 T / 1 T P avg 0 v DSn 5t 6 i Dn 5t 6 dt1 T / v SDp 5t6 i Dp 5t 6 dt T T dv out dv out i Dn 5t 6= C load i Dp 5t 6=C load dt dt 71
d v out d v out 1 T / 1 T P avg 0 v out 5 C load 6dt 1 T / 5V DD v out 65C load 6 dt T dt T dt vin, vout 0 1 0 1 V P avg V C load v out 5t 6dv out 1 0 C load 5V DD v out 5t 66 dv out T T DD DD v out =0 v out 1.= [ C load ] T v out =V DD v out =V DD v out 1 1 [C load 5V DD v out 6] T v out =0 7
v out =0 v out 1 P avg [ C load ] T v 1.= C load V DD T out =V DD v out =V DD v out 1 1 [C load 5V DD v out 6] T v out =0 P avg C load V DD f f = operating frequency or switching frequency Units calculation P avg C load V DD Q 1 f = F V Hz= V s = A V =W In General: V C load 3C total Ctotal = total chip capacitance 73
P avg C load V DD f EXAMPLE: Consider 0.1 µm CMOS chip with a clock rate of 100 MHz, = V and an average Cload = 3 ff per gate. (a). What is the dynamic power dissipation per gate? (b). If the chip incorporates 00,000 gates, what is the power dissipation for the chip? (a). P avg / gate 3 x 10 (b). 15 F 6 1 4V 100 x 10 s =1.= W / gate gate P avg = P avg / gate 00,000 gates 1.= W / gate x 105 gates=0.4 W PESSIMISTIC -> NOT ALL 00,000 GATES SWITCH AT THE SAME TIME OR AT 100 MHZ! C EFF =9C load P avg C EFF V DD f CEFF = effective capacitance -> avg. capacitance switched per cycle at f Hz. e.g. if α = 0., Pavg = 0.4 W -> 48 mw 74
Buffer to Drive Large CLOAD standard CMOS logic on die INV1 Buffer CLOAD A DESIGN STRATEGY: Make buffer (W/L)n and (W/L)p sufficiently large to drive CLOAD with a specified τp. How do you feel about this design strategy? 75
Buffer to Drive Large CLOAD standard CMOS logic on die Buffer INV1 CLOAD Cin A DESIGN STRATEGY: Make buffer (W/L)n and (W/L)p sufficiently large to drive CLOAD with a specified τp. How do you feel about this design strategy? What happens to Cin as (W/L)n and (W/L)p sufficiently large? What is the impact on the standard CMOS logic on the die? 76
Super-Buffer to Drive Large CLOAD standard CMOS logic on die INV1 CLOAD PROBLEM: A minimum sized inverter drives a large load CLOAD, leading to excessive delay, even with a large buffer (large W/L). CLOAD SOLUTION: Insert N inverter stages in cascade with increasing W/L between INV1 and load CLOAD. The total delay through N smaller stages will be less than the delay through a single large stage driving CLOAD. N=3 CLOAD 77
Super-Buffer to Drive Large CLOAD cont. INV1 Stage-0 CLOAD NOTE for CMOS INV: Cd = Cdbn + Cdbp Cg = Cgbn + Cgbp cascade a -> stage scale factor > 1 Wni = aiwn0, Lni = Ln0 and Wpi = aiwp0, Lpi = Lp0 for i = 0, 1,,..., N Stage load capacitances Cloadi are also scaled by a Cloadi = ai Cload0 = ai (Cd + acg) for i = 0, 1,,.., N when i = N: CloadN = an Cload0 = an (Cd + acg) => let CLOAD = an(acg) = an+1cg N+1 CLOAD/Cg = a ln 5C LOAD / C g 6 => N = 1 ln a N is rounded up to nearest integer value. 78
Super-Buffer to Drive Large CLOAD cont. CLOAD CLOAD NOTE: ALL inverters Stage-0 through Stage-N have the same gate delay > PHL 1> PLH C load > p= =7 W Let τ0 = gate delay for INV1 (with a = 1) in a ring oscillator with load Cload = Cd + Cg Cdd 1a C g Cdd1a C g >d0 C load0 /W 0 C For Stage-0: = = > p0 =>0 >0 5C Cdd 1C g 6/ W 0 C dd 1C g Cdd 1C g 79
Super-Buffer to Drive Large CLOAD cont. Cdd 1a C g > p0 C load0 /W 0 CCdd1a C g For Stage-0: = = > p0 =>0 Cdd 1C g 6/W 0 orc dd 1C g Cdd 1C g >0 5C C Cd 1a C g > p1 C load1 /a W 0 5a Cdd 1a C g 6/ a For Stage-1: = = > p1=>0 => p0 5C C 1C 6/W C 1C C 1C C >0 Cdd g 0 g g dd dd Cd 1a C g > pn C load1 /a N W 0 5a N C Cdd 1a N 11 C g 6/a N C = = > pn =>0 => p0 For Stage-N: C 5C 1C 6/ W 1C 1C C >0 Cdd g 0 g g dd dd Cdd 1a C g Choose N and a TOTAL DELAY >total =5 N 116 > p0 =5N 116 >0 C C dd 1C g to minimize τtotal 80
Super-Buffer to Drive Large CLOAD cont. Cdd 1a C g C >total =5 N 116 >0 Cdd 1C g C ln 5C LOAD / C g 6 N 11= ln a Cd 1a C g ln 5C LOAD /C g 6 C >total = >0 ln a C dd 1C g Wni = aiwn0 Wpi = aiwp0 TO MINIMIZE τtotal: d >total C LOAD 1/a CCdd1a C g Cg 1 =>0 ln 5 6 [ 1 ]=0 Cdd 1C g ln a CCdd1C g da Cg 5ln a6 C =0 Cdd aopt [ln a opt 1]= Cg Cd ln a opt =1 a opt =e 1 =.718 ln 5C /C g 6 is rounded up to nearest Since Cd > Cg, Cd =N0=is onlyload an academic special case. 1 N integer value. ln aopt Since Cd > Cg, then Cd = 0 is only an academic special case. aaopt e=.718 opt e=.718 81
Super-Buffer to Drive Large CLOAD cont. EXAMPLE: Design a Buffer using a scaled cascade of inverters to achieve minimum total delay ttotal when CCLOAD = 100 CCgg. Consider the case where LOAD 100 Cd = Cg. Cd = Cg => plot aopt as function of Cd/Cg: aopt = 4.35 => ln aopt = 1.47 ln 5C LOAD /C g 6 ln aopt 4.61 ln 5C LOAD /C g 6 N= 1=.133 N =3 1.47 Plot using Excel, MathCad, MatLab. N 11= a opt =4.35 i 1 Cd/Cg = e Cdd Cg =aopt [ln aopt 1] C LOAD 4 1.47 e Suitable =100 e Design? =365 Sub-Optimum Cg Wni/Wn0 Wpi/Wp0 (aopt)1 = 4.35 (aopt)1 = 4.35 3.13 1.47 (aopt) = 18.9 (aopt) = 18.9 3 (aopt)3 = 8.31 (aopt)3 = 8.31 rd N+1 with little impact. 3 stageccan be/celiminated NOTE: = a = 8 for N = LOAD g = 358 >> 100 for N = 3 8