Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: CMOS Inverter: Visual VTC. Review: CMOS Inverter: Visual VTC

Similar documents
ESE 570: Digital Integrated Circuits and VLSI Fundamentals

! Inverter Power. ! Dynamic Characteristics. " Delay ! P = I V. ! Tricky part: " Understanding I. " (pairing with correct V) ! Dynamic current flow:

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Midterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

THE INVERTER. Inverter

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter

Lecture 14 - Digital Circuits (III) CMOS. April 1, 2003

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)

ECE321 Electronics I

EEC 118 Lecture #5: CMOS Inverter AC Characteristics. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

Lecture 11 VTCs and Delay. No lab today, Mon., Tues. Labs restart next week. Midterm #1 Tues. Oct. 7 th, 6:30-8:00pm in 105 Northgate

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Total Power. Energy and Power Optimization. Worksheet Problem 1

The Physical Structure (NMOS)

Lecture 12 Circuits numériques (II)

EE5311- Digital IC Design

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)

CMOS Inverter (static view)

ECE 342 Electronic Circuits. Lecture 35 CMOS Delay Model

Lecture 13 - Digital Circuits (II) MOS Inverter Circuits. March 20, 2003

ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals

Practice 7: CMOS Capacitance

ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals

2007 Fall: Electronic Circuits 2 CHAPTER 10. Deog-Kyoon Jeong School of Electrical Engineering

5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1

! Energy Optimization. ! Design Space Exploration. " Example. ! P tot P static + P dyn + P sc. ! Steady-State: V in =V dd. " PMOS: subthreshold

MOS Transistor Theory

High-to-Low Propagation Delay t PHL

CHAPTER 15 CMOS DIGITAL LOGIC CIRCUITS

EECS 141: FALL 05 MIDTERM 1

! Dynamic Characteristics. " Delay

EEE 421 VLSI Circuits

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Restore Output. Pass Transistor Logic. How compare.

The CMOS Inverter: A First Glance

DC and Transient Responses (i.e. delay) (some comments on power too!)

EEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EE5311- Digital IC Design

MOSFET and CMOS Gate. Copy Right by Wentai Liu

The CMOS Inverter: A First Glance

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance

ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

ECE 342 Solid State Devices & Circuits 4. CMOS

EE 560 MOS INVERTERS: DYNAMIC CHARACTERISTICS. Kenneth R. Laker, University of Pennsylvania

University of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA

Announcements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power

Integrated Circuits & Systems

! MOS Capacitances. " Extrinsic. " Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications

EEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

ECE 546 Lecture 10 MOS Transistors

Electronic Devices and Circuits Lecture 15 - Digital Circuits: Inverter Basics - Outline Announcements. = total current; I D

VLSI Design and Simulation

Digital Microelectronic Circuits ( ) Ratioed Logic. Lecture 8: Presented by: Mr. Adam Teman

EEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation

Check course home page periodically for announcements. Homework 2 is due TODAY by 5pm In 240 Cory

Digital Microelectronic Circuits ( )

EE141Microelettronica. CMOS Logic

Digital Integrated Circuits

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: 1st Order RC Delay Models. Review: Two-Input NOR Gate (NOR2)

9/18/2008 GMU, ECE 680 Physical VLSI Design

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Digital Integrated Circuits A Design Perspective

COMP 103. Lecture 16. Dynamic Logic

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

EE115C Digital Electronic Circuits Homework #3

ECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120

Digital Integrated Circuits A Design Perspective

Lecture 4: CMOS review & Dynamic Logic

Integrated Circuits & Systems

Digital Microelectronic Circuits ( ) The CMOS Inverter. Lecture 4: Presented by: Adam Teman

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model

Miscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]

EE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Name: Answers. Grade: Q1 Q2 Q3 Q4 Q5 Total. ESE370 Fall 2015

EECS 141 F01 Lecture 17

MOS Transistor Theory

Lecture 6: DC & Transient Response

Chapter 5. The Inverter. V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov Inverter

Lecture 5: DC & Transient Response

Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model

Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo

Step 1. Finding V M. Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since

CMOS scaling rules Power density issues and challenges Approaches to a solution: Dimension scaling alone Scaling voltages as well

DC & Transient Responses

Power Dissipation. Where Does Power Go in CMOS?

EE 434 Lecture 33. Logic Design

Dynamic operation 20

Lecture 5: DC & Transient Response

Lecture 23. CMOS Logic Gates and Digital VLSI I

Lecture 4: DC & Transient Response

Pass-Transistor Logic

4.10 The CMOS Digital Logic Inverter

EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University

Integrated Circuits & Systems

Transcription:

ESE 570: Digital Integrated Circuits and LSI Fundamentals Lec 0: February 4, 207 MOS Inverter: Dynamic Characteristics Lecture Outline! Review: Symmetric CMOS Inverter Design! Inverter Power! Dynamic Characteristics Delay 2 Review: CMOS Inverter: isual TC Review: CMOS Inverter: isual TC - out = in - T0p - out = in - T0p th T0p out = in - T0n th T0p out = in - T0n th th th T0n th T0n - - th - th T0n IL - IH T0n IL IH 3 4 Review: CMOS Inverter: Design/Sizing Review: Noise Margin Example T 0n th = ( T 0 p ) = 2 T 0 p th # th Important design Eq. for CMOS inverter TC. Compute the noise margins for a symmetric CMOS inverter has been designed to achieve th = /2, where = 5 and T0n = - T0p =. If th is set to ideal case: th = 2 = 2 T 0 p 2 = 2 2 T 0 p # 2 # 2 ideal th If T0n = - T0p = - T0 (symmetric CMOS) NM H = NM L = 2.25 RECALL (with = 5 ). NM H, NM L > /4 =.25 = 2 T 0 p 2 = k If, also 2 2 T 0 = R symetric = µ = W n n W p = µ n # 2 # 2 T 0 µ p W p W n µ p 2. Ideal NM => NM H = NM L = 2.5 > /2 5 6

Power Inverter Power! P = I! Tricky part: Understanding I (pairing with correct ) 8 Static Current Switching Currents! P = I static! Dynamic current flow:! If both transistor on: Current path from dd to Gnd Short circuit current 9 0 Currents Summary Currents Summary! I changes over! I changes over! At least two components! At least two components I static no switching I static no switching I switch when switching I switch when switching and I sc and I sc CLK φ ramp_enable RAMP 2 2

Switching Currents Switching! I total (t) = I static (t)i switch (t) Dynamic Power! I switch (t) = I sc (t) (t) I static I sc 3 4 Charging Switching Energy focus on (t)! (t) why is it changing? I ds = f( ds, gs ) and gs, ds changing I DS ν sat C OX W GS T ( DSAT 2 ) W ) I DS = µ n C OX ( # L GS T ) DS 2, DS. 2 - I sc I static 5 6 Switching Energy focus on (t) Switching Energy! Do we know what this is? (t) E = P(t) = I(t) dd = dd E = P(t) = I(t) dd = dd 7 8 3

Switching Energy Switching Energy! Do we know what this is?! Do we know what this is? Q = (t) Q = (t)! What is Q? E = P(t) = I(t) dd = dd E = P(t) = I(t) dd = dd 9 20 Switching Energy Switching Energy! Do we know what this is?! Do we know what this is? Q = (t) Q = (t)! What is Q? E = P(t) = I(t) dd = dd Q = C =! What is Q? E = P(t) = I(t) dd = dd Q = C = E = C dd 2 Capacitor charging energy 2 22 Switching Power! Every output switches 0# pay: E = C 2 Switching! P dyn = (# 0# trans) C 2 / Short Circuit Power! # 0# trans = ½ # of transitions! P dyn = (# trans) ½C 2 / 23 24 4

Short Circuit Power! Between TN and dd - TP Both N and P devices conducting Short Circuit Power! Between TN and dd - TP Both N and P devices conducting! Roughly: I sc in dd-thp thn dd dd Isc 25 out 26 Peak Current Peak Current! I peak around dd /2 If TN = TP and sized equal rise/spring I DS ν sat C OX W GS T ( DSAT 2 )! I peak around dd /2 If TN = TP and sized equal rise/spring I DS ν sat C OX W GS T ( DSAT 2 ) I t ( peak sc 2 ) in dd-thp thn dd in dd-thp thn dd dd Isc dd Isc out 27 out 28 Peak Current! I peak around dd /2 If TN = TP and sized equal rise/spring I DS ν sat C OX W GS T ( DSAT 2 ) I t ( peak sc 2 ) # E = dd I peak t sc ( in 2 dd dd-thp thn dd Isc Short Circuit Energy! Make it look like a capacitance, C SC Q=I t Q=C E = dd I peak t sc # # 2 E = dd Q SC E = dd (C SC dd ) = C SC 2 dd out 29 30 5

Short Circuit Energy! Every switch (0# and #0) Also dissipate short-circuit energy: E = C 2 Dynamic Characteristics Different C = C sc C cs fake capacitance (for accounting) 3 32 Inverter Delay Inverter Delay! Caused by charging and discharging the capacitive What is the? 33 34 Inverter Delay Inverter Delay C gb = C gbn C gbp C = C # dbn C# dbp C# gdn C# gdp C int C gb 35 36 6

Inverter Delay Inverter Delay n = fan-out Usually C db >> C gd C sb >> C gs C C # dbn C# dbp C int C gb C C dbn C dbp C int nc gb 37 38 Propogation Delay Definitions Propogation Delay Definitions 0 t t 0 50 = /2 39 40 Propogation Delay Definitions Rise/Spring Times 4 42 7

MOS Inverter Dynamic Performance! ANALYSIS (OR SIMULATION): For a given MOS inverter schematic and C, estimate (or measure) the propagation delays! DESIGN: For given specs for the propagation delays and C, determine the MOS inverter schematic MOS Inverter Dynamic Performance! ANALYSIS (OR SIMULATION): For a given MOS inverter schematic and C, estimate (or measure) the propagation delays! DESIGN: For given specs for the propagation delays and C, determine the MOS inverter schematic METHODS:. Average Current Model METHODS: 2. Differential Equation Model Δ C HL = C OH 50 i C d out d = C out i C τ PLH C Δ LH 50 OL Assume in ideal or τ PLH Assume in ideal 43 44 MOS Inverter Dynamic Performance! ANALYSIS (OR SIMULATION): For a given MOS inverter schematic and C, estimate (or measure) the propagation delays! DESIGN: For given specs for the propagation delays and C, determine the MOS inverter schematic METHODS: 3. st Order RC delay Model Method Average Current Model 0.69 C R n τ PLH 0.69 C R p Assume in ideal 45 Calculation of Propagation Delays Calculation of Propagation Delays Δ C HL = C OH 50 Δ C HL = C OH 50 τ PLH C Δ LH 50 OL τ PLH C Δ LH 50 OL 47 48 8

Calculation of Propagation Delays Calculation of Rise/Spring Times Δ C HL = C OH 50 τ fall C Δ 90 0 I avg,90 0 90 0 I avg,90 0 τ PLH C Δ LH 50 OL τ rise C Δ 0 90 I avg,0 90 90 0 I avg,0 90 49 50 Calculation of Rise/Spring Times Calculation of Rise/Spring Times τ fall C Δ 90 0 I avg,90 0 90 0 I avg,90 0 τ fall C Δ 90 0 I avg,90 0 90 0 I avg,90 0 τ rise C Δ 0 90 I avg,0 90 90 0 I avg,0 90 τ rise C Δ 0 90 I avg,0 90 90 0 I avg,0 90 5 52 Calculating Propagation Delays Method 2 Assume in is an ideal step-input Differential Equation Model Two Cases. in abruptly rises => out Springs => 2. in abruptly Springs => out rises => τ PLH i DP - i Dn 54 9

Case : in Abruptly Rises - Case : in Abruptly Rises - 55 56 Case : in Abruptly Rises - Case : in Abruptly Rises - 57 58 Case : in Abruptly Rises - Recall: CMOS Inverter: isual TC - out = in - T0p th T0p out = in - T0n th out = T0n th T0n - th - T0n IL IH 59 60 0

Case : in Abruptly Rises - Case : in Abruptly Rises - saturation linear t 0 #t t #t 50 T 0 n /2 =C d out C T 0 n d out out = T0n d C out i Dn d = C out i Dn = t=t 50 out= /2 = C t=t 0 out= ) d out i Dn ( =C /2 ) d out C ) i Dn ( T 0 n i Dn ( T 0 n t 0 #t t #t 50 d out out = T0n 6 saturation: i Dn = 2 ( in )2,sat T 0 n C 2 ) 2 # T 0 n d out,sat = d 2 ( out T 0n )2 2C,sat = T 0n ) 2 62 Case : in Abruptly Rises - Case : in Abruptly Rises - saturation linear t 0 #t t #t 50 T 0 n /2 =C d out C T 0 n ( ) d out linear: i Dn = 2 ( ) 2 in T 0n out out /2,lin T 0 n ( 2 2( ) 2 T 0n out out # ),lin = 2C /2 k n #( 2 ) out 2 T 0 n out ),lin = 2C 2 ) ln out #( 2 ) out ) d out d out out= /2 out= T 0 n out = T0n 63,lin = 2C 2 ) ln # out ( 2 ) ( out ) C,lin = ) ln # 2 ) 2 ( 2 out= /2 out= T 0 n 64 Case : in Abruptly Rises - Case : in Abruptly Rises - saturation linear saturation linear t 0 #t t #t 50 T 0 n /2 =C d out C T 0 n d out out = T0n t 0 #t t #t 50 T 0 n /2 =C d out C T 0 n d out out = T0n 2C,sat = T 0n C τ ) 2 PHL,lin = ) ln 2 ) 2 # 2 2C,sat = T 0n ) 2 C,lin = ) ln 2 ) 2 # 2 2C = T 0n ) C 2 ) ln 2 ) 2 # 2 2C = T 0n ) C 2 ) ln 2 ) 2 # 2 R n 65 ) 2 =C T 0n ) ) ln # 2( ), T 0n (. 2-66

Case : in Abruptly Rises - Case : in Abruptly Rises - ) 2 =C T 0n ) ) ln # 2 ), (. 2 - ) 2 =C T 0n ) ) ln # 2 ), (. 2 - Recall from static CMOS Inverter: T 0n th = ( T 0 p ) = 2 T 0 p th # th Recall from static CMOS Inverter: T 0n th = ( T 0 p ) = 2 T 0 p th # th DESIGN: () th ; (2) ; (3) k p DESIGN: () th ; (2) ; (3) k p () th ; (2) τ PLH k p ; (3) k p 67 68 Idea Admin! P tot = P static P dyn P sc Can t ignore Static Power (aka. Leakage power)! Propogation Delay Average Current Model Differential Equation Model st Order Model! HW 4 due Thursday, 2/6 69 70 2