Lecture 23 P-MOS Device and CMOS Inverters A) P-MOS Device Structure and Oeration B) Relation of Current to t OX, µ V LIMIT C) CMOS Device Equations and Use D) CMOS Inverter V OUT vs. V IN E) CMOS Short Circuit Current Reading: Schwarz and Oldham,. 518-526
CMOS = Comlementary MOS (PMOS is a second Flavor) source n N-MOS gate oxide insulator P n drain In this device the gate controls electron flow from source to drain. It is made in -tye silicon. The NEW FLAVOR! P-MOS In this device the gate controls hole flow from source to drain. It is made in n-tye silicon. source P-MOS n-tye Si gate drain
In this device the gate controls hole flow from source to drain. It is made in n-tye silicon. PMOS source P-MOS gate drain n-tye Si V GS > V t + - gate drain What if we aly a big negative voltage on the gate? If V GS > V t (both negative) source n-tye Si then we induce a + charge on the surface (holes)
NMOS Body -tye Source n-tye Drain n-tye V GS ositive V T ositive V DS ositive I D ositive (into drain) G S D I n D n 1 ma (for I DS = 1mA) I D B NMOS and PMOS Comared V GS =3V V GS =0 PMOS Body n-tye Source -tye Drain -tye V GS negative V T negative V DS negative I D negative (into drain) S G D 1 ma (for I DS = -1mA) I D B n V GS = 3V V GS =0 I D 1 V DS 2Coyright 3 42001, Regents of University of California 1 2 3 4 V DS
CMOS Challenge: build both NMOS and PMOS on a single silicon chi NMOS needs a -tye substrate PMOS needs an n-tye substrate Requires extra rocess stes S G D D G oxide n n n-well P-Si S
Why do we want PMOS? We already have the ideal switch to connect any node to ground. An NMOS transistor with gate held high has a very low resistance and essentially switches a node to ground (logic low). We also need a switch to switch nodes to whatever voltage is chosen as logic high (tyically V DD ). V DD inut outut inut outut A PMOS transistor is just the ticket. It is recisely as ideal a switch for connections to high as NMOS transistors are for connections to low. What s cool is that there is little more to learn about PMOS. These devices are essentially the same as NMOS excet all signs on V and I are reversed.
THE BASIC STATIC CMOS INVERTER For V in > 1.5V NMOS on, PMOS off V DD V DD PMOS source drain V in V out V out = 0 v in v out drain NMOS For V in < 1V NMOS off, PMOS on source V DD Examle for Discussion: NMOS: V Tn = 1V V in V out V out = V DD PMOS: V T = -1V Let V DD = 2.5V
MOS Current Levels The current values deend on the roerties of silicon, geometrical layout, design style and technology node. n-tye silicon has a carrier mobility that is 2 to 3 times higher than -tye. The current roortion to the gate width/length in the geometrical layout. Design styles may restrict all NMOS and PMOS to be of a redetermined fixed size. The current er unit width of the gate increases nearly inversely with the linewidth.
Relation of Current to Physical Parameters C ox = ε t ox ox = I D Mobility of carriers Oxide thickness W = µ ncox ( VGS VT ) V L Geometrical Layout n OUT SAT n ( 14 8.85x10 F / cm)( 3.9) 7 2 6x10 7 cm Excess Gate drive Voltage of scattering velocity limit ( 2 µ = 500 cm Vs) ( 2 µ cm Vs) = 150 / n / 4 = 5.75x10 F / cm 4 ( V / cm) 0.25x10 cm = 0. V VOUT SAT n = ECrit L = 10 25
CMOS Device Parameters at 0.25µm Gate length is 0.25 µm = 250 nm V DD = 2.5V V T (V) V OUT-SAT (V) k (µa/v 2 ) NMOS PMOS 0.43 0.4 0.63 1 100 25 I I These arameters are from re-fitting I vs. V data in Chater 3 of the EECS 141 Text Book by Rabaey with saturation current model we are using in EE42. OUT SAT D = k D ( V ) IN VTD VOUT SAT D 0.375 ( 2 100µ A/ V )( )(2.5V 0.43V )(0.63V ) = 196 A OUT SAT D = µ 0.25 Here V IN = V DD is used to estimate the maximum I DS
Saturation Current 0.25 µm NMOS Model Current I OUT only flows when V IN is larger than the threshold value V TD and the current is roortional to V OUT u to V OUT-SAT-n where it reaches the saturation current µ A I n = 100 V 2 = 77.5µ A 0.375 0.25 W ( 1.25V 0.4V ) 0.63V ( V ) IN VTn VOUT SAT n IOUT SAT n = k ' n L n Note that we have added an extra arameter to distinguish between threshold (V TD ) and saturation (V OUT-SAT-D ). Examle: I OUT (µa) V IN = 1.25V k 100 n = 100 µa/v 2 W = 0.375µm Saturation (with V OUT ) V Tn = 0.43V V DD = 2.5V V OUT-SAT-n = 0.63V 60 20 Here V DD /2 is used to estimate the shortcircuit current Linear (with V OUT ) 0 3 2.5 V OUT (V)
Saturation Current 0.25 µm PMOS Model Current I OUT only flows when V IN is smaller than V DD minus the threshold value V TU and the current is roortional to (V DD -V OUT ) u to (V DD -V OUT-SAT- ) where it reaches the saturation current I OUT SAT Examle: k = 25 µa/v 2 V T = 0.4V V OUT-SAT- = 1V µ A I = 25 V 2 = 63.8µ A 0.75 0.25 = k ' W L ( 2.5V 1.25V 0.4V ) W = 0.75µm V DD = 2.5V ( V ) DD VIN VT VOUT SAT 1V 100 60 20 Saturation (with V OUT ) 0 3 2.5 V OUT (V) I OUT (µa) V IN = 1.25V Here V DD /2 is used to estimate the shortcircuit current
Voltage Transfer Function for the 0.25 µm CMOS Inverter 2.5 V Tn V OUT-SAT-U V OUT (V) V OUT-SAT-D 0.6 3 1.5 0 V OUT = V IN V M 0 1.5 2.5 Vertical section due to zero sloe of I OUT vs. V OUT in the saturation region of both devices. The value of VM will deend on the (W/L) s V T This grah is for (W/L)n = 1.5 (W/L) = 3.0 V IN (V)
Finding V M for 0.25 µm Inverter At V M, 1) V OUT = V IN =V M 2) Both devices are in saturation 3) I OUT-SAT- n = I OUT-SAT- ' W IOUT SAT n = kn VIN V L I OUT SAT = k ' W L n ( ) Tn V OUT SAT n ( V ) DD VIN VT VOUT SAT SubstituteV M Result will deend on (W/L) ratios. = Solve for V M For (W/L) n = 1.5 and (W/L) = 3.0 V M is 1.17V
CMOS Short-Circuit Current When V IN is at an intermediate value both the NMOS and PMOS can conduct simultaneously. If in addition V OUT is at an intermediate value, both the NMOS and PMOS devices will have sizeable currents and only the difference between their currents will be flowing through the load. Most of the current will simly flow from the ower suly through both devices to ground as what is termed a shortcircuit current. Examle for the above inverter at the an instant V IN = 1.25V and V OUT = 1.25V I = 63.8 µa and I n = 77.5 µa This means 63.8 µa flows directly to ground and only 13.7 µa flows out of the load and into the NMOS and on to ground.
Lecture 23 CMOS Inverter in Short-Circuit Condition Assume the CMOS inverter from above with V IN = 1.25V and V OUT = 1.25V driving a 10 ff caacitor V IN = 1.25V V DD = 1.25V V OUT = 1.25V What haens to the outut signal? The caacitor slowly discharges to try to find an outut voltage that balances the NMOS and PMOS currents for the given value of V IN. I Short-Circuit = 63.8 µa (We used V IN = V DD /2) I Discharge_Load = 13.7 µa (We Used V IN = V DD /2) C OUT = 10fF V I 13.7µ A = = t C 10 ff = 1.37 ( V / ns)