University of Pennsylvania Department of Electrical and System Engineering Circuit-Level Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2015 Midterm 1 Monday, September 28 5 problems with weights indicated. Parts within a problem will not be weighted equally. Calculators allowed. Closed book = No text or notes allowed. Final answers here. Additional workspace in exam book. Note where to find work in exam book if relevant. Sign Code of Academic Integrity statement on front/back of exam book. Name: Answers Grade: Q1 Q2 Q3 Q4 Q5 Total 1
1. (25 points) Identify if the following circuits are CMOS, why or why not, and their functions. [Show your work for partial credit consideration.] (a) CMOS? (circle one) Yes No (if CMOS) Function (Out) (if not CMOS) Why not? Pull up and pull down not compliments. Output undriven for some cases (A=1, B=1, C=1), and short from Vdd to Gnd in some cases(a=0, B=1, C= 0). 2
(b) CMOS? (circle one) Yes No (if CMOS) Function (Out) OUT = A*/D + B + /C (if not CMOS) Why not? 3
(c) CMOS? (circle one) Yes No (if CMOS) Function (Out) (if not CMOS) Why not? Not complimentary. Pullup network always on, and when A=B=C=1, pulldown network is on creating a short from power to ground. 4
2. (25 points) Provide a CMOS, circuit-level implemenation of the following function (try to minimize the number of stages (first) and the transistor count (second), while retaining fully complementary operation). (We are not asking for transistor sizing in this question.) Out = C*D + /A*C + /B Out = C*(D+/A) + /B /Out = /(C*(D+/A))*B /Out = (/C+/(D+/A))*B /Out = (/C + /D*A)*B 5
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3. (25 points) Consider the following circuit: Assume: all transistors are same size. all on transistors have resitance R on. all transistors have total gate capacitance C g. 7
(a) Highest resistance pull up driving output? Case: A=C=D=0, B=E=1 (b) Highest resistance pull down driving output? Case: C=D=0, A=B=E=1 (c) Lowest capacitance of an input? Which: A, B, or E (d) Highest capacitance of an input? Which: C or D Resistance: 3R on Resistance: 3R on Capacitance: 2C g Capacitance: 4C g (e) Worst-case 10-90 rise time for this gate driving into the C input of another of these gates? Case: A=D=0, B=E=1, C=1 0 Rise Time Expression: 2.2 3R on 4C g = 26.4R on C g (f) Worst-case 10-90 fall time for this gate driving into the C input of another of these gates? Case: A=B=1, C=D=0, E=0 1 Fall Time Expression: 2.2 3R on 4C g = 26.4R on C g [Show your work for partial credit consideration.] 8
4. (20 points) Consider the following non-cmos circuit. Ideal: V dd = 600mV, V thn = 300mV, V thp = -300mV. Use the following simplified transistor models: NMOS: PMOS: V GS V DS Mode I DS > V th < V GS V th Resistive 3.33 10 3 (V GS V th ) V DS > V GS V th Saturation 5 10 4 (V GS V th ) < V th Subthreshold 0 V GS V DS Mode I DS < V th > V GS V th Resistive 3.33 10 3 (V GS V th ) V DS < V GS V th Saturation 5 10 4 (V GS V th ) > V th Subthreshold 0 (a) What function does the circuit perform? Buffer 9
(b) Identify noise margins that will provide restoration assuming V dd and V th are exactly as specified (Ideal). V OH 0.6 V IH 0.4 V IL 0.4 V OL 0 NM L 0.4 NM H 0.2 We can first look at the first stage and call the intermediary node, V X, and then write: V X = 0.6 R I ds = 0.6 6000 I ds (1) Up to V thn = 300mV, the transistor is off so the resistor pulls V X all the way to V dd = 0.6V. The transistor then operates in saturation initially since V ds = V X > 300mV. Here: V X = 0.6 6000 5 10 4 (V in 0.3) = 0.6 3(V in 0.3) (2) This can only hold until V ds = V X < V gs V th. That is: V X < V in 0.3. (3) Substituting V X = V in 0.3 into the saturation equation, we get: V in 0.3 = 0.6 3 (V in 0.3) (4) Which we can solve for V in = 0.45. Additionally, for V in = 0.45, V X = 0.15. Here, we can look at the second stage, which is an inverter with an ideal voltage transfer function with the infinite gain at V X = 300mV. We can use our equations to solve for what V in gives V X = 300mV. 0.3 = 0.6 3 (V in 0.3) V in = 0.4 (5) Therefore we can conclude the transfer function of our non-cmos circuit is as shown above with the noise margins also specified above. 10
5. (5 points) For this problem we consider the circuit below. All transistors are sized with W=L=10 and assumed to not be short channel (i.e do not suffer from velocity saturation). They are like the MOSFETS discussed in class with the following behavior: V GS V DS Mode I DS ( ) ( ) > V th < V GS V th Resistive µ n C W OX (VGS V L th ) V DS (V DS) 2 ( ) 2 µ > V GS V th Saturation nc OX W (VGS V 2 L th ) 2 ( ) ( ) V < V th Subthreshold I W GS V th S L e nkt /q 1 e V DS kt /q (1 + λv DS ) (a) What function does this gate perform? Inverter (b) The input is switched from V dd to Gnd and allowed to reach steady-state. Circle the region of operation each transistor is operating in. i. Mn1: Subthreshold Linear Saturation ii. Mn2: Subthreshold Linear Saturation iii. Mp1: Subthreshold Linear Saturation iv. Mp2: Subthreshold Linear Saturation When the input is switched down to ground, the pmos transistors have a V gs > V th, and the nmos transistors have a V gs < V th. Therefore both the nmos transistors are in subthreshold. The pmos transistors initially enter saturation because their V ds = V dd > V gs V th. However, as V Out charges up to V dd to its steady state voltage, V ds falls below V gs V th and both pmos transistors fall into the Linear/Resistive region. 11