University of Pennsylvania Department of Electrical and System Engineering Circuit-Level Modeling, Design, and Optimization for Digital Systems ESE370, Fall 205 Midterm Wednesday, November 4 Point values for each problem are denoted in exam. Point breakdown within problems varies. Calculators allowed. No smartphones. Closed book = No text or notes allowed. Final answers here. Additional workspace in exam book. Note where to find work in exam book if relevant. Sign Code of Academic Integrity statement on front/back of exam book. V dd =V, V thn = V thp = 250mV, µ n = µ p, R p0 = R n0 = R 0, unless otherwise specified in problem. Unless otherwise noted, inputs driven by R 0 drive with self load 2γC 0. model_drive A model for the input driver is: Name: Grade: Q Q2 Q3 Q4 Q5 Total
. (30pts) Estimate Delay and Switching Energy for the following implementations of an 8:3 encoder called an octal-to-binary encoder. The truth table and logic function are given below. You can assume only the inputs included in the truth table are possible. Basic function is: Inputs Outputs E 7 E 6 E 5 E 4 E 3 E 2 E E 0 A 2 A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A 0 = E + E 3 + E 5 + E 7 A = E 2 + E 3 + E 6 + E 7 A 2 = E 4 + E 5 + E 6 + E 7 All transistors W=L=. Give answers in terms of τ and γ; γ = C diff /C gate. Assume all inputs arrive at the same time and are driven by R 0 drive with 2γC 0 self load. The load on each of the outputs is 32C 0. 2
(a) Using inverter on page and the or gate shown (top) in the configuration shown (bottom), report worst-case delay from this R 0 input driver driving the inputs through driving the 32C 0 load on each A i in units of τ and the worst-case dynamic switching energy. Your calculations can assume the inputs to all or gates arrive at the same time. Delay Dynamic Energy (show delay by stages for partial credit consideration) Stage Delay 3
(b) Using the inverter shown on page in the configuration shown below, report worst-case delay from this R 0 input driver driving the inputs through driving the 32C 0 load on each A i in units of τ and the worst-case dynamic switching energy. Delay Dynamic Energy (show delay by stages for partial credit consideration) Stage Delay 4
2. (20 pts) Ratioed logic and layout (a) In an effort to optimized for area, delay and power, design an XOR gate while minimizing the number of transistors (< 0) without using inverted inputs and using only ratioed logic. Y = A B 5
(b) Draw a stick drawing of the layout of your gate from part (a). Assume all transistors are minimum sized. For reference, an example of a layout stick drawing for a CMOS inverter is shown below. An represents a contact or via and the dashed line defines the n-well area. 6
3. (20 pts) Consider a pass transistor multiplexer that uses PMOS pass gates and a ratioed inverter with an NMOS load transistor for buffering and restoration. Device model assuming L =. Remember µ n = µ p, V thn = V thp =250mv. Device V gs I ds NMOS V gs < V thn (5 0 7 ) W e Vgs V thn 40mV V gs > V thn 2 0 4 W (V gs V thn ) ( PMOS V gs > V thp ( 5 0 7 ) W e Vgs Vthp ) 40mV V gs < V thp 2 0 4 W (V gs V thp ) For references, the output of the following circuit with W p = W n = is V dd /2: 7
(a) How must the transistors be sized to perform restoration to allow a cascade of arbitrary length? Transistor W Reason TR IPU TR IPD TR PT TR PT0 TR PU TR PD 2 Given (select other consistent with this) 8
(b) Use the transistor sizes you specified in part (a) and report the worst case delay. Circuit repeated here for convenience: Give answers in terms of τ and γ; γ = C diff /C gate Assume inputs driven by R 0 drive with 2γC 0 self load. Report delay from this R 0 input driver driving the inputs through to the output of this circuit driving a 4C 0 load. Assume all inputs arrive at the same time. Delay (show delay by stages for partial credit consideration) Stage Delay 9
4. (5 pts) Assume: V Tp = V Tn R 0 =resistance of W n = NMOS transistor µ n =300 cm 2 /(V s), µ p =00 cm 2 /(V s) (I.e. R p0 = 3R n0 ) C 0 = gate capacitance of W n = transistor C diff =0 The output is loaded with a C Load = 4C 0 For the following circuit size and label the transistors on the figure below for a worstcase output resistance of R 0 /3 in each stage and calculate the worst-case delay in units of τ. Assume that the inputs are driven by inverters with an output resistance of R 0 /3. Delay 0
5. (5 pts) Short Answer Questions: Answer the questions briefly. Include diagrams and equations as needed. Be clear in your explanation and handwriting. A Describe the source of short circuit power and when it occurs in a CMOS gate. B What impact does decreasing V dd have on delay and the switching power of a gate? C What is a technique you can use to drive a large load capacitance to reduce delay? Explain what the design to implement this techniques looks like.
D Explain why you can t cascade pass transistors into gate inputs of another pass gate as show in the circuits below E A wire s resistance can be modeled as either a lumped RC network or a distributed RC ladder network. Draw an example of each and explain the difference between the two models. 2