MOSFET and CMOS Gate
CMOS Inverter DC Analysis - Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max NMH = V OH min V IH min (7) (gate threshold voltage) V M In VDD Out Vin Vout CL
CMOS Inverter - Layout PMOS V DD In Out Metal1 Polysilicon NMOS GND
CMOS Inverter DC Analysis - Voltage Transfer Curve (VTC) Vout V OHmax V OH min NMOS off PMOS lin 1 NMOS sat PMOS lin slope = 1 V OL min V M V OLmax 0 NMOS sat PMOS sat NMOS lin PMOS sat NMOS lin PMOS off V in V V V IL min ILmax IH min V IHmax
CMOS Inverter DC Analysis - Voltage Transfer Curve (VTC) β n = 1 β p β β n < n > 1 β 1 p β p
CMOS Inverter Voltage Transfer Curve (VTC) Analytical Graphical Simulation I n,p V in = 0 PMOS V in = 4 V in = 1 V in = 3 V in = 2 V in = 4 V in = 3 V in = 5 V in = 5 V in = 4 V in = 3 V in = 2 NMOS V in = 2 V in = 1 V in = 0
CMOS Inverter Noise Margin In node Out Out V OHM V OHm Noise Margin High "1" Noise Margin Low NM L = V ILmax V OL max V OLM "0" V OLm V IHM NMH = V OH min V IH min V IHm Undefined Region V ILM V ILm Gate Output Gate Input
Noise Margin Noise Margin - applicable to both cases same or different technology Driver noise Receiver [, V ] V OH min OHmax [, V ] V IH min IHmax [, ] [, ] V OL min IL min V OLmax V V ILmax Example - VOH (ALS) = 2.7v, and VIH (ACT) = 2.0v, NMH = 2.7-2.0 = 0.7
Transient Analysis Find Rise time - Fall time - Delay time - t r t f Delay time - t PHL t PLH V in V out 50% t t t phl plh 50% delay time - 1 2 d = (t + t PHL PLH t ) tf 90% 10% tr t
Delay Time Formula Delay Time Formula - Exact Exact p L r PLH n L f PHL n L f th th th n L 2 th n th L th 2 th n L 2 th n L v 2C t 2 1 t, v 2C t 2 1 t, v 4C t3 t 5 v v if 0.85 4ln15 1 1 1 t3 t1 1 t3 t1 t3 time) (fall 0.1v 0.1v ) v 2(v ln ) v (v C t1 t3 ) v (v v 2C t1 Solution : v v & v(t1) t2 t t1 if ], 2 v )v v [(v dt dv C v & v(0) t1 t 0 if, ) v (v 2 dt dv C β = = β = = β = = + = β = β = = = β = β = 0.5v V - Vtn 0.1v v
Delay Time -Input Waveform Delay formula also depends on input waveform delay = (input transition dependent term) + (output capicitance dependent term) v 1 th 1 v 4C t, t ( )t L PLH PHL = T + 2 1 + α β v where t T is the transition time of the input waveform Input dependent delay Total delay 60% 40% 1 2 3 4 5 6 t T (C L / β V ) R on C L t
RC model Delay Time - Approximately good enough for manual analysis since 85% of the transition is in the linear region β 2 I n ds = (v v th ) 2 sin ce then Q = I t = C ds L t = C V = I β ds L n V 2C (v L v v th ) 2 V out R on CL Replace each turn on transistor by its equivalent resistance
Power Dissipation Static Power leakage current due to parasitic diodes Dynamic Power 2 dynmic C L V P = f charging/discharging capacitors Crowbar Current Power P crowbar α t T short current between two rails of power supply Standby Current leakage current due to transistors (sub-threshold region, a transistor is not really turn-off, it is in weak inversion)
Shopping for a Technology Signal - Bandwidth and Rise Time Technology - Unity Gain f Short Circuit Current Unity Gain Voltage Unity Gain knee ϖ T ϖ T = (C (signal) < f gs (voltage) = T g m + C In reality wechoose (C gs L ) g m + C I ds v C L (gate technology) 5f (data) < f 12f gd g ) C t d (data) m L 1 (gate) T < f in order to preserve (technology) T (technology) Voltage gain (gate) (pass) the signal for a digital signal f 3db f T (unity gain) for an analog signal and
CMOS Gate - Static CMOS Gate for Boolean Expression RC Model
Oscillator - Inverter Chain V 0 V 1 V 2 V 3 V 4 V 5 V 2 V 4 V 5 V 0 t d V 1 V 3 T = 2 n t d where n must be a prime number
Oscillator - Differential Inverter + in + out + in + out + in + out out + out in out in out in out + in v b The number of stages must be an even number in
V b Oscillator - Current Starved Inverter
CMOS Static Gate At every point in time (except during the switching transients) the gate output is connected to either VDD or VSS via a low resistive path The output of the gate faithfully generates the value of the Boolean function, implemented by the circuit except the transient effects during switching period This is in contrast to the dynamic circuit, which relies on the temporary storage of signal values on the capacitance of the circuit node. In general, the dynamic circuit depends on two operation phases of pre-charge (pre-discharge) and evaluation. Only in the steady state of evaluation phase, the output of a dynamic gate faithfully implements the desired functional value
Static Gate Structure V DD x1 x2 x3 PMOS PMOS Only f x1 x2 x3 NMOS NMOS Only V SS NMOS and PMOS Blocks are Dual Networks
Implementation Procedure Given the function f (x1,x2,x3,.xn) Obtain of the function network (NMOS) by the complement Construct f make a serial connection if there is a conjunctive term (e.g. x^y^z) make a parallel connection if tehre is a disjunctive term e.g. x+y+z) Construct the dual ( d ) of network (PMOS) by f f make a serial connection if there is a conjunctive term (e.g. x^y^z) make a parallel connection if tehre is a disjunctive term e.g. x+y+z) f Cascade and d together according to the static gate f structure ECE733
ECE733 Example - NAND
V Out GND ECE733 Example - NAND Gate V DD In1 In2 In3 In4 In1 In2 In3 In4 In1 In2 In3 In4 Out
ECE733 Example - NOR
ECE733 Example - Complex Gate VDD A B C D A D B C OUT = D + A (B+C)
ECE733 Inputs Complex Gate - Switch Network B Switch Out A Network B B N transistors No static consumption Out
ECE733 Complex Gate - Switch Network C = 5 V C = 5 V A = 5 V A = 5 V B Mn B M2 CL M1 V B does not pull up to 5V, but 5V - V TN
ECE733 Transmission Gate C C A B A B C C C = 5 V A = 5 V B C L C = 0 V
ECE733 R (Ohm) Transmission Gate - Resistance 30000.0 R n 20000.0 R p 10000.0 R eq 0.0 0.0 1.0 2.0 3.0 4.0 5.0 Vout (W/L)p=(W/L)n = 1.8/1.2
A B Transmission Gate - Multiplexer S S VDD S V DD M2 S F M1 S GND A S S B ECE733
ECE733 A Transmission Gate -XOR Gate B M2 B F M1 B B A M3/M4