74AHC2G241; 74AHCT2G241

Similar documents
74AHC2G126; 74AHCT2G126

74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate

Dual buffer/line driver; 3-state

74HC2G125; 74HCT2G125

2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device.

Dual buffer/line driver; 3-state

74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate

74HC2G16; 74HCT2G16. The 74HC2G16; 74HCT2G16 is a high-speed Si-gate CMOS device. The 74HC2G16; 74HCT2G16 provides two buffers.

74HC2G08-Q100; 74HCT2G08-Q100

Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.

2-input EXCLUSIVE-OR gate

74HC3G04; 74HCT3G General description. 2. Features and benefits. 3. Ordering information. 4. Marking. Triple inverter

74HC2G02; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. 4. Marking. Dual 2-input NOR gate

The 74AXP1G04 is a single inverting buffer.

The 74LV08 provides a quad 2-input AND function.

The 74AUP2G34 provides two low-power, low-voltage buffers.

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate

74HC1G86; 74HCT1G86. 2-input EXCLUSIVE-OR gate. The standard output currents are half those of the 74HC/HCT86.

74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02.

74AHC1G125; 74AHCT1G125

74AUP1G04-Q100. The 74AUP1G04-Q100 provides the single inverting buffer.

Low-power triple buffer with open-drain output

74HC4050-Q100. Hex non-inverting HIGH-to-LOW level shifter

Bus buffer/line driver; 3-state

Low-power configurable multiple function gate

74HC368; 74HCT368. Hex buffer/line driver; 3-state; inverting

74LVC1G125-Q100. Bus buffer/line driver; 3-state

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

74AHC1G126; 74AHCT1G126

Octal buffer/line driver; 3-state

Triple inverting Schmitt trigger

74HC366; 74HCT366. Hex buffer/line driver; 3-state; inverting

Low-power configurable multiple function gate

Single supply translating buffer/line driver; 3-state

74LVC General description. 2. Features and benefits. Ordering information. Octal D-type flip-flop with data enable; positive-edge trigger

74HC1G02-Q100; 74HCT1G02-Q100

74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter

Low-power buffer and inverter. The 74AUP2G3404 is a single buffer and single inverter.

Low-power 3-input EXCLUSIVE-OR gate. The 74AUP1G386 provides a single 3-input EXCLUSIVE-OR gate.

74LVC1G18 1-of-2 non-inverting demultiplexer with 3-state deselected output Rev. 3 2 December 2016 Product data sheet 1. General description

2-input single supply translating NAND gate

74HC1G08; 74HCT1G08. 1 General description. 2 Features. 3 Ordering information. 2-input AND gate

Low-power dual Schmitt trigger inverter

74HC541; 74HCT541. Octal buffer/line driver; 3-state

74HC3G14; 74HCT3G14. Triple inverting Schmitt trigger. The 74HC3G14; 74HCT3G14 is a high-speed Si-gate CMOS device.

Octal bus transceiver; 3-state

74HC1G32-Q100; 74HCT1G32-Q100

74HC365; 74HCT365. Hex buffer/line driver; 3-state

7-stage binary ripple counter

74HC2G34; 74HCT2G34. The 74HC2G34; 74HCT2G34 is a high-speed Si-gate CMOS device. The 74HC2G34; 74HCT2G34 provides two buffers.

Dual supply buffer/line driver; 3-state

XC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger

74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function.

Dual buffer/line driver; 3-state

74HC30-Q100; 74HCT30-Q100

74AHC1G00; 74AHCT1G00

Single D-type flip-flop; positive-edge trigger. The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop.

74LVC1G79-Q100. Single D-type flip-flop; positive-edge trigger. The 74LVC1G79_Q100 provides a single positive-edge triggered D-type flip-flop.

74HC1G125; 74HCT1G125

74HC153-Q100; 74HCT153-Q100

Low-power buffer/line driver; 3-state

Hex inverter with open-drain outputs

Low-power buffer with voltage-level translator

4-bit magnitude comparator

The 74LV08 provides a quad 2-input AND function.

Octal buffer/line driver with 5 V tolerant inputs/outputs; 3-state

74LVC125A. 1. General description. 2. Features and benefits. Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

Low-power 2-input NAND gate. The 74AUP1G00 provides the single 2-input NAND function.

74HC253; 74HCT253. Dual 4-input multiplexer; 3-state

74AVC General description. 2 Features and benefits. 1-to-4 fan-out buffer

74HC10; 74HCT General description. 2. Features and benefits. 3. Ordering information. Triple 3-input NAND gate

74HC126; 74HCT126. Quad buffer/line driver; 3-state

74LVC07A-Q100. Hex buffer with open-drain outputs

The 74AVC16374 is designed to have an extremely fast propagation delay and a minimum amount of power consumption.

Low-power 2-input AND gate with open-drain

Single dual-supply translating 2-input OR with strobe

74AVC16374-Q General description. 2. Features and benefits. 16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state

The 74LVC1G02 provides the single 2-input NOR function.

74HC280; 74HCT bit odd/even parity generator/checker

Dual supply configurable multiple function gate

Low-power 3-input AND gate. The 74AUP1G11 provides a low-power, low-voltage single 3-input AND gate.

74LVC General description. 2. Features and benefits. 3. Ordering information. Triple 3-input OR gate. The 74LVC332 is a triple 3-input OR gate.

74HC540; 74HCT540. Octal buffer/line driver; 3-state; inverting

The 74LVC10A provides three 3-input NAND functions.

74HC132-Q100; 74HCT132-Q100

74AHC541; 74AHCT541. Octal buffer/line driver; 3-state. The 74AHC541; 74AHCT541 is a high-speed Si-gate CMOS device.

74ALVC04. 1 General description. 2 Features and benefits. 3 Ordering information. Hex inverter

74HC03-Q100; 74HCT03-Q100

Dual bus buffer/line driver; 3-state

Low-power dual supply translating buffer

Low-power unbuffered inverter. The 74AUP1GU04 provides the single unbuffered inverting gate.

74HC174; 74HCT174. Hex D-type flip-flop with reset; positive-edge trigger

74HC4002; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NOR gate

Low-power dual PCB configurable multiple function gate

74AHC02; 74AHCT02. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

74AHC541-Q100; 74AHCT541-Q100

Low-power inverter with open-drain output

Transcription:

Rev. 3 13 May 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a high-speed Si-gate CMOS device. The is a dual non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. HIGH level at pin 1OE causes output 1Y to assume a high-impedance OFF-state. LOW level at pin 2OE causes output 2Y to assume a high-impedance OFF-state. Schmitt-trigger action at all inputs makes the circuit highly tolerant for slower input rise and fall times. Symmetrical output impedance High noise immunity ESD protection: HBM JESD22-114E: exceeds 2000 V MM JESD22-115-: exceeds 200 V CDM JESD22-C101C: exceeds 1000 V Low power dissipation Balanced propagation delays Multiple package options Specified from 40 C to +85 C and from 40 C to +125 C Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC2G241DP 40 C to +125 C TSSOP8 plastic thin shrink small outline package; 8 leads; SOT505-2 74HCT2G241DP 74HC2G241DC 40 C to+125 C VSSOP8 body width 3 mm; lead length 0.5 mm plastic very thin shrink small outline package; 8 leads; SOT765-1 74HCT2G241DC 74HC2G241GD 74HCT2G241GD 40 C to +125 C XSON8 body width 2.3 mm plastic extremely thin small outline package; no leads; 8 terminals; body 3 2 0.5 mm SOT996-2

4. Marking Table 2. Marking Type number Marking code 74HC2G241DP 241 74HCT2G241DP C241 74HC2G241DC 41 74HCT2G241DC C41 74HC2G241GD 41 74HCT2G241GD C41 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 1OE 2 1 1Y 6 7 2OE 5 2 2Y 3 2 1 5 7 EN1 EN2 1 2 6 3 001aaa409 001aaa408 Fig 1. Logic symbol Fig 2. IEC logic symbol 6. Pinning information 6.1 Pinning 74HC2G241 74HCT2G241 74HC2G241 74HCT2G241 1OE 1 1 2 8 7 V CC 2OE 1OE 1 2Y 1 2 3 8 7 6 V CC 2OE 1Y 2Y GND 3 4 6 5 1Y 2 GND 4 5 2 001aaj392 001aaj391 Transparent top view Fig 3. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) Fig 4. Pin configuration SOT996-2 (XSON8) Product data sheet Rev. 3 13 May 2013 2 of 17

6.2 Pin description Table 3. Pin description Symbol Pin Description 1OE 1 output enable input (active LOW) 1 2 data input 2Y 3 data output GND 4 ground (0 V) 2 5 data input 1Y 6 data output 2OE 7 output enable input (active HIGH) V CC 8 supply voltage 7. Functional description Table 4. Function table Input Output Input Output 1OE 1 1Y 2OE 2 2Y L L L H L L L H H H H H H X Z L X Z H = HIGH voltage level; L = LOW voltage level; X = don t care; Z = high-impedance OFF-state. 8. Limiting values Table 5. Limiting values In accordance with the bsolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage 0.5 +7.0 V V I input voltage 0.5 +7.0 V I IK input clamping current V I < 0.5 V 20 - m I OK output clamping current V O < 0.5 V or V O >V CC +0.5V - 20 m I O output current 0.5 V < V O <V CC +0.5V - 25 m I CC supply current - 75 m I GND ground current 75 - m T stg storage temperature 65 +150 C P tot total power dissipation T amb = 40 C to +125 C [2] - 250 mw The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For TSSOP8 package: above 55 C the value of P tot derates linearly with 2.5 mw/k. For VSSOP8 package: above 110 C the value of P tot derates linearly with 8 mw/k. For XSON8 package: above 45 C the value of P tot derates linearly with 2.4 mw/k. Product data sheet Rev. 3 13 May 2013 3 of 17

9. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74HC2G241 74HCT2G241 Unit Min Typ Max Min Typ Max V CC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V V I input voltage 0-5.5 0-5.5 V V O output voltage 0 - V CC 0 - V CC V T amb ambient temperature 40 +25 +125 40 +25 +125 C t/ V input transition rise V CC = 3.3 V 0.3 V - - 100 - - - ns/v and fall rate V CC = 5.0 V 0.5 V - - 20 - - 20 ns/v 10. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74HC2G241 V IH HIGH-level V CC = 2.0 V 1.5 - - 1.5-1.5 - V input voltage V CC = 3.0 V 2.1 - - 2.1-2.1 - V V CC = 5.5 V 3.85 - - 3.85-3.85 - V V IL LOW-level V CC = 2.0 V - - 0.5-0.5-0.5 V input voltage V CC = 3.0 V - - 0.9-0.9-0.9 V V CC = 5.5 V - - 1.65-1.65-1.65 V V OH HIGH-level output voltage V I = V IH or V IL I O = 50 ; V CC = 2.0 V 1.9 2.0-1.9-1.9 - V I O = 50 ; V CC = 3.0 V 2.9 3.0-2.9-2.9 - V I O = 50 ; V CC = 4.5 V 4.4 4.5-4.4-4.4 - V I O = 4.0 m; V CC = 3.0 V 2.58 - - 2.48-2.40 - V I O = 8.0 m; V CC = 4.5 V 3.94 - - 3.8-3.70 - V V OL LOW-level output voltage V I = V IH or V IL I O = 50 ; V CC = 2.0 V - 0 0.1-0.1-0.1 V I O = 50 ; V CC = 3.0 V - 0 0.1-0.1-0.1 V I O = 50 ; V CC = 4.5 V - 0 0.1-0.1-0.1 V I O = 4.0 m; V CC = 3.0 V - - 0.36-0.44-0.55 V I O = 8.0 m; V CC = 4.5 V - - 0.36-0.44-0.55 V I OZ OFF-state output current V I =V CC or GND; V CC =5.5V - - 0.25-2.5-10 I I input leakage current V I = 5.5 V or GND; V CC =0Vto5.5V I CC supply current V I =V CC or GND; I O = 0 ; V CC = 5.5 V - - 0.1-1.0-2.0 - - 1.0-10 - 40 Product data sheet Rev. 3 13 May 2013 4 of 17

Table 7. Static characteristics continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max C I input capacitance - 1.5 10-10 - 10 pf 74HCT2G241 V IH HIGH-level 2.0 - - 2.0-2.0 - V input voltage V IL LOW-level - - 0.8-0.8-0.8 V input voltage V OH HIGH-level output voltage V I = V IH or V IL ; V CC = 4.5 V I O = 50 4.4 4.5-4.4-4.4 - V I O = 8.0 m 3.94 - - 3.8-3.70 - V V OL LOW-level output voltage V I = V IH or V IL ; V CC = 4.5 V I O = 50-0 0.1-0.1-0.1 V I O = 8.0 m - - 0.36-0.44-0.55 V I OZ OFF-state output current V I =V CC or GND; V CC =5.5V - - 0.25-2.5-10 I I input leakage current V I = 5.5 V or GND; V CC =0Vto5.5V I CC supply current V I =V CC or GND; I O = 0 ; V CC = 5.5 V I CC C I additional supply current input capacitance per input pin; V I =3.4V; other inputs at V CC or GND; I O =0 ; V CC = 5.5 V 11. Dynamic characteristics - - 0.1-1.0-2.0 - - 1.0-10 - 40 - - 1.35-1.5-1.5 m - 1.5 10-10 - 10 pf Table 8. Dynamic characteristics GND = 0 V; for test circuit see Figure 8. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74HC2G241 t pd propagation n to ny; see Figure 5 delay V CC = 3.0 V to 3.6 V [2] C L = 15 pf - 4.7 8.0 1.0 9.5 1.0 11.5 ns C L = 50 pf - 6.6 11.5 1.0 13.0 1.0 14.5 ns C L = 15 pf - 3.4 5.5 1.0 6.5 1.0 7.0 ns C L = 50 pf - 4.7 7.5 1.0 8.5 1.0 9.5 ns Product data sheet Rev. 3 13 May 2013 5 of 17

Table 8. Dynamic characteristics continued GND = 0 V; for test circuit see Figure 8. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max t en enable time 1OE to 1Y; see Figure 6 V CC = 3.0 V to 3.6 V [2] C L = 15 pf - 5.0 8.0 1.0 9.5 1.0 11.5 ns C L = 50 pf - 6.9 11.5 1.0 13.0 1.0 14.5 ns C L = 15 pf - 3.6 5.1 1.0 6.0 1.0 6.5 ns C L = 50 pf - 4.9 7.5 1.0 8.5 1.0 9.5 ns 2OE to 2Y; see Figure 7 V CC = 3.0 V to 3.6 V [2] C L = 15 pf - 4.9 8.0 1.0 9.5 1.0 10.0 ns C L = 50 pf - 7.0 11.5 1.0 13.0 1.0 14.5 ns t dis disable time 1OE to 1Y; see Figure 6 C PD power dissipation capacitance 74HCT2G241 t pd propagation delay C L = 15 pf - 3.6 5.6 1.0 6.3 1.0 7.0 ns C L = 50 pf - 5.4 8.0 1.0 9.0 1.0 9.5 ns V CC = 3.0 V to 3.6 V [2] C L = 15 pf - 6.0 9.7 1.0 11.5 1.0 12.5 ns C L = 50 pf - 8.3 13.2 1.0 15.0 1.0 16.5 ns C L = 15 pf - 4.1 6.8 1.0 8.0 1.0 8.5 ns C L = 50 pf - 5.7 8.8 1.0 10.0 1.0 11.0 ns 2OE to 2Y; see Figure 7 V CC = 3.0 V to 3.6 V [2] C L = 15 pf - 6.3 9.7 1.0 11.5 1.0 12.5 ns C L = 50 pf - 9.0 13.2 1.0 15.0 1.0 16.5 ns C L = 15 pf - 4.3 6.8 1.0 8.0 1.0 8.5 ns C L = 50 pf - 6.1 8.8 1.0 10.0 1.0 11.0 ns per buffer; [4] - 10 - - - - - pf C L =50pF;f i =1 MHz; V I =GNDtoV CC n to ny; see Figure 5 C L = 15 pf - 3.4 5.5 1.0 6.5 1.0 7.0 ns C L = 50 pf - 4.7 7.5 1.0 8.5 1.0 9.5 ns Product data sheet Rev. 3 13 May 2013 6 of 17

Table 8. Dynamic characteristics continued GND = 0 V; for test circuit see Figure 8. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max t en enable time 1OE to 1Y; see Figure 6 t pd is the same as t PLH and t PHL. t en is the same as t PZL and t PZH. t dis is the same as t PLZ and t PHZ. [2] Typical values are measured at V CC = 3.3 V. Typical values are measured at V CC = 5.0 V. [4] C PD is used to determine the dynamic power dissipation P D ( W). P D =C PD V CC 2 f i + (C L V CC 2 f o )where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in Volts. C L = 15 pf - 3.9 5.1 1.0 6.0 1.0 6.5 ns C L = 50 pf - 5.1 7.5 1.0 8.5 1.0 9.5 ns 2OE to 2Y; see Figure 7 t dis disable time 1OE to 1Y; see Figure 6 C PD power dissipation capacitance C L = 15 pf - 3.4 5.6 1.0 6.3 1.0 6.5 ns C L = 50 pf - 4.8 7.5 1.0 9.0 1.0 9.5 ns C L = 15 pf - 4.5 6.8 1.0 8.0 1.0 8.5 ns C L = 50 pf - 6.1 8.8 1.0 10.0 1.0 11.0 ns 2OE to 2Y; see Figure 7 C L = 15 pf - 4.0 6.8 1.0 8.0 1.0 8.5 ns C L = 50 pf - 5.7 8.8 1.0 10.0 1.0 11.0 ns per buffer; [4] - 10 - - - - - pf C L =50pF;f i =1 MHz; V I =GNDtoV CC Product data sheet Rev. 3 13 May 2013 7 of 17

12. Waveforms V I n input GND t PHL t PLH V OH ny output V OL mna230 Fig 5. Measurement points are given in Table 9. Logic levels: V OL and V OH are typical output voltage levels that occur with the output load. The input (n) to output (ny) propagation delays V I 1OE input GND t PLZ t PZL output LOW-to-OFF OFF-to-LOW V CC V OL V OL + 0.3 V t PHZ t PZH output HIGH-to-OFF OFF-to-HIGH V OH GND outputs enabled V OH 0.3 V outputs disabled outputs enabled 001aaa411 Fig 6. Measurement points are given in Table 9. Logic levels: V OL and V OH are typical output voltage levels that occur with the output load. The input (1OE) to output 1Y enable and disable times Product data sheet Rev. 3 13 May 2013 8 of 17

V I 2OE input GND t PLZ t PZL output LOW-to-OFF OFF-to-LOW V CC V OL V OL + 0.3 V t PHZ t PZH output HIGH-to-OFF OFF-to-HIGH V OH GND outputs enabled V OH 0.3 V outputs disabled outputs enabled 001aaa410 Fig 7. Measurement points are given in Table 9. Logic levels: V OL and V OH are typical output voltage levels that occur with the output load. The input (2OE) to output 2Y enable and disable times Table 9. Measurement points Type Input Output 74HC2G241 0.5V CC 0.5V CC 74HCT2G241 1.5 V 0.5V CC Product data sheet Rev. 3 13 May 2013 9 of 17

V I negative pulse 0 V 90 % 10 % t W t f t r t r t f V I positive pulse 0 V 10 % 90 % t W V CC V CC G VI DUT VO RL S1 open RT CL 001aad983 Fig 8. Test data is given in Table 10. Definitions test circuit: R T = Termination resistance should be equal to output impedance Z o of the pulse generator. C L = Load capacitance including jig and probe capacitance. R L = Load resistance. S1 = Test selection switch. Test circuit for measuring switching times Table 10. Test data Type Input Load S1 position V I t r, t f C L R L t PHL, t PLH t PZH, t PHZ t PZL, t PLZ 74HC2G241 V CC 3 ns 15 pf, 50 pf 1 k open GND V CC 74HCT2G241 3 V 3 ns 15 pf, 50 pf 1 k open GND V CC Product data sheet Rev. 3 13 May 2013 10 of 17

13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 D E X c y H E v M Z 8 5 2 1 ( 3 ) pin 1 index L p θ L 1 4 detail X e b p w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT max. 1 mm 1.1 0.15 0.00 2 3 b p c D (1) E (1) e H E L L p v w y Z (1) θ 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8 0 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT505-2 - - - 02-01-16 Fig 9. Package outline SOT505-2 (TSSOP8) Product data sheet Rev. 3 13 May 2013 11 of 17

VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 D E X c y H E v M Z 8 5 Q 2 1 pin 1 index ( 3 ) L p θ 1 4 detail X L e b p w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT max. 1 mm 1 0.15 0.00 2 3 b p c D (1) E (2) e H E L L p Q v w y Z (1) θ 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.5 3.2 3.0 0.4 0.40 0.15 0.21 0.19 0.2 0.13 0.1 0.4 0.1 8 0 OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT765-1 MO-187 02-06-07 Fig 10. Package outline SOT765-1 (VSSOP8) Product data sheet Rev. 3 13 May 2013 12 of 17

XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 3 x 2 x 0.5 mm SOT996-2 D B E 1 detail X terminal 1 index area L 1 e 1 e b 1 4 v w C C B y 1 C C y L 2 L 8 5 X 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit (1) 1 b D E e e 1 L L 1 L 2 v w y y 1 mm max nom min 0.5 0.05 0.00 0.35 0.15 2.1 1.9 3.1 2.9 0.5 0.15 0.6 0.5 1.5 0.1 0.05 0.3 0.05 0.4 0.05 0.1 sot996-2_po Outline version SOT996-2 References IEC JEDEC JEIT European projection Issue date 07-12-21 12-11-20 Fig 11. Package outline SOT996-2 (XSON8) Product data sheet Rev. 3 13 May 2013 13 of 17

14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes v.3 20130513 Product data sheet - v.2 Modifications: For type number 74HC2G241GD and 74HCT2G241GD XSON8U has changed to XSON8. v.2 20090113 Product data sheet - v.1 Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. dded type number 74HC2G241GD and 74HCT2G241GD (XSON8U package). v.1 20040310 Product data - - Product data sheet Rev. 3 13 May 2013 14 of 17

15. Legal information 15.1 Data sheet status Document status [2] Product status Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 15.2 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of a Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Product data sheet Rev. 3 13 May 2013 15 of 17

Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia s specifications such use shall be solely at customer s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia s standard warranty and Nexperia s product specifications. Translations non-english (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Product data sheet Rev. 3 13 May 2013 16 of 17

17. Contents 1 General description...................... 1 2 Features and benefits.................... 1 3 Ordering information..................... 1 4 Marking................................ 2 5 Functional diagram...................... 2 6 Pinning information...................... 2 6.1 Pinning............................... 2 6.2 Pin description......................... 3 7 Functional description................... 3 8 Limiting values.......................... 3 9 Recommended operating conditions........ 4 10 Static characteristics..................... 4 11 Dynamic characteristics.................. 5 12 Waveforms............................. 8 13 Package outline........................ 11 14 Revision history........................ 14 15 Legal information....................... 15 15.1 Data sheet status...................... 15 15.2 Definitions............................ 15 15.3 Disclaimers........................... 15 15.4 Trademarks........................... 16 16 Contact information..................... 16 17 Contents.............................. 17 For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 13 May 2013