The University of Toledo EECS:1100 R2 Digital Logic Design Dr. Anthony D. Johnson Cover Sheet for Lab Experiment #3 Student Names Course Section Anthony Phillips 003 Alexander Beck 003 Report turned in late Grade /2 Final Grade /2
1. Introduction to Lab Report 1.1 Objectives 1. Becoming familiar with two standard forms of logic functions: Sum of Products (SOP), and Product of Sums (POS) 2. Becoming familiar with two canonical forms of logic functions: Sum of Minterms, and Product of Maxterms 3. Applying the algebraic manipulation method to transform standard to canonical forms 4. Learning a procedure for deriving the truth table of a logic function which is known in algebraic form 5. Learning how to derive the minterm list (decimal sum of minterms) form of a logic function whose truth table is known 6. Learning how to derive the maxterm list (decimal product of maxterms) form of a logic function whose truth table is known 7. Exercising two-level implementation of logic functions 8. Becoming familiar with degenerate two-level logic circuits: AND-AND 9. Developing skills in analyzing and testing the behavior of combinational logic circuits.
2. Report on Prelab Work 2.1 SOP Form of Logic Functions 2.1.1 For this lab we will be considering the following function in minimal SOP form: F = f(a, B, C, D) = B'C + AD' We are first asked to algebraically derive the canonical minterm expression. The work is as follows: First we expand the term B'C B'C = B'C (A + A') (D + D') = (B'CA + B'CA') (D + D') = AB'CD + AB'CD' + A'B'CD + A'B'CD' Next we expand the term AD' AD' = AD' (B + B') (C + C') = (AD'B + AD'B') (C + C') = ABCD' + ABC'D' + AB'CD' + AB'C'D' We then substitute for B'C and AD' in F=B'C+AD' F = AB'CD + AB'CD' + A'B'CD + A'B'CD' + ABCD' + ABC'D' + AB'CD' + AB'C'D Lastly, we remove the duplicate terms AB'CD' (x + x = x) and arrive at the canonical minterm expression F = AB'CD + AB'CD' + A'B'CD + A'B'CD' + ABCD' + ABC'D' + AB'C'D'
2.1.2 Using the canonical minterm expression, we can derive the truth table T2.1.2-1.. F = AB'CD + AB'CD' + A'B'CD + A'B'CD' + ABCD' + ABC'D' + AB'C'D' Note that the 1-minterms in the table are color-coded with their corresponding term in the canonical minterm expression. Table T2.1-1 Truth table for the function F=B'C+AD' including min / max terms and inverse. A B C D m n M n F F' 0 0 0 0 A'B'C'D'=m 0 A+B+C+D=M 0 0 0 A'B'C'D=m 1 A+B+C+D'=M 1 0 0 A'B'CD'=m 2 A+B+C'+D=M 2 0 1 A'B'CD=m 3 A+B+C'+D'=M 3 0 0 A'BC'D'=m 4 A+B'+C+D=M 4 A'BC'D=m 5 A+B'+C+D'=M 5 A'BCD'=m 6 A+B'+C'+D=M 6 1 1 A'BCD=m 7 A+B'+C'+D'=M 7 0 0 AB'C'D'=m 8 A'+B+C+D=M 8 AB'C'D=m 9 A'+B+C+D'=M 9 1 0 AB'CD'=m 10 A'+B+C'+D=M 10 1 1 AB'CD=m 11 A'+B+C'+D'=M 11 1 0 ABC'D'=m 12 A'+B'+C+D=M 12 1 1 ABC'D=m 13 A'+B'+C+D'=M 13 1 1 ABCD'=m 14 A'+B'+C'+D=M 14 1 1 1 1 ABCD=m 15 A'+B'+C'+D'=M 15
2.1.3 We are asked now to represent the function in minterm list form, or decimal Sum of Minterms form. According to our canonical minterm expression: F = AB'CD + AB'CD' + A'B'CD + A'B'CD' + ABCD' + ABC'D' + AB'C'D' Now, using table T2.1-1, we substitute the decimal values for each minterm: A B C D m n 0 0 A'B'CD'=m 2 0 1 A'B'CD=m 3 0 0 AB'C'D'=m 8 1 0 AB'CD'=m 10 1 1 AB'CD=m 11 1 0 ABC'D'=m 12 1 1 ABCD'=m 14 F = AB'CD + AB'CD' + A'B'CD + A'B'CD' + ABCD' + ABC'D' + AB'C'D' = m 11 + m 10 + m 3 + m 2 + m 14 + m 12 + m 8 = 11 + 10 + 3 + 2 +14 + 12 + 8 Finally, we put this in summation form: F = 11 + 10 + 3 + 2 +14 + 12 + 8 = Σ (11, 10, 3, 2, 14, 12, 8) Equation E2.1-3 F = Σ (2, 3, 8, 10, 11, 12, 14) Its inverse is then represented by summation of the 0-minterms (or the 1-minterms of F'): Equation E2.1-3 F' = Σ (0, 1, 4, 5, 6, 7, 9, 13, 15)
2.1.4 / 2.1.5 a) b) Figure 2.1-1
2.2 Degenerate Two-Level AND-AND Logic Circuit 2.2.1 / 2.2.4 a) b) Figure 2.2-1
2.2 The function given by the circuit in figure 2.2-1a is: F = f(a, B, C, D) = { [ (B'C)' ][ (AD')' ] }' This function generates the truth table shown in T2.2-1. Table T2.2-1 Truth table for the function F={ [ (B'C)' ][ (AD')' ] }' including minterms, maxterms and inverse. A B C D m n M n F F' 0 0 0 0 A'B'C'D'=m 0 A+B+C+D=M 0 0 0 A'B'C'D=m 1 A+B+C+D'=M 1 0 0 A'B'CD'=m 2 A+B+C'+D=M 2 0 1 A'B'CD=m 3 A+B+C'+D'=M 3 0 0 A'BC'D'=m 4 A+B'+C+D=M 4 A'BC'D=m 5 A+B'+C+D'=M 5 A'BCD'=m 6 A+B'+C'+D=M 6 1 1 A'BCD=m 7 A+B'+C'+D'=M 7 0 0 AB'C'D'=m 8 A'+B+C+D=M 8 AB'C'D=m 9 A'+B+C+D'=M 9 1 0 AB'CD'=m 10 A'+B+C'+D=M 10 1 1 AB'CD=m 11 A'+B+C'+D'=M 11 1 0 ABC'D'=m 12 A'+B'+C+D=M 12 1 1 ABC'D=m 13 A'+B'+C+D'=M 13 1 1 ABCD'=m 14 A'+B'+C'+D=M 14 1 1 1 1 ABCD=m 15 A'+B'+C'+D'=M 15
2.2.3 If we extract the 1-minterms of F from table T2.2-1 we can prepare the canonical minterm expression: A B C D m n F 0 0 A'B'CD'=m 2 1 0 1 A'B'CD=m 3 1 0 0 AB'C'D'=m 8 1 1 0 AB'CD'=m 10 1 1 1 AB'CD=m 11 1 1 0 ABC'D'=m 12 1 1 1 ABCD'=m 14 1 Equation E2.2-1 F = A'B'CD' + A'B'CD + AB'C'D' + AB'CD' + AB'CD + ABC'D' + ABCD' It should be noted that this expression is identical to the canonical minterm expression derived in 2.1.1 from the function F = B'C + AD'. Extracting the 0-maxterms of F from table 2.2-1, we can also gather the maxterm list: A B C D M n F 0 0 0 0 A+B+C+D=M 0 0 0 0 A+B+C+D'=M 1 0 0 0 A+B'+C+D=M 4 0 A+B'+C+D'=M 5 0 A+B'+C'+D=M 6 0 1 1 A+B'+C'+D'=M 7 0
A'+B+C+D'=M 9 0 1 1 A'+B'+C+D'=M 13 0 1 1 1 1 A'+B'+C'+D'=M 15 0 F = M 0 + M 1 + M 4 + M 5 + M 6 + M 7 + M 9 + M 13 + M 15 = 0 + 1 +4 + 5 + 6 + 7 + 9 + 13 + 15 Equation E2.2-2 F = Π (0, 1, 4, 5, 6, 7, 9, 13, 15) It should be noted that this maxterm list is identical to the 0-minterm list we derived in 2.1.3. 2.2.5 As we have observed, the truth tables and minterm expressions are identical for both F 0 = B'C + AD' and F 1 ={ [ (B'C)' ][ (AD')' ] }'. This means they represent the same function. Here we further prove that these functions are equivalent by applying DeMorgan's Theorem: F 0 = B'C + AD' = B'(C')' + (A')'D' = (B + C')' + (A' + D)' = [ (B + C')(A' + D) ]' = { [ (B')' + C' ][ A' + (D')' ] }' = { [ (B'C)' ][ (AD')' ] }' = F 1
2.3 POS Form of Logic Functions 2.3.1 We are now asked to algebraically derive the POS standard form of the equation given in 2.1.1. We can do this by applying DeMorgan's Law: F = B'C + AD' = B'(C')' + (A')'D' = (B + C')' + (A' + D)' Equation E2.3-1 F = [ (B + C')(A' + D) ]' 2.3.2 We will now determine the product of maxterms canonical form: First we expand the term B+C': B + C' = B + C' + AA' + DD' = (A + B + C' +D)(A' + B + C' + D)(A + B + C' + D')(A' + B + C + D') Next we expand the term A'+D: A' + D = A' + D + BB' + CC' = (A' + B + C + D)(A' + B' + C + D)(A' + B + C' + D)(A' + B' + C' + D) We then substitute for B+C' and A'+D: F = [ (B + C')(A' + D) ]' = [ (A + B + C' +D)(A' + B + C' + D)(A + B + C' + D')(A' + B + C + D')(A' + B + C + D)(A' + B' + C + D)(A' + B + C' + D)(A' + B' + C' + D) ]' We eliminate duplicate terms: F = [ (A + B + C' +D)(A' + B + C' + D)(A + B + C' + D')(A' + B + C + D')(A' + B + C + D)(A' + B' + C + D)(A' + B' + C' + D) ]'
Finally, we should see that our expression is a complement; this means that the maxterms in our expression are the 1-maxterms. We now convert this to an expression of 0-maxterms: Equation E2.3-2 F = (A' + B' + C +D')(A + B' + C + D')(A' + B' + C + D)(A + B' + C' + D)(A + B' + C' + D')(A + B + C' + D')(A + B + C + D') 2.3.3 If we compare the maxterms we derived in Equation E2.3-2 to the maxterms contained in the truth table T2.2.1, we can see that our canonical maxterm expression is verified: F = (A' + B' + C +D')(A + B' + C + D')(A' + B' + C + D)(A + B' + C' + D)(A + B' + C' + D')(A + B + C' + D')(A + B + C + D') A B C D M n F F' 0 0 0 0 A+B+C+D=M 0 0 0 A+B+C+D'=M 1 0 0 A+B'+C+D=M 4 A+B'+C+D'=M 5 A+B'+C'+D=M 6 1 1 A+B'+C'+D'=M 7 A'+B+C+D'=M 9 1 1 A'+B'+C+D'=M 13 1 1 1 1 A'+B'+C'+D'=M 15
2.3.4 / 2.3.6 a) b) Figure 2.3-1
3. Experimental Results and Discussion 3.1 AND-OR Implementation of f(d,c,b,a) Figure 3.1-1 Output produced by AND-OR implementation.
3.2 Degenerate Two-Level AND-AND Logic Circuit Figure 3.2-1 Output produced by AND-AND implementation.
3.3 OR-AND Implementation of f(d,c,b,a) Figure 3.3-1 Output produced by OR-AND implementation.
4. Answers to Questions 4.1 (from 4.2.6) What is the maximum number of inputs (fan-in) of an AND gate which can be implemented using the IC 7408? An IC 7408 contains four 2-Input AND gates therefore the maximum number of inputs possible for IC 7408 is 8. 4.2 (from 4.2.6) How many different implementations of the maximum fan-in AND gate can be constructed using the IC 7408? The number of implementations is 2 n where n is the number of inputs. In our case n=8, so: 2 8 = 256
Helpful Sources: Semantics: https://en.wikipedia.org/wiki/canonical_normal_form Deriving minterm / maxterm expressions: http://www.cs.ucr.edu/~ehwang/courses/cs120a/minterms.pdf http://webpages.uncc.edu/~sjkuyath/elet3132/fundamentals/t4-1%20sop%20expressions.p df Function Checker: http://electronics-course.com/boolean-algebra http://www.32x8.com/var4.html Circuit Modeling: https://circuits.io/ http://www.digikey.com/schemeit/project/