74AHC373; 74AHCT373. Octal D-type transparant latch; 3-state

Similar documents
74AHC259; 74AHCT259. The 74AHC259; 74AHCT259 has four modes of operation:

Octal D-type transparent latch; 3-state

2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device.

74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function.

74AHC02; 74AHCT02. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function.

Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.

2-input EXCLUSIVE-OR gate

74HC1G86; 74HCT1G86. 2-input EXCLUSIVE-OR gate. The standard output currents are half those of the 74HC/HCT86.

74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02.

74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter

74AHC86; 74AHCT86. Quad 2-input EXCLUSIVE-OR gate. The 74AHC86; 74AHCT86 provides a 2-input exclusive-or function.

74HC General description. 2. Features. Octal D-type flip-flop; positive-edge trigger; 3-state; inverting

The 74LV08 provides a quad 2-input AND function.

74HC2G34; 74HCT2G34. The 74HC2G34; 74HCT2G34 is a high-speed Si-gate CMOS device. The 74HC2G34; 74HCT2G34 provides two buffers.

Octal bus transceiver; 3-state

The 74LVC1G02 provides the single 2-input NOR function.

The 74LV32 provides a quad 2-input OR function.

74AHC125; 74AHCT125. Quad buffer/line driver; 3-state

74AHC541; 74AHCT541. Octal buffer/line driver; 3-state. The 74AHC541; 74AHCT541 is a high-speed Si-gate CMOS device.

74AHC2G126; 74AHCT2G126

74AHC244; 74AHCT244. Octal buffer/line driver; 3-state. The 74AHC244; 74AHCT244 is a high-speed Si-gate CMOS device.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

74AHC1G00; 74AHCT1G00

Dual 3-channel analog multiplexer/demultiplexer with supplementary switches

74AHC14; 74AHCT14. Hex inverting Schmitt trigger

XC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger

HEF4028B. 1. General description. 2. Features. 3. Applications. 4. Ordering information. BCD to decimal decoder

The 74LVC1G11 provides a single 3-input AND gate.

74HC02; 74HCT02. The 74HC02; 74HCT02 provides a quad 2-input NOR function.

74AHC573; 74AHCT573. Octal D-type transparant latch; 3-state

74LVC1G General description. 2. Features. Single D-type flip-flop with set and reset; positive edge trigger

74HC594; 74HCT bit shift register with output register

74LV General description. 2. Features. 8-bit addressable latch

74HC1G125; 74HCT1G125

74AHC1G14; 74AHCT1G14

74HC373; 74HCT General description. 2. Features. Octal D-type transparent latch; 3-state

74LV General description. 2. Features. 3. Applications. 8-bit serial-in/serial-out or parallel-out shift register; 3-state

Temperature range Name Description Version 74LVC74AD 40 C to +125 C SO14 plastic small outline package; 14 leads;

74HC General description. 2. Features. 3-to-8 line decoder, demultiplexer with address latches; inverting

74HC3G14; 74HCT3G14. Triple inverting Schmitt trigger. The 74HC3G14; 74HCT3G14 is a high-speed Si-gate CMOS device.

Dual 2-to-4 line decoder/demultiplexer

BCD to 7-segment latch/decoder/driver

74LVT125; 74LVTH General description. 2. Features. 3. Quick reference data. 3.3 V quad buffer; 3-state

5-stage Johnson decade counter

The 74LV08 provides a quad 2-input AND function.

74AHC1G66; 74AHCT1G66

8-bit binary counter with output register; 3-state

74HC238; 74HCT to-8 line decoder/demultiplexer

The 74AVC16374 is designed to have an extremely fast propagation delay and a minimum amount of power consumption.

Octal buffer/line driver; 3-state

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate

Dual JK flip-flop with reset; negative-edge trigger

74ALVCH V/3.3 V 16-bit D-type transparent latch; 3-state

Bus buffer/line driver; 3-state

74ALVCH V/3.3 V 16-bit D-type transparent latch; 3-state

74LVC1G125-Q100. Bus buffer/line driver; 3-state

74HC373-Q100; 74HCT373-Q100

74HC2G16; 74HCT2G16. The 74HC2G16; 74HCT2G16 is a high-speed Si-gate CMOS device. The 74HC2G16; 74HCT2G16 provides two buffers.

3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state

74HC4094-Q100; 74HCT4094-Q100

74HC368; 74HCT368. Hex buffer/line driver; 3-state; inverting

74HC573-Q100; 74HCT573-Q100

Dual buffer/line driver; 3-state

74HC541; 74HCT541. Octal buffer/line driver; 3-state

The 74HC21 provide the 4-input AND function.

74LVC1G79-Q100. Single D-type flip-flop; positive-edge trigger. The 74LVC1G79_Q100 provides a single positive-edge triggered D-type flip-flop.

8-bit binary counter with output register; 3-state

74LVC1G18 1-of-2 non-inverting demultiplexer with 3-state deselected output Rev. 3 2 December 2016 Product data sheet 1. General description

74HC154; 74HCT to-16 line decoder/demultiplexer

74HC151-Q100; 74HCT151-Q100

The 74AUP2G34 provides two low-power, low-voltage buffers.

74HC2G125; 74HCT2G125

74ALVCH V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

74HC366; 74HCT366. Hex buffer/line driver; 3-state; inverting

74AVC16374-Q General description. 2. Features and benefits. 16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state

74HC365; 74HCT365. Hex buffer/line driver; 3-state

74HC574; 74HCT574. Octal D-type flip-flop; positive edge-trigger; 3-state. The 74HC574; 74HCT574 is functionally identical to:

74AVC General description. 2 Features and benefits. 1-to-4 fan-out buffer

Low-power buffer and inverter. The 74AUP2G3404 is a single buffer and single inverter.

Single D-type flip-flop; positive-edge trigger. The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop.

Quad bus transceiver; 3-state. The output enable inputs (OEA and OEB) can be used to isolate the buses.

74HC30-Q100; 74HCT30-Q100

74AUP1G04-Q100. The 74AUP1G04-Q100 provides the single inverting buffer.

74AHC273-Q100; 74AHCT273-Q100

74LVU General description. 2. Features. 3. Applications. Hex inverter

74HC107-Q100; 74HCT107-Q100

74HC253; 74HCT253. Dual 4-input multiplexer; 3-state

74LVC General description. 2. Features and benefits. Ordering information. Octal D-type flip-flop with data enable; positive-edge trigger

Dual buffer/line driver; 3-state

The 74AXP1G04 is a single inverting buffer.

74HC244; 74HCT244. Octal buffer/line driver; 3-state

Hex inverter with open-drain outputs

Octal buffer/line driver with 5 V tolerant inputs/outputs; 3-state

Low-power triple buffer with open-drain output

74ALVC bit dual supply translating transciever; 3-state. This device can be used as two 8-bit transceivers or one 16-bit transceiver.

Dual buffer/line driver; 3-state

Octal bus transceiver; 3-state

74LV03. 1 General description. 2 Features and benefits. 3 Ordering information. Quad 2-input NAND gate

74HC597-Q100; 74HCT597-Q100

74HC126; 74HCT126. Quad buffer/line driver; 3-state

Transcription:

Rev. 03 20 May 2008 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEEC standard No. 7-A. The consists of eight -type transparent latches featuring separate -type inputs for each latch and 3-state true outputs for bus oriented applications. A latch enable input () and an output enable input (OE) are common to all latches. When pin is HIGH, data at the n inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding n input changes. When pin is LOW, the latches store the information that is present at the n inputs, after a set-up time preceding the HIGH-to-LOW transition of. When pin OE is LOW, the contents of the 8 latches are available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. The is functionally identical to the 74AHC573; 74AHCT573, but has a different pin arrangement. Balanced propagation delays All inputs have a Schmitt-trigger action Common 3-state output enable input Inputs accepts voltages higher than V CC Functionally identical to the 74AHC573; 74AHCT573 Input levels: For 74AHC373: CMOS input level For 74AHCT373: TTL input level ES protection: HBM EIA/JES22-A114E exceeds 2000 V MM EIA/JES22-A115-A exceeds 200 V CM EIA/JES22-C101C exceeds 1000 V Multiple package options Specified from 40 C to +85 C and from 40 C to +125 C

3. Ordering information Table 1. Type number Ordering information Package 4. Functional diagram Temperature range Name escription Version 74AHC373 74AHC373 40 C to +125 C SO20 plastic small outline package; 20 leads; body width 7.5 mm 74AHC373PW 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm 74AHCT373 74AHCT373 40 C to +125 C SO20 plastic small outline package; 20 leads; body width 7.5 mm 74AHCT373PW 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT163-1 SOT360-1 SOT163-1 SOT360-1 3 4 7 8 13 14 17 18 0 1 2 3 4 5 6 7 1 TO 8 3-STATE OUTPUTS 0 1 2 3 4 5 6 7 2 5 6 9 12 15 16 19 11 1 OE 001aae050 Fig 1. Functional diagram Product data sheet Rev. 03 20 May 2008 2 of 17

OE 1 11 EN C1 3 4 7 8 13 14 17 18 0 1 2 3 4 5 6 7 11 0 1 2 3 4 5 6 7 OE 2 5 6 9 12 15 16 19 0 1 2 3 4 5 6 7 3 4 7 8 13 14 17 18 1 2 5 6 9 12 15 16 19 0 1 2 3 4 5 6 7 1 001aae048 001aae049 Fig 2. Logic symbol Fig 3. IEC logic symbol 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 OE 0 1 2 3 4 5 6 7 001aae052 Fig 4. Logic diagram 001aae051 Fig 5. Logic diagram (one latch) Product data sheet Rev. 03 20 May 2008 3 of 17

5. Pinning information 5.1 Pinning 74AHC373 74AHCT373 OE 1 20 V CC 0 2 19 7 0 3 18 7 1 4 17 6 1 5 16 6 2 6 15 5 2 7 14 5 3 8 13 4 3 9 12 4 GN 10 11 001aai132 Fig 6. Pin configuration SO20 and TSSOP20 5.2 Pin description Table 2. Pin description Symbol Pin escription OE 1 3-state output enable input (active LOW) 0 2 3-state latch output 0 3 data input 1 4 data input 1 5 3-state latch output 2 6 3-state latch output 2 7 data input 3 8 data input 3 9 3-state latch output GN 10 ground (0 V) 11 latch enable input (active HIGH) 4 12 3-state latch output 4 13 data input 5 14 data input 5 15 3-state latch output 6 16 3-state latch output 6 17 data input Product data sheet Rev. 03 20 May 2008 4 of 17

Table 2. Pin description continued Symbol Pin escription 7 18 data input 7 19 3-state latch output V CC 20 supply voltage 6. Functional description Table 3. Function table [1] Operating mode Control Input Internal Output OE n latch 0 to 7 Enable and read register (transparent mode) L H L L L H H H Latch and read register L L l L L h H H Latch register and disable outputs H X X X Z X X Z [1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW transition; X = don t care; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GN (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage 0.5 +7.0 V V I input voltage 0.5 +7.0 V I IK input clamping current V I < 0.5 V [1] 20 - ma I OK output clamping current V O < 0.5 V or V O >V CC + 0.5 V [1] 20 +20 ma I O output current V O = 0.5 V to (V CC + 0.5 V) 25 +25 ma I CC supply current - +75 ma I GN ground current 75 - ma T stg storage temperature 65 +150 C P tot total power dissipation T amb = 40 C to +125 C [2] - 500 mw [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO20 packages: above 70 C the value of P tot derates linearly at 8 mw/k. For TSSOP20 packages: above 60 C the value of P tot derates linearly at 5.5 mw/k. Product data sheet Rev. 03 20 May 2008 5 of 17

8. Recommended operating conditions Table 5. Operating conditions Symbol Parameter Conditions Min Typ Max Unit 74AHC373 V CC supply voltage 2.0 5.0 5.5 V V I input voltage 0-5.5 V V O output voltage 0 - V CC V T amb ambient temperature 40 +25 +125 C t/ V input transition rise and fall rate V CC = 3.0 V to 3.6 V - - 100 ns/v V CC = 4.5 V to 5.5 V - - 20 ns/v 74AHCT373 V CC supply voltage 4.5 5.0 5.5 V V I input voltage 0-5.5 V V O output voltage 0 - V CC V T amb ambient temperature 40 +25 +125 C t/ V input transition rise and fall rate V CC = 4.5 V to 5.5 V - - 20 ns/v 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GN (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74AHC373 V IH HIGH-level V CC = 2.0 V 1.5 - - 1.5-1.5 - V input voltage V CC = 3.0 V 2.1 - - 2.1-2.1 - V V CC = 5.5 V 3.85 - - 3.85-3.85 - V V IL LOW-level V CC = 2.0 V - - 0.5-0.5-0.5 V input voltage V CC = 3.0 V - - 0.9-0.9-0.9 V V CC = 5.5 V - - 1.65-1.65-1.65 V V OH HIGH-level output voltage V I = V IH or V IL I O = 50 µa; V CC = 2.0 V 1.9 2.0-1.9-1.9 - V I O = 50 µa; V CC = 3.0 V 2.9 3.0-2.9-2.9 - V I O = 50 µa; V CC = 4.5 V 4.4 4.5-4.4-4.4 - V I O = 4.0 ma; V CC = 3.0 V 2.58 - - 2.48-2.40 - V I O = 8.0 ma; V CC = 4.5 V 3.94 - - 3.80-3.70 - V V OL LOW-level output voltage V I = V IH or V IL I O = 50 µa; V CC = 2.0 V - 0 0.1-0.1-0.1 V I O = 50 µa; V CC = 3.0 V - 0 0.1-0.1-0.1 V I O = 50 µa; V CC = 4.5 V - 0 0.1-0.1-0.1 V I O = 4.0 ma; V CC = 3.0 V - - 0.36-0.44-0.55 V I O = 8.0 ma; V CC = 4.5 V - - 0.36-0.44-0.55 V Product data sheet Rev. 03 20 May 2008 6 of 17

Table 6. Static characteristics continued At recommended operating conditions; voltages are referenced to GN (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit I OZ I I OFF-state output current input leakage current V I =V IH or V IL ; V O =V CC or GN; V CC = 5.5 V V I =V CC or GN; V CC = 0 V to 5.5 V Min Typ Max Min Max Min Max - - ±0.2 - ±2.5 - ±10.0 µa 5 - - 0.1-1.0-2.0 µa I CC supply current V I =V CC or GN; I O =0A; - - 4.0-40 - 80 µa V CC = 5.5 V C I input V I =V CC or GN - 3 10-10 - 10 pf capacitance C O output capacitance - 4 - - - - 10 pf 74AHCT373 V IH HIGH-level V CC = 4.5 V to 5.5 V 2.0 - - 2.0-2.0 - V input voltage V IL LOW-level V CC = 4.5 V to 5.5 V - - 0.8-0.8-0.8 V input voltage V OH HIGH-level output voltage V I = V IH or V IL ; V CC = 4.5 V I O = 50 µa 4.4 4.5-4.4-4.4 - V I O = 8.0 ma 3.94 - - 3.80-3.70 - V V OL LOW-level output voltage V I = V IH or V IL ; V CC = 4.5 V I O = 50 µa - 0 0.1-0.1-0.1 V I O = 8.0 ma - - 0.36-0.44-0.55 V I OZ I I OFF-state output current input leakage current V I =V IH or V IL ; V O =V CC or GN per input pin; other inputs at V CC or GN; I O = 0 A; V CC = 5.5 V V I = 5.5 V or GN; V CC = 0 V to 5.5 V I CC supply current V I =V CC or GN; I O = 0 A; V CC = 5.5 V I CC C I C O additional supply current input capacitance output capacitance - - ±0.2 5 - ±2.5 - ±10.0 µa - - 0.1-1.0-2.0 µa - - 4.0-40 - 80 µa per input pin; V I =V CC 2.1 V; other pins at V CC or GN; I O =0A; V CC = 4.5 V to 5.5 V - - 1.35-1.5-1.5 µa V I =V CC or GN - 3 10-10 - 10 pf - 4 - - - - 10 pf Product data sheet Rev. 03 20 May 2008 7 of 17

10. ynamic characteristics Table 7. ynamic characteristics Voltages are referenced to GN (ground = 0 V); for test circuit see Figure 11. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ [1] Max Min Max Min Max 74AHC373 t pd propagation n to n; see Figure 7 [2] delay V CC = 3.0 V to 3.6 V C L = 15 pf - 6.0 11.4 1.0 13.5 1.0 14.5 ns C L = 50 pf - 7.8 14.9 1.0 17.0 1.0 19.0 ns V CC = 4.5 V to 5.5 V C L = 15 pf - 4.0 7.2 1.0 8.5 1.0 9.0 ns C L = 50 pf - 5.3 9.2 1.0 10.5 1.0 11.5 ns to n; see Figure 8 [2] V CC = 3.0 V to 3.6 V C L = 15 pf - 6.3 11.0 1.0 13.0 1.0 14.0 ns C L = 50 pf - 8.3 14.5 1.0 16.5 1.0 18.5 ns V CC = 4.5 V to 5.5 V C L = 15 pf - 4.3 7.2 1.0 8.5 1.0 9.0 ns C L = 50 pf - 5.6 9.7 1.0 11.1 1.0 12.5 ns t en enable time OE to n; see Figure 9 [3] V CC = 3.0 V to 3.6 V C L = 15 pf - 5.6 11.4 1.0 13.5 1.0 14.5 ns C L = 50 pf - 7.5 14.9 1.0 17.0 1.0 19.0 ns V CC = 4.5 V to 5.5 V C L = 15 pf - 3.8 8.1 1.0 9.5 1.0 10.5 ns C L = 50 pf - 5.2 10.1 1.0 11.5 1.0 13.0 ns t dis disable time OE to n; see Figure 9 [4] V CC = 3.0 V to 3.6 V C L = 15 pf - 5.6 10.0 1.0 12.0 1.0 13.0 ns C L = 50 pf - 9.2 13.3 1.0 15.0 1.0 17.0 ns V CC = 4.5 V to 5.5 V C L = 15 pf - 4.3 7.2 1.0 8.5 1.0 9.5 ns C L = 50 pf - 6.4 9.2 1.0 10.5 1.0 11.5 ns t W pulse width HIGH or LOW; see Figure 8 V CC = 3.0 V to 3.6 V 5.0 - - 5.0-5.0 - ns V CC = 4.5 V to 5.5 V 5.0 - - 5.0-5.0 - ns t su set-up time n to ; see Figure 10 V CC = 3.0 V to 3.6 V 4.0 - - 4.0-4.0 - ns V CC = 4.5 V to 5.5 V 4.0 - - 4.0-4.0 - ns Product data sheet Rev. 03 20 May 2008 8 of 17

Table 7. ynamic characteristics continued Voltages are referenced to GN (ground = 0 V); for test circuit see Figure 11. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ [1] Max Min Max Min Max t h hold time n to ; see Figure 10 V CC = 3.0 V to 3.6 V 1.0 - - 1.0-1.0 - ns V CC = 4.5 V to 5.5 V 1.0 - - 1.0-1.0 - ns C P power dissipation capacitance f i = 1 MHz; V I = GN to V CC [5] - 10 - - - - - pf 74AHCT373; V CC = 4.5 V to 5.5 V t pd propagation n to n; see Figure 7 [4] delay C L = 15 pf - 4.0 8.5 1.0 9.5 1.0 11.0 ns C L = 50 pf - 5.2 9.5 1.0 10.5 1.0 12.0 ns to n; see Figure 8 C L =15pF [4] - 4.3 12.3 1.0 13.5 1.0 15.5 ns C L = 50 pf - 5.5 13.3 1.0 14.5 1.0 17.0 ns t en enable time OE to n; see Figure 9 C L = 15 pf - 4.0 10.9 1.0 12.5 1.0 14.0 ns C L =50pF [4] - 5.2 11.9 1.0 13.5 1.0 15.0 ns t dis disable time OE to n; see Figure 9 C L = 15 pf - 4.4 10.2 1.0 11.0 1.0 13.0 ns C L = 50 pf - 6.5 11.2 1.0 12.0 1.0 14.0 ns t W pulse width HIGH; see Figure 8 [4] 6.5 - - 6.5-6.5 - ns t su set-up time n to ; see Figure 10 3.5 - - 3.5-3.5 - ns t h hold time n to ; see Figure 10 1.5 - - 1.5-1.5 - ns C P power dissipation capacitance [1] Typical values are measured at nominal supply voltage (V CC = 3.3 V and V CC = 5.0 V). [2] t pd is the same as t PHL and t PLH. [3] t en is the same as t PZH and t PZL. [4] t dis is the same as t PHZ and t PLZ. [5] C P is used to determine the dynamic power dissipation (P in µw). P =C P V CC 2 f i N+Σ(C L V CC 2 f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; f i = 1 MHz; V I = GN to V CC N = number of inputs switching; Σ(C L V 2 CC f o ) = sum of the outputs. [5] - 12 - - - - - pf Product data sheet Rev. 03 20 May 2008 9 of 17

11. Waveforms V I n input GN t PHL t PLH V OH n output V OL mna811 Fig 7. Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. ata input to output propagation delays 1/f max V I input GN t W t PHL t PLH V OH n output V OL mna812 Fig 8. Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. Latch enable pulse width and input to output propagation delays Product data sheet Rev. 03 20 May 2008 10 of 17

V I OE input GN t PLZ t PZL n output LOW-to-OFF OFF-to-LOW V CC V OL V X t PHZ t PZH V OH n output HIGH-to-OFF OFF-to-HIGH GN outputs enabled V Y outputs disabled outputs enabled mna813 Fig 9. Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. Enable and disable times V I n input GN t h t h t su t su V I input GN mna814 Fig 10. Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. The shaded areas indicate when the input is permitted to change for predicable output performance. ata set-up and hold times Table 8. Measurement points Type Input Output V X V Y 74AHC373 0.5 V CC 0.5 V CC V OL + 0.3 V V OH 0.3 V 74AHCT373 1.5 V 0.5 V CC V OL + 0.3 V V OH 0.3 V Product data sheet Rev. 03 20 May 2008 11 of 17

V I negative pulse 0 V 90 % 10 % t W t f t r t r t f V I positive pulse 0 V 10 % 90 % t W V CC V CC G VI UT VO RL S1 open RT CL 001aad983 Fig 11. Test data is given in Table 9. efinitions test circuit: R T = termination resistance should be equal to output impedance Z o of the pulse generator. C L = load capacitance including jig and probe capacitance. R L = load resistance. S1 = test selection switch. Test circuitry for switching times Table 9. Test data Type Input Load S1 position V I t r, t f C L R L t PHL, t PLH t PZH, t PHZ t PZL, t PLZ 74AHC373 V CC 3.0 ns 15 pf, 50 pf 1 kω open GN V CC 74AHCT373 3.0 V 3.0 ns 15 pf, 50 pf 1 kω open GN V CC Product data sheet Rev. 03 20 May 2008 12 of 17

12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 E A X c y H E v M A Z 20 11 A 2 A 1 (A ) 3 A pin 1 index L p L θ 1 e b p 10 w M detail X 0 5 10 mm scale IMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A 1 A 2 A 3 b p c (1) E (1) e H (1) E L L p v w y Z 0.3 0.1 0.012 0.004 2.45 2.25 0.096 0.089 0.25 0.01 0.49 0.36 0.019 0.014 0.32 0.23 0.013 0.009 13.0 12.6 0.51 0.49 7.6 7.4 0.30 0.29 1.27 10.65 10.00 0.419 0.394 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 0.05 1.4 0.055 1.1 0.4 0.043 0.016 1.1 1.0 0.043 0.039 0.25 0.25 0.1 0.01 0.01 0.004 θ 0.9 0.4 o 8 o 0.035 0 0.016 OUTLINE VERSION REFERENCES IEC JEEC JEITA EUROPEAN PROJECTION ISSUE ATE SOT163-1 075E04 MS-013 99-12-27 03-02-19 Fig 12. Package outline SOT163-1 (SO20) Product data sheet Rev. 03 20 May 2008 13 of 17

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E A X c y H E v M A Z 20 11 pin 1 index A 2 A 1 (A ) 3 A θ 1 10 w M e b p detail X L p L 0 2.5 5 mm scale IMENSIONS (mm are the original dimensions) A UNIT A 1 A 2 A 3 b p c (1) E (2) e H (1) E L L p v w y Z max. mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEEC JEITA SOT360-1 MO-153 EUROPEAN PROJECTION ISSUE ATE 99-12-27 03-02-19 Fig 13. Package outline SOT360-1 (TSSOP20) Product data sheet Rev. 03 20 May 2008 14 of 17

13. Abbreviations Table 10. Acronym CM CMOS ES HBM MM TTL Abbreviations escription Charged evice Model Complementary Metal-Oxide Semiconductor ElectroStatic ischarge Human Body Model Machine Model Transistor-Transistor Logic 14. Revision history Table 11. Revision history ocument I Release date ata sheet status Change notice Supersedes 20080520 Product data sheet - 74AHC_AHCT373_2 Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Table 6: conditions for the input leakage current have been changed. 74AHC_AHCT373_2 19991123 Product specification - 74AHC_AHCT373_1 74AHC_AHCT373_1 19981211 Product specification - - Product data sheet Rev. 03 20 May 2008 15 of 17

15. Legal information 15.1 ata sheet status ocument status [1][2] Product status [3] efinition Objective [short] data sheet evelopment This document contains data from the objective specification for product development. Preliminary [short] data sheet ualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section efinitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 15.2 efinitions raft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 isclaimers General Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use Nexperia products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia accepts no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by Nexperia. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Product data sheet Rev. 03 20 May 2008 16 of 17

17. Contents 1 General description...................... 1 2 Features............................... 1 3 Ordering information..................... 2 4 Functional diagram...................... 2 5 Pinning information...................... 4 5.1 Pinning............................... 4 5.2 Pin description......................... 4 6 Functional description................... 5 7 Limiting values.......................... 5 8 Recommended operating conditions........ 6 9 Static characteristics..................... 6 10 ynamic characteristics.................. 8 11 Waveforms............................ 10 12 Package outline........................ 13 13 Abbreviations.......................... 15 14 Revision history........................ 15 15 Legal information....................... 16 15.1 ata sheet status...................... 16 15.2 efinitions............................ 16 15.3 isclaimers........................... 16 15.4 Trademarks........................... 16 16 Contact information..................... 16 17 Contents.............................. 17 For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com ate of release: 20 May 2008