Lecture 6: Logical Effort

Lecture 6: Logical Effort

Outline Logical Effort Delay in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages Example Summary

Introduction Chip designers face a bewildering array of choices What is the best circuit topology for a function? How many stages of logic give least delay? How wide should the transistors be???? Logical effort is a method to make these decisions Uses a simple model of delay Allows back-of-the-envelope calculations Helps make rapid comparisons between alternatives Emphasizes remarkable symmetries 3

Example Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded automotive processor. Help Ben design the A[3:0] A[3:0] decoder for a register file. 3 bits Decoder specifications: 6 6 word register file Each word is 3 bits wide Each bit presents load of 3 unit-sized transistors True and complementary address inputs A[3:0] Each input may drive 0 unit-sized transistors Ben needs to decide: How many stages to use? How large should each gate be? How fast can decoder operate? :6 Decoder Register File 6 words

Delay in a Logic Gate Express delays in process-independent unit d = Delay has two components: d = f + p τ = 3RC f: effort delay = gh (a.k.a. stage effort) Again has two components g: logical effort Measures relative ability of gate to deliver current g for inverter h: electrical effort = C out / C in Ratio of output to input capacitance Sometimes called fanout p: parasitic delay Represents delay of gate driving no load Set by internal parasitic capacitance d abs τ 3 ps in 65 nm process 60 ps in 0.6 μm process 5

Delay Plots d = f + p = gh + p What about NOR? Normalized Delay: d 6 5 3 -input NAND Inverter g = /3 p = d = (/3)h + g = p = d = h + Effort Delay: f 0 Parasitic Delay: p 0 3 5 Electrical Effort: h = C out / C in 6

Computing Logical Effort DEF: Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current. Measure from delay vs. fanout plots Or estimate by counting transistor widths A Y A B Y A B Y C in = 3 g = 3/3 C in = g = /3 C in = 5 g = 5/3 7

Catalog of Gates Logical effort of common gates Gate type Number of inputs 3 n Inverter NAND /3 5/3 6/3 (n+)/3 NOR 5/3 7/3 9/3 (n+)/3 Tristate / mux XOR, XNOR, 6,, 6 8, 6, 6, 8 8

Catalog of Gates Parasitic delay of common gates In multiples of p inv ( ) Gate type Number of inputs 3 n Inverter NAND 3 n NOR 3 n Tristate / mux 6 8 n XOR, XNOR 6 8 9

Example: Ring Oscillator Estimate the frequency of an N-stage ring oscillator Logical Effort: g = Electrical Effort: h = Parasitic Delay: p = Stage Delay: d = Frequency: f osc = /(*N*d) = /N 3 stage ring oscillator in 0.6 μm process has frequency of ~ 00 MHz 0

Example: FO Inverter Estimate the delay of a fanout-of- (FO) inverter d Logical Effort: g = Electrical Effort: h = Parasitic Delay: p = Stage Delay: d = 5 The FO delay is about 300 ps in 0.6 μm process 5 ps in a 65 nm process

Multistage Logic Networks Logical effort generalizes to multistage networks Path Logical Effort Path Electrical Effort Path Effort G = g i C H = C out-path in-path F = fi = gh i i 0 g = h = x/0 x g = 5/3 h = y/x y g 3 = /3 h 3 = z/y z g = h = 0/z 0

Multistage Logic Networks Logical effort generalizes to multistage networks Path Logical Effort Path Electrical Effort Path Effort Can we write F = GH? G = g i Cout H = path C in path F = fi = gh i i 3

Paths that Branch No! Consider paths that branch: G = H = 90 / 5 = 8 5 5 90 GH = 8 h = (5 +5) / 5 = 6 5 90 h = 90 / 5 = 6 F = g g h h = 36 = GH

Branching Effort Introduce branching effort Accounts for branching between stages in path b = C on path B= b i C C on path off path Now we compute the path effort F = GBH + Note: h i = BH 5

Multistage Delays Path Effort Delay D F = f i Path Parasitic Delay Path Delay P= p i = i = F + D d D P 6

Designing Fast Circuits = i = F + D d D P Delay is smallest when each stage bears same effort fˆ = gh = F i i N Thus minimum delay of N stage path is N D= NF + P This is a key result of logical effort Find fastest possible delay Doesn t require calculating gate sizes 7

Gate Sizes How wide should the gates be for least delay? fˆ = gh= g C = in i C C out in gc i fˆ out i Working backward, apply capacitance transformation to find input capacitance of each gate given load it drives. Check work by verifying input cap spec is met. 8

Example: 3-stage path Select gate sizes x and y for least delay from A to B x x y 5 A 8 x y B 5 9

Example: 3-stage path x A y x 5 8 x y B 5 Logical Effort G = (/3)*(5/3)*(5/3) = 00/7 Electrical Effort H = 5/8 Branching Effort B = 3 * = 6 Path Effort F = GBH = 5 Best Stage Effort ˆ 3 F 5 Parasitic Delay P = + 3 + = 7 f = = Delay D = 3*5 + 7 = =. FO 0

Example: 3-stage path Work backward for sizes y = 5 * (5/3) / 5 = 5 x = (5*) * (5/3) / 5 = 0 x A P: 8 N: x P: x N: 6 y P: y N: 3 5 B 5

Best Number of Stages How many stages should a path use? Minimizing number of stages is not always fastest Example: drive 6-bit datapath with unit inverter Initial Driver D = NF /N + P = N(6) /N + N 8.8 6 8 3 Datapath Load 6 6 6 6 N: f: D: 6 65 8 8 3 5 Fastest.8 5.3

Derivation Consider adding inverters to end of path How many give least delay? = n N + i + i= D NF p N n p D N N N N ( ) Define best stage effort inv = F ln F + F + p = 0 inv ρ = F N Logic Block: n Stages Path Effort F N - n Extra Inverters p + ρ lnρ = 0 inv ( ) 3

Best Stage Effort p + ρ lnρ = 0 inv ( ) has no closed-form solution Neglecting parasitics (p inv = 0), we find ρ =.78 (e) For p inv =, solve numerically for ρ = 3.59

Sensitivity Analysis How sensitive is delay to using exactly the best number of stages?.6 D(N) /D(N).5..6..5.0 (ρ=6) (ρ =.) 0.0 0.5 0.7.0..0. < ρ < 6 gives delay within 5% of optimal We can be sloppy! I like ρ = N / N 5

Example, Revisited Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded automotive processor. Help Ben design the A[3:0] A[3:0] decoder for a register file. 3 bits Decoder specifications: 6 6 word register file Each word is 3 bits wide Each bit presents load of 3 unit-sized transistors True and complementary address inputs A[3:0] Each input may drive 0 unit-sized transistors Ben needs to decide: How many stages to use? How large should each gate be? How fast can decoder operate? :6 Decoder Register File 6 words 6

Number of Stages Decoder effort is mainly electrical and branching Electrical Effort: H = (3*3) / 0 = 9.6 Branching Effort: B = 8 If we neglect logical effort (assume G = ) Path Effort: F = GBH = 76.8 Number of Stages: N = log F = 3. Try a 3-stage design 7

Gate Sizes & Delay Logical Effort: G = * 6/3 * = Path Effort: F = GBH = 5 Stage Effort: Path Delay: Gate sizes: z = 96*/5.36 = 8 y = 8*/5.36 = 6.7 A[3] A[3] A[] A[] A[] A[] A[0] A[0] 0 0 0 0 0 0 0 0 ˆ /3 = F = 5.36 f D = 3 fˆ + + + =. y z word[0] 96 units of wordline capacitance y z word[5] 8

Comparison Compare many alternatives with a spreadsheet D = N(76.8 G) /N + P Design NOR N G 3 P D 3 NAND-INV 5 9.8 NAND-NOR 0/9 30. INV-NAND-INV NAND-INV-INV-INV 3 6 7.. NAND-NOR-INV-INV 0/9 6 0.5 NAND-INV-NAND-INV 6/9 6 9.7 INV-NAND-INV-NAND-INV 5 6/9 7 0. NAND-INV-NAND-INV-INV-INV 6 6/9 8.6 9

Review of Definitions Term number of stages logical effort electrical effort branching effort effort effort delay parasitic delay delay Stage g h = b = f f p = C C C out in on-path gh + C C on-path d = f + p off-path Path N G = g i H = C C out-path in-path B = b i F = GBH D F = f i P = p i D = d = D + P i F 30

Method of Logical Effort ) Compute path effort ) Estimate best number of stages 3) Sketch path with N stages ) Estimate least delay 5) Determine best stage effort F = GBH N = log F N D= NF + P fˆ = F N 6) Find gate sizes C in i = gic fˆ out i 3

Limits of Logical Effort Chicken and egg problem Need path to compute G But don t know number of stages without G Simplistic delay model Neglects input rise time effects Interconnect Iteration required in designs with wire Maximum speed only Not minimum area/power for constrained delay 3

Summary Logical effort is useful for thinking of delay in circuits Numeric logical effort characterizes gates NANDs are faster than NORs in CMOS Paths are fastest when effort delays are ~ Path delay is weakly sensitive to stages, sizes But using fewer stages doesn t mean faster paths Delay of path is about log F FO inverter delays Inverters and NAND best for driving large caps Provides language for discussing fast circuits But requires practice to master 33