Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 12 The CMOS Inverter: static behavior guntzel@inf.ufsc.br
Design Metrics Cost Complexity and area Integrity and robustness Static (steadystate) behavior Performance Dynamic (transient) response Energy efficiency Energy and power consumption Slide 12.2
Schematics vs. Layout N Well The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again. V DD PMOS 2λ Contacts Polysilicon In Out Metal 1 Source: Rabaey; Chandrakasan; Nikolic, 2003 NMOS GND Slide 12.3 3
Schematics vs. Layout Slide 12.4
Static Characteristics The CMOS Inverter V DD V DD V DD R p V in C L R n V in = V DD V in = 0 V in NMOS PMOS 0 OFF ON V DD V DD ON OFF 0 Slide 12.5
Static Characteristics The CMOS Inverter V DD V DD V DD R p V in C L R n V in = V DD V in = 0 V in NMOS PMOS 0 OFF ON V DD V DD ON OFF 0 Slide 12.6
Static Characteristics The CMOS Inverter V DD V DD V DD R p V in C L R n V in = V DD V in = 0 V in NMOS PMOS 0 OFF ON V DD V DD ON OFF 0 Slide 12.7
Static Characteristics The CMOS Inverter V DD High noise margins: voltage swing is equal to the supply voltage; V in C L Ratioless logic: logic levels are not dependent upon the relative device sizes; Low output impedance: in steady state there always exists a path with finite resistance between the output and either V DD or ground; The input resistance ; Static power 0: no direct path exists between supply and ground rails under steadystate operating conditions* * this is first order approx. and is far from reality in more advanced technologies. Modified from Rabaey; Chandrakasan; Nikolic, 2003 Slide 12.8
Static Characteristics: VTC NMOS TVC PMOS TVC x 10 4 6 VGS= 2.5 V 0 x 10 4 I D (A) 5 4 3 2 1 Resistive Saturation VGS= 2.0 V V DS = V GS V T VGS= 1.5 V VGS= 1.0 V 0 0 0.5 1 1.5 2 2.5 V DS (V) I D (A) 0.2 0.4 0.6 0.8 1 2.5 2 1.5 1 0.5 0 V DS (V) Assume all variables negative! Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 12.9
Static Characteristics: VTC V DD V GSp V DSp I DSp = I DSn V GSn = V in ; V GSp = V in V DD V DSn = ; V DSp = V DD V in I Dp V GSn I Dn V DSn C L Slide 12.10
Static Characteristics: VTC V DD V GSp V DSp I DSp = I DSn V GSn = V in ; V GSp = V in V DD V DSn = ; V DSp = V DD V in I Dp V GSn I Dn V DSn C L Translating PMOS ID curves to the space defined by V in, and I dn to create the PMOS load line I Dn I Dp = I Dp V in = V DD V GSp = V DD V DSp Slide 12.11
Static Characteristics: VTC I Dn V DD V GSp V DSp PMOS Load line I Dp = I Dn V in = V DD V GSp V in I Dp = V DD V DSp I Dn C L V GSn V DSn Assuming V DD = 2.5V Modified from: Rabaey; Chandrakasan; Nikolic, 2003 Slide 12.12
Static Characteristics: VTC Slide 12.13
Static Characteristics: Shortcurrent Slide 12.14
Static Characteristics: Switching Threshold V DD V DD Curve for an inverter with k p /k n > 1 V in V GSp V DSp I Dp PMOS and NMOS are saturated because V GS =V DS V M I Dn V in = V GSn V DSn V in V DD V Tp V DD Adapted from Weste & Harris, 2005 Slide 12.15
Static Characteristics: Switching Threshold V DD V in V GSp V DSp I Dp I Dn Equating the currents through NMOS and PMOS Assuming that V DD is high enough such that both devices are velocity saturated (V DSAT < V M VT) V GSn V DSn V M V in For V DD >> V T and V DD >> V DSAT : V M = rv DD 1 r Slide 12.16
Static Characteristics: Switching Threshold V M = rv DD 1 r r = k p V DSATp k n V DSATn = v satp W p v satn W n Conclusion: V M is defined by r i.e., the relative driving strength of the PMOS and NMOS transistors! It is desirable that V M is located around the middle of the voltage swing (V DD /2), for what r should be approx. =1: (W /L) p = (W /L)n k' n V DSATn k' p V DSATp Slide 12.17
Static Characteristics: Switching Threshold To set V M is to a given desired value: (W /L) p (W /L) n = k' n V DSATn (V M V Tn V DSATn /2) k' p V DSATp (V DD V M V Tp V DSATp /2) Slide 12.18
Static Characteristics: Switching Threshold For longchannel devices or Lowsupply voltages, velocity saturation does not occurs (V M V T < V DSAT ) V M = V Tn r(v DD V Tp ) 1 r with r = k p k n Slide 12.19
Static Characteristics: Switching Threshold Example (W /L) p Calculate the (W /L) ratio for V M =V DD /2 for a minimumsized inverter in the n 0.25 µm technology used in the book? For such devices, W/L= 1.5 (W /L) p (W /L) n = (W /L) p (W /L) n = k' n V DSATn (V M V Tn V DSATn /2) k' p V DSATp (V DD V M V Tn V DSATn /2) Minimumsize NMOS (W d =0.375 and L d =0.25 µm) γ V T0 (V) (V 0.5 ) V DSAT (V) k (A/V 2 ) λ (V 1 ) NMOS 0.43 0.4 0.63 115 x 10 6 0.06 PMOS 0.4 0.4 1 30 x 10 6 0.1 115 10 6 0.63 6 30 10 1.0 (1.25 0.43 0.63/2) (2.5 1.25 ( 0.4) ( 1) /2) = 3.5 Slide 12.20
Static Characteristics: Switching Threshold Simulation results of V T x W p /W n for a minimumsized inverter in 0.25 µm technology V (V) M 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 If V M = V DD /2 (i.e., r=1) N M is maximized and VTC characteristics are symmetrical (N ML N MH ) V M is relatively insensitive to changes in W p /W n W p /W n V M 1 0.9 W p /W n V M 0.8 10 0 10 1 W /W p n Slide 12.21
Static Characteristics: Noise Margins V DD V GSp V DSp V DD Curve for an inverter with k p /k n > 1 Unity gain point (i.e., where d /dv in = g = 1) V in I Dp V M I Dn V GSn V DSn V in = V in Adapted from Weste & Harris, 2005 V IL V IH V DD V Tp V DD Slide 12.22
Static Characteristics: Noise Margins V OH Observe that V OH = V DD and V OL = Gnd 3 similar (rightangled) triangles V IH V IL = (V OH V OL ) = V DD g g V IH = V M V M g V IL = V M V DD V M g V in = V M g is the gain at point V M (to be determined) NM H = V DD V IH NM L = V IL Ideally, we would like that g V IH = V M V IL = V M V OL V in NM H = V DD V M NM L = V M V IL V IH That is, the noise margins span the complete voltage swing! Slide 12.23
Static Characteristics: Noise Margins Calculating the gain at point V M Current (valid around V M ): k n V DSATn V in V Tn V DSATn 2 (1 λ n ) k p V DSATp V in V DD V Tp V DSATp (1 λ p ) = 0 2 Differentiating, solving for d /dv in, ignoring some second order effects and making V in = : g = 1 k n V DSATn k p V DSATp I D (V M ) λ n λ p 1 r (V M V Tn V DSATn /2)(λ n λ p ) Slide 12.24
Static Characteristics: Noise Margins Example (cont d) Assume an inverter in 0.25 µm technology with W p /W n = 3.4 and NMOS with minimum size (W/L= 1.5). Calculate the noise margins NM L and NM H. As first step, we must compute I D (V M =1.25V): I D (V M ) = k n V DSATn V in V Tn V DSATn 2 (1 λ n ) with k n = k' n W n L n I D (V M ) =1.5 115 10 6 0.63 (1.25 0.43 0.63/2) (1 0.06 1.25) = 59 10 6 A Minimumsize NMOS (W d =0.375 and L d =0.25 µm) γ V T0 (V) (V 0.5 ) V DSAT (V) k (A/V 2 ) λ (V 1 ) NMOS 0.43 0.4 0.63 115 x 10 6 0.06 PMOS 0.4 0.4 1 30 x 10 6 0.1 Slide 12.25
Static Characteristics: Noise Margins Example (cont d) Assume an inverter in 0.25 µm technology with W p /W n = 3.4 and NMOS with minimum size (W/L= 1.5). Calculate the noise margins NM L and NM H. And then, the gain at V M (=1.25V): g = 1 I D (V M ) k n V DSATn k p V DSATp λ n λ p 1 1.5 115 10 6 0.631.5 3.4 30 10 6 1.0 g = 59 10 6 0.06 1 = 27.5 Minimumsize NMOS (W d =0.375 and L d =0.25 µm) γ V T0 (V) (V 0.5 ) V DSAT (V) k (A/V 2 ) λ (V 1 ) NMOS 0.43 0.4 0.63 115 x 10 6 0.06 PMOS 0.4 0.4 1 30 x 10 6 0.1 Slide 12.26
Static Characteristics: Noise Margins Example (cont d) Assume an inverter in 0.25 µm technology with W p /W n = 3.4 and NMOS with minimum size (W/L= 1.5). Calculate the noise margins NM L and NM H. Finally, the values of V IL, V IH, NM L and NM H V IH = V M V M g 1.25 =1.25 =1.25 0.04545 =1.3V 27.5 V IL = V M V DD V M g =1.25 2.5 1.25 27.5 =1.25 0.04545 =1.2V NM H = V DD V IH = 2.5 1.3 =1.2V NM L = V IL =1.2V Slide 12.27
Static Characteristics: Simulation Results Inverter in 0.25 µm technology with W p /W n = 3.4, minimum sized NMOS (W/L= 1.5). VTC Gain Max gain = 17 (instead of 27.5) V IL =1.03V (predicted=1.2v), V IH =1.45V (1.3V), NM L =1.03V (1.2V) NM H =1.05V (1.2V) Overestimation due to: Piecewise linear approximation of VTC (mainly) Equation of gain produces overestimated values Slide 12.28
Impact of Process Variations 2.5 V out (V) 2 1.5 1 Good NMOS Bad PMOS Nominal Good PMOS Bad NMOS Inverter simulations: typical, case and two corner cases (fast/slow versions). 0.5 0 0 0.5 1 1.5 2 2.5 V in (V) Slide 12.29
Static Characteristics: Gain as Function of V DD Gain=1 For reliable operation: V DDmin > 2 4kT/q (=100mV @room temp.) While V DD scales down at similar rates to the device, V T almost does not scale Slide 12.30
The References CMOS Inverter 1. RABAEY, J; CHANDRAKASAN, A.; NIKOLIC, B. Digital Integrated Circuits: a design perspective. 2 nd Edition. Prentice Hall, 2003. ISBN: 0130909963. 2. WESTE, Neil; HARRIS, David. CMOS VLSI Design: a circuits and systems perspective. AddisonWesley, 4 th Edition, 2010. ISBN 9780321547743. Slide 12.31