Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 14 The CMOS Inverter: dynamic behavior (sizing, inverter chain, power and energy) guntzel@inf.ufsc.br
To Minimize Propagation Delay of a Gate Reduce Keep the drain diffusion areas as small as possible (to reduce selfloading capacitance) Place fanout gates as close as possible (to reduce routing capacitance) Increase the W/L ratio of the transistors Most powerful and effective design action Caution: it increases diffusion capacitance (and thus, ) It also increases gate capacitances (thus increasing the fanout factor of the driving gate) Increase Above certain levels yields only minimal improvements Increases power consumption and dissipation Slide 14.2
NMOS/PMOS Ratio (V) 1 1.5 2 2.5 NMOS (kω) 35 19 15 13 PMOS (kω 115 55 38 31 For symmetrical response: β = 31 kω /13kΩ 2.4 For minimizing tp = (tp HL + tp LH )/2: C β opt = r 1+ w C dn1 + c gn2 β=1.9 β=2.4 r = R eqp /R eqn for identically sized PMOS and NMOS Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 14.3
Sizing Inverters for Performance = C int + C ext intrinsic load (= C gd1 + C gd2 + C db1 + C db2 ) extrinsic load (= C w + C g ) t p = 0.69R eq (C int + C ext ) = 0.69R eq C int (1+ C ext /C int ) = t p0 (1+ C ext /C int ) where t p0 = 0.69R eq C int is called the intrinsic or unloaded delay (i.e., when C ext =0) Now assume a sizing factor S such that: C int = SC iref R eq = C ref /S then t p = 0.69(R ref /S)(SC iref )(1+ C ext /(SC iref )) t p = 0.69R ref C iref 1+ C ext SC iref = t p0 1+ C ext SC iref t p0 is independent of the sizing of the gate S infinitely large yields the maximum performance, eliminating the impact of C ext Slide 14.4
Sizing Inverters for Performance (for fixed load) majority of improv. Self-loading effect: Intrinsic capacitances dominate Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 14.5
Sizing a Chain of Inverters A chain of inverters is a good first case of real environment In 1 2 N Out C g1 Vdd C int = γc g in out t p = t p0 1+ C ext γc = t p0 (1+ f /γ) g Gnd f = C ext C g is the effective fanout Slide 14.6
Sizing a Chain of Inverters Target: minimize the delay through the inverter chain! In 1 2 N Out C g1 Minimally-sized For the j-th inverter (and ignoring the wiring capacitance): t p,j = t p0 1+ C g,j+1 γc = t p0 (1+ f j /γ) g,j The total delay of the chain can be expressed by: t p = N = t p0 1+ C g,j+1 γc g,j N t p,j j=1 j=1 with C g,n+1 = Slide 14.7
Sizing a Chain of Inverters In 1 2 N Out C g1 Minimally-sized t p = N = t p0 1+ C g,j+1 γc g,j N t p,j j=1 j=1 with C g,n+1 = For the minimum delay, a set of constraints is found by N-1 partial derivatives of the form t p / C g,j = 0 C g,j+1 /C g,j = C g,j /C g,j 1 with (j=2, N) Slide 14.8
Sizing a Chain of Inverters In 1 2 N Out C g1 Minimally-sized The optimum size of each inverter is the geometric mean of its neighbors sizes: C g,j = C g,j 1 C g,j+1 Each stage (inverter) has the same effective fanout (Cout/Cin) Each stage has the same delay Slide 14.9
Sizing a Chain of Inverters In 1 2 N Out C g1 Minimally-sized When each stage is sized by f and has same effective fanout f: f N = F = /C g,1 and the effective fanout of each stage is: f = N F Finally, the minimum delay through the chain is t p = Nt p0 (1+ N F /γ) Slide 14.10
Sizing a Chain of Inverters In 1 2 N Out C g1 Minimally-sized Each inverter is sized up by the same factor f w.r.t. the preceding gate f = N /C g,1 = N F and the minimum delay through the chain is t p = Nt p0 (1+ N F /γ) Slide 14.11
Sizing a Chain of Inverters Example In Out C 1 1 f f 2 = 8 C 1 /C 1 has to be evenly distributed across N = 3 stages: Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 14.12
Optimum Number of Stages For a given load, and given input capacitance C in find optimal sizing f t p = Nt p0 ( 1+ F 1/ N /γ) = t p0 ln F γ f ln f + γ ln f For γ = 0, f = e=2.71828, N = ln(f) Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 14.13
Optimum Effective Fanout f Optimum f for given process defined by γ f opt = 3.6 for γ=1 f opt Source: Rabaey; Chandrakasan; Nikolic, 2003 γ Slide 14.14
Buffer Design 1 64 N f t p 1 64 65 1 8 64 2 8 18 1 4 16 64 3 4 15 1 2.8 8 22.6 64 4 2.8 15.3 Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 14.15
Impact of Rise Time (Slew) on Delay (measure at 10%-90%) Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 14.16
Power Dissipation In CMOS is due to: The CMOS Inverter Dynamic Power Consumption Charging and discharging capacitors Short Circuit Currents Short circuit path between between supply rails during switching Leakage Leaking diodes and transistors Slide 14.17
Dynamic Power Dissipation Vdd Vin Vout Energy/transition = * V 2 dd Power = Energy/transition * f = * V dd 2 * f Not a function of transistor sizes! Need to reduce, V dd, and f to reduce power. Slide 14.18
Dynamic Dissipation M2 M2 in out in out M1 M1 Simplified model out M2 out M1 Slide 14.19
Energy Taken from the Supply M2 out dv E VDD = i VDD (t) dt = C out L dt = 2 dv out = dt 0 0 0 Slide 14.20
Energy Stored in the Capacitor M2 out dv E C = i VDD (t)v out dt = C out L v out dt = v out dv out = C 2 L dt 2 0 0 Only half of the energy supplied by the power source is stored on The other half has been dissipated by the PMOS 0 Slide 14.21
Energy Stored in the Capacitor out M1 dv E C = i VDD (t)v out dt = C out L v out dt = v out dv out = C 2 L dt 2 0 0 0 During the discharge phase, the charge is removed from the capacitor, and its energy is dissipated in the NMOS transistor Slide 14.22
Dynamic Dissipation The CMOS Inverter Each switching (L H, H L) cycle takes a fixed amount of energy, equal to 2 Power consumption is P dyn = 2 f 0 1 where f 0 1 is the number of times per second that the gate is switched on and off (also called switching activity). Slide 14.23
Dynamic Dissipation Example The CMOS Inverter Compute the capacitive dissipation of the 0.25µm CMOS technology CMOS inverter of previous examples. =6 ff E dyn = V 2 DD = 6. 2.5 2 = 37.5 fj Suppose that the inverter is switched at maximum rate (T= 1/f= t plh +t plh = 2t p = 2x32.5 ps) P dyn = E dyn /2t p = 580 μw However, an inverter in actual circuit rarely switches at the maximum rate Slide 14.24
Dynamic Dissipation Short Circuit Current The CMOS Inverter Falling Transition Vin R p Vout Vin= (0 ) i cc Vout = ( 0) 0V t R n 0V t Rising Transition Vin Vin= ( 0) i cc R p i Vout = (0 ) Vout 0V t R n 0V t Slide 14.25
Minimizing Short Circuit Current Slide 14.26
Leakage Sub-threshold current one of most compelling issues in low-energy circuit design! Slide 14.27
Reverse-Biased Diode Leakage JS = 10-100 pa/µm2 at 25 deg C for 0.25µm CMOS JS doubles for every 9 deg C! Slide 14.28
Subthreshold Leakage Slide 14.29
Principles for Power Reduction Prime choice: Reduce voltage! Recent years have seen an acceleration in supply voltage reduction Design at very low voltages still open question (0.6 0.9 V by 2010!) Reduce switching activity Reduce physical capacitance Device Sizing: for F=20 f opt (energy)=3.53, f opt (performance)=4.47 Slide 14.30
The References CMOS Inverter 1. RABAEY, J; CHANDRAKASAN, A.; NIKOLIC, B. Digital Integrated Circuits: a design perspective. 2 nd Edition. Prentice Hall, 2003. ISBN: 0-13-090996-3. 2. WESTE, Neil; HARRIS, David. CMOS VLSI Design: a circuits and systems perspective. Addison-Wesley, 4 th Edition, 2010. ISBN 978-0321547743. Slide 14.31