INNOVATION and EX C ELL E N C E Ultra-Fast, 1-Bit Linear Monolithic Sample-Hold Amplifiers FEATURES Fast acquisition time: 10ns to ±0.1% 0ns to ±0.0% ns to ±0.01% ±0.001% Nonlinearity 6µV rms output noise 0MHz small signal bandwidth 70MHz full power bandwidth 80dB feedthrough 1ps Aperture jitter 0mW power dissipation Low cost GENERAL DESCRIPTION The is an extremely high-speed and accurate monolithic sample-and-hold amplifier designed for fast data acquisition applications. The is accurate (±0. LSB to 1-bits over the full military temperature range) and is very fast (10ns and 0ns acquisition times to accuracies of 10 and 1 bits respectively). With this high performance and a full power bandwidth of 70MHz, the is an ideal device for driving flash and high-resolution subranging A/D converters. A careful design optimizes the device for accuracy and speed over the full military temperature range. The droop rate is a low ±mv/µs and can be further reduced by adding an optional external hold capacitor. The 0mA output current and guaranteed specifications for a 100Ω load provide high drive capability. Operating from ± V supplies, the consumes only 0mW of power. The is built using a fast complementary bipolar process. The device is available in both military and industrial temperature ranges. The is packaged in a -pin plastic SOIC or in a 0-pin ceramic LCC. / CONNECTIONS SOIC PIN FUNCTION PIN FUNCTION 1 DO NOT CONNECT DO NOT CONNECT 6 DO NOT CONNECT 7 DO NOT CONNECT 8 1 NOT CONNECTED NOT CONNECTED NOT CONNECTED 6 DO NOT CONNECT 7 8 DO NOT CONNECT 9 DO NOT CONNECT 10 / 1 / 1 EXT. CAPACITOR 1 11 10 9 / CONNECTIONS CLCC PIN FUNCTION PIN FUNCTION 0 NOT CONNECTED 19 / 18 / 17 NOT CONNECTED 1 EXT. CAPACITOR 1 1 11 EXTERNAL CAPACITOR 1,, 8 10, 11, 1 +1 CH 1pF +1 9 / 1 SWITCH DRIVE /,, 6, 7 DO NOT CONNECT 1 Note: SOIC Package Pinouts Shown Figure 1. Functional Block Diagram DATEL, Inc., 11 Cabot Boulevard, Mansfield, MA 008-111 (U.S.A.) Tel: (08) 9-000 Fax: (08) 9-66 For immediate assistance (800) -76
ABSOLUTE MAXIMUM RATINGS PARAMETERS LIMITS UNITS +V Supply 0 to +6 Volts V Supply 0 to 6 Volts Analog Input +V Supply 1 Volts V Supply +1 Volts Continuous Output Current ±0 ma Digital Inputs <Supply Voltages Volts Junction Temperature +17 C Lead Temperature (10 seconds) +00 C Output shorted to any supply will cause permanent damage. FUNCTIONAL SPECIFICATIONS (Apply over the operating temperature range using a 100Ω resistive load, 10pF capacitive load, ECL digital input levels, and ±V nominal supplies, unless specified.) S MIN. TYP. MAX. UNITS Input Voltage Range. +. Volts Input Impedance 0. 1 MΩ Digitals Inputs (Balanced ECL) Logic Levels Logic 1 1. +1.8 Volts Logic 0. +0.8 Volts Logic Loading Logic 1 +10 +0 µa Logic 0 0 10 µa S Output Voltage Range. +. Volts Output Current 1 ± 0 ma Output Impedance (dc) 0. 1 Ω Stable Capacitive Load 0 pf PERFORMANCE Nonlinearity (±1V) + C ±0.001 % 0 to +8 C ±0.00 % to +1 C ±0.00 % Sample Mode Offset + C ±1 mv 0 to +8 C ±0 mv to +1 C ±0 mv Pedestal + C ± mv 0 to +8 C ±0 mv to +1 C ±0 mv Gain, + C +0.98 +0.99 V/V Gain Drift (±1V) 0 to +8 C ±0 ppm/ C to +1 C ±0 ppm/ C Aperture Delay 0 to +8 C ns to +1 C ns Aperture Jitter 0 to +8 C 1 ps rms to +1 C 1 ps rms Harmonic Distortion (±1V) dc to 1MHz 7 db dc to 10MHz + C 8 db 0 to +8 C 0 db to +1 C 8 db Acquisition Time (±0.01%, ±V) 0 to +8 C ns to +1 C ns Acquisition Time (±0.0%, ±V) 0 to +8 C 0 ns to +1 C 0 ns Acquisition Time (±0.0%, ±V) 0 to +8 C 19 0 ns to +1 C 0 ns PERFORMANCE (Cont.) MIN. TYP. MAX. UNITS Acquisition Time (±0.1%, ±V) 0 to +8 C 10 ns to +1 C 10 19 ns Hold Mode Settling (±0.01%) 0 to +8 C 1 ns to +1 C 1 ns Hold Mode Settling (±0.0%) 0 to +8 C 7 18 ns to +1 C 7 18 ns Hold Mode Settling (±0.0%) 0 to +8 C 6 ns to +1 C 6 ns Hold Mode Settling (±0.1%) 0 to +8 C 1 ns to +1 C 1 ns Slew Rate ±00 ±0 V/µs Full Power Bandwidth (±1V) 70 MHz Small Signal Bandwidth 100 0 MHz Output Noise, Hold Mode 6 µvrms Feedthrough (V Step) 80 db Droop Rate + C ± ±6 mv/µs 0 to +8 C ± ±1 mv/µs to +1 C ±10 ±0 mv/µs POWER SUPPLY REQUIREMENTS Power Supply Range +V Supply +. + +. Volts V Supply.. Volts Power Supply Current +V Supply +17 + +0 ma V Supply 17 0 ma Power Dissipation 170 0 00 mw Power Supply Rejection Ratio 0 60 db ENVIRONMENTAL Operating Temp. Range, Case S, L 0 +8 C LM +1 C Storage Temperature Range 6 +10 C Package Type S -Pin plastic SOIC L, LM 0-Pin ceramic LCC Footnotes: 1 Short circuit protection at ±0mA. TECHNICAL NOTES The employs an open loop architecture in order to achieve its superior high-speed characteristics. The first stage buffer amplifier, which charges the hold capacitor, incorporates the sample-and-hold switch into its design. This technique allows for a fast acquisition time which is not limited by slew current like the traditional Schottky diode bridge switch. The output amplifier uses a closed loop voltage feedback design which provides a low (0.Ω, typical) output impedance. Gain and linearity are not affected by heavy loads. The design has been optimized to achieve the high accuracy associated with fast transient responses over the full military temperature range. During the track-to-hold transient, the integral nonlinearity is not affected and the pedestal remains constant over the full ±.V input range. An external hold capacitor can be added to the 1pF internal hold capacitor to obtain a lower droop rate (the droop rate is proportional to the inverse of the total hold capacitor value) without increasing transient response times by more than few ns. Settling and acquisition times are typically increased by ns and 10ns respectively for 7pF and 100pF external hold capacitors. The external hold capacitor should not exceed 100pF.
ING AND LAYOUT Obtaining fully specified performance from the requires careful attention to pc-board layout and power supply decoupling. For optimal performance, tie all grounds directly to a large analog ground plane beneath and around the package. Bypass all power supplies to ground with 10µF tantalum capacitors in parallel with ceramic capacitors. Locate the bypass capacitors as close to the unit as possible. For best performance, controlled impedance transmission line techniques, such as microstrip, should be used. Mount all components as close to the required pins as possible. It is strongly recommended that the not be socket-mounted. 0Ω 0 Ω 1 () / / (19) 1 (18) 1 (17) () 0Ω (7) V SUPPLY EXTERNAL CAPACITOR (1) 1 (1) 11 () C Refer to Table 1 for optional capacitor values. + 10µF 8 (10) V SUPPLY 10 (1) 9 (11) 10µF V NOTES: 1. Pin numbers in ( ) are for CLCC package.. For SOIC package: Pins,, 6, 7 DO NOT CONNECT. For CLCC package: Pins 1,,,, 0 NOT CONNECTED Pins 6, 8, 9 DO NOT CONNECT R Load 100Ω +V + Figure. Simplified Connection Diagram -0.8 V -1.8 V -0.8 V -1.8 V +1 V -1 V Acquisition Time to ±0.0% 0ns typ. +1 V -1 V 7ns typ. Track-to-hold Settling to ±0.0% Feedthrough -80dB 7ns typ. 0ns typ. Figure. Control and Timing
Evaluation Board for CLCC-0 Version 0Ω, 17, 18, 19 0 1Ω 7 / / EXTERNAL CAPACITOR 19 18 17, 0 1 1, 1 C 8Ω 0Ω 8Ω Refer to Table 1. for optional capacitor values. 1 6, 7, 8, 9, 10 11, 1, 1 1,,, PLANE 10 11 Figure. Evaluation Board Schematic Table 1. Optional External Capacitor Operating Type of Capacitor Model Temperature Range (Ceramic, 100pF, ±10%) L, -1S 0 to +8 C Type I or II, NPO or X7R LM to +1 C Type I or NPO
0 19 18 17 1 1 1 11 R C1 C7 PLASTIC STANDOFF R1 C6 R6 R C C R C C EXT C 1 6 7 8 9 10 INCHES (mm) 0. (11) 0.100 (.) 0.018 (0.) 0. (.) 1 6 7 8 9 (TOP VIEW) 0.8 (1.9) 0 19 18 17 1 1 1 10 11 1.10 (7.9) (BOTTOM VIEW) 0.9 (.) Figure. Evaluation Board Dimensions Evaluation Board Connections PIN FUNCTION 1 6 7 8 9 10 11 1 1 1 17 18 19 0
MECHANICAL DIMENSIONS INCHES (MM) A 1 8 E D 9 K INCHES MILLIMETERS C F B L J G H SOIC- Package SYMBOL MIN. MAX. MIN. MAX. A 0.0 0.1 10.1 10.6 B 0.00 0.10 10. 10.1 C 0.9 0.99 7.0 7.60 D 0.01 0.019 0. 0.8 E 0.000 BSC 1.7 BSC F 0.009 0.011 0.10 0.0 G 0 8 0 8 H 0.00 0.00 0.1 1.0 J 0.097 0.10.6.6 K 0.010 0.00 0. 0.1 L 0.0091 0.01 0. 0. A CLCC-0 Package G B D C E PIN 1 INDEX INCHES MILLIMETERS SYMBOL MIN. MAX. MIN. MAX. A 0.06 0.100 1.6. B 0.0 0.0 1.1 1.0 C 0.07 REF 1.91 REF D 0. 0.8 8.69 9.09 E 0.0 0.08 0.6 0.71 F 0.00 REF 0.1 G 0.00 BSC 1.7 BSC H 0.00 REF 1.0 (H x H PLACES) F (F x ) BOTTOM VIEW ORDERING INFORMATION MODEL NUMBER PACKAGE TEMPERATURE RANGE S SOIC- 0 to +8 C L CLCC-0 0 to +8 C LM CLCC-0 to +1 C EVB-SHM1 Evaluation Board (with LM) Contact DATEL for availability of high reliability models. INNOV A TION and EX CELLENCE ISO 9001 ISO 9001 R E G I S T E R E D DS-011 10/96 DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 008-111 Tel: (08) 9-000 (800) -76 Fax: (08) 9-66 Internet: www.datel.com E-mail:sales@datel.com Data Sheet Fax Back: (08) 61-87 DATEL (UK) LTD. Tadley, England Tel: (016)-880 DATEL S.A.R.L. Montigny Le Bretonneux, France Tel: 1--60-01-01 DATEL GmbH München, Germany Tel: 89--0 DATEL KK Tokyo, Japan Tel: -779-101, Osaka Tel: 6--0 DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark.