Static CMOS Circuits Conventional (ratio-less) static CMOS Covered so far Ratio-ed logic (depletion load, pseudo nmos) Pass transistor logic ECE 261 Krish Chakrabarty 1 Example 1 module mux(input s, d0, d1, output y); assign y = s? d1 : d0; endmodule 1) Sketch a design using AND, OR, and NOT gates. ECE 261 Krish Chakrabarty 2 1
Example 1 module mux(input s, d0, d1, output y); assign y = s? d1 : d0; endmodule 1) Sketch a design using AND, OR, and NOT gates. ECE 261 Krish Chakrabarty 3 Example 2 2) Sketch a design using NAND, NOR, and NOT gates. Assume ~S is available. ECE 261 Krish Chakrabarty 4 2
Example 2 2) Sketch a design using NAND, NOR, and NOT gates. Assume ~S is available. ECE 261 Krish Chakrabarty 5 Bubble Pushing Start with network of AND / OR gates Convert to NAND / NOR + inverters Push bubbles around to simplify logic Remember DeMorgan s Law ECE 261 Krish Chakrabarty 6 3
Example 3 3) Sketch a design using one compound gate and one NOT gate. Assume ~S is available. ECE 261 Krish Chakrabarty 7 Example 3 3) Sketch a design using one compound gate and one NOT gate. Assume ~S is available. ECE 261 Krish Chakrabarty 8 4
Compound Gates Logical Effort of compound gates ECE 261 Krish Chakrabarty 9 Example 4 The multiplexer has a maximum input capacitance of 16 units on each input. It must drive a load of 160 units. Estimate the delay of the NAND and compound gate designs. H = 160 / 16 = 10 B = 1 N = 2 ECE 261 Krish Chakrabarty 10 5
NAND Solution ECE 261 Krish Chakrabarty 11 NAND Solution ECE 261 Krish Chakrabarty 12 6
Compound Solution ECE 261 Krish Chakrabarty 13 Compound Solution ECE 261 Krish Chakrabarty 14 7
Example 5 Annotate your designs with transistor sizes that achieve this delay. Informal homework exercise (see textbook)! ECE 261 Krish Chakrabarty 15 Input Order Our parasitic delay model was too simple Calculate parasitic delay for Y falling If A arrives latest? If B arrives latest? ECE 261 Krish Chakrabarty 16 8
Input Order Our parasitic delay model was too simple Calculate parasitic delay for Y falling If A arrives latest? 2 If B arrives latest? 2.33 ECE 261 Krish Chakrabarty 17 Inner & Outer Inputs Outer input is closest to rail (B) Inner input is closest to output (A) If input arrival time is known Connect latest input to inner terminal ECE 261 Krish Chakrabarty 18 9
Asymmetric Gates Asymmetric gates favor one input over another Ex: suppose input A of a NAND gate is most critical Use smaller transistor on A (less capacitance) Boost size of noncritical input So total resistance is same g A = 10/9 g B = 2 g total = g A + g B = 28/9 Asymmetric gate approaches g = 1 on critical input But total logical effort goes up ECE 261 Krish Chakrabarty 19 Symmetric Gates Inputs can be made perfectly symmetric ECE 261 Krish Chakrabarty 20 10
Skewed Gates Skewed gates favor one edge over another Ex: suppose rising output of inverter is most critical Downsize noncritical nmos transistor Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge. g u = g d = ECE 261 Krish Chakrabarty 21 Skewed Gates Skewed gates favor one edge over another Ex: suppose rising output of inverter is most critical Downsize noncritical nmos transistor Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge. g u = 2.5 / 3 = 5/6 g d = 2.5 / 1.5 = 5/3 ECE 261 Krish Chakrabarty 22 11
HI- and LO-Skew Def: Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition. Skewed gates reduce size of noncritical transistors HI-skew gates favor rising output (small nmos) LO-skew gates favor falling output (small pmos) Logical effort is smaller for favored direction But larger for the other direction ECE 261 Krish Chakrabarty 23 Catalog of Skewed Gates ECE 261 Krish Chakrabarty 24 12
Catalog of Skewed Gates ECE 261 Krish Chakrabarty 25 Catalog of Skewed Gates ECE 261 Krish Chakrabarty 26 13
Asymmetric Skew Combine asymmetric and skewed gates Downsize noncritical transistor on unimportant input Reduces parasitic delay for critical input ECE 261 Krish Chakrabarty 27 Best P/N Ratio We have selected P/N ratio for unit rise and fall resistance (μ = 2-3 for an inverter). Alternative: choose ratio for least average delay Ex: inverter Delay driving identical inverter t pdf = t pdr = t pd = Differentiate t pd w.r.t. P Least delay for P = ECE 261 Krish Chakrabarty 28 14
Best P/N Ratio We have selected P/N ratio for unit rise and fall resistance (μ = 2-3 for an inverter). Alternative: choose ratio for least average delay Ex: inverter Delay driving identical inverter t pdf = (P+1) t pdr = (P+1)(μ/P) t pd = (P+1)(1+μ/P)/2 = (P + 1 + μ + μ/p)/2 Differentiate t pd w.r.t. P Least delay for P = ECE 261 Krish Chakrabarty 29 P/N Ratios In general, best P/N ratio is sqrt of that giving equal delay. Only improves average delay slightly for inverters But significantly decreases area and power ECE 261 Krish Chakrabarty 30 15
Observations For speed: NAND vs. NOR Many simple stages vs. fewer high fan-in stages Latest-arriving input For area and power: Many simple stages vs. fewer high fan-in stages ECE 261 Krish Chakrabarty 31 Combinational vs. Sequential Logic I n L o g i c C i r c u i t O u t I n L o g i c C i r c u i t O u t S t a t e ( a ) C o m b i n a t i o n a l ( b ) S e q u e n t i a l O u t p u t = f ( I n ) O u t p u t = f ( I n, P r e v i o u s I n ) ECE 261 Krish Chakrabarty 32 16
Static CMOS Circuit (Review) At every point in time (except during the switching transients) each gate output is connected to either V DD or V ss via a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. ECE 261 Krish Chakrabarty 33 Static CMOS (Review) V D D I n 1 I n 2 I n 3 P U N P M O S O n l y I n 1 I n 2 I n 3 P D N F = G N M O S O n l y V S S P U N a n d P D N a r e D u a l N e t w o r k s ECE 261 Krish Chakrabarty 34 17
Properties of Complementary CMOS Gates (Review) H i g h n o i s e m a r g i n s : V O H a n d V O L a r e a t V D D a n d G N D, r e s p e c t i v e l y. N o s t a t i c p o w e r c o n s u m p t i o n : T h e r e n e v e r e x i s t s a d i r e c t p a t h b e t w e e n V D D a n d V S S ( G N D ) i n s t e a d y - s t a t e m o d e. C o m p a r a b l e r i s e a n d f a l l t i m e s : ( u n d e r t h e a p p r o p r i a t e s c a l i n g c o n d i t i o n s ) ECE 261 Krish Chakrabarty 35 Influence of Fan-In and Fan-Out on Delay V D D A B C A D F a n - O u t : N u m b e r o f G a t e s C o n n e c t e d Every fanout (output) adds two gate capacitances (pmos and nmos) B C D F a n I n : Q u a d r a t i c T e r m d u e t o : 1. R e s i s t a n c e I n c r e a s i n g 2. C a p a c i t a n c e I n c r e a s i n g t p = a 1 F I + a 2 F I 2 + a 3 F O ECE 261 Krish Chakrabarty 36 18
Fast Complex Gate-Design Techniques T r a n s i s t o r S i z i n g : A s l o n g a s F a n - o u t C a p a c i t a n c e d o m i n a t e s P r o g r e s s i v e S i z i n g : I n N I n 3 I n 2 I n 1 M N M 3 M 2 M 1 O u t C L M 1 > M 2 > M 3 > M N C 3 C 2 C 1 ECE 261 Krish Chakrabarty 37 Fast Complex Gate - Design Techniques T r a n s i s t o r O r d e r i n g c r i t i c a l p a t h c r i t i c a l p a t h I n 3 M 3 C L I n 1 M 1 C L I n 2 M 2 C 2 I n 2 M 2 C 2 I n 1 M 1 C 1 I n 3 M 3 C 3 ( a ) ( b ) ECE 261 Krish Chakrabarty 38 19
Fast Complex Gate - Design Techniques I m p r o v e d L o g i c D e s i g n ECE 261 Krish Chakrabarty 39 Ratioed Logic V D D V D D V D D R e s i s t i v e L o a d I n 1 I n 2 I n 3 P D N R L F D e p l e t i o n L o a d I n 1 I n 2 I n 3 P D N V T < 0 F P M O S L o a d V S S I n 1 I n 2 I n 3 P D N F V S S V S S V S S ( a ) r e s i s t i v e l o a d ( b ) d e p l e t i o n l o a d N M O S ( c ) p s e u d o - N M O S G o a l : t o r e d u c e t h e n u m b e r o f d e v i c e s o v e r c o m p l e m e n t a r y C M O S Careful design needed! ECE 261 Krish Chakrabarty 40 20
Ratioed Logic V D D V O H = V D D R e s i s t i v e L o a d R L V OL = R PDN R L + R PDN V DD F Desired: R L >> R PDN (to keep noise margin low) I n 1 I n 2 I n 3 P D N R PDN t PLH = 0.69R L C L Problems: 1) Static power dissipation V S S 2) Difficult to implement a large resistor, eg 40k resistor (typical value) needs 3200 μ 2 of n-diff, i.e. 1,000 transistors! ECE 261 Krish Chakrabarty 41 V D D Active Loads V D D D e p l e t i o n L o a d V T < 0 P M O S L o a d V S S F F I n 1 I n 2 I n 3 P D N I n 1 I n 2 I n 3 P D N V S S ECE 261 Krish Chakrabarty 42 V S S d e p l e t i o n l o a d N M O S p s e u d o - N M O S Depletion-mode transistor has negative threshold On if V GS = 0 Body effect may be a problem! 21
Pseudo-nMOS V D D A B C D F C L No problems due to body effect N-input gate requires only N+1 transistors Each input connects to only a single transistor, presenting smaller load to preceding gate Static power dissipation (when output is zero) Asymmetric rise and fall times Example: Suppose minimal-sized gate consumes 1 mw of static power. 100, 000 gate-circuit: 50 W of static power (plus dynamic power)! (half the gates are in low-output state) Effective only for small subcircuits where speed is important, eg address decoders in memories ECE 261 Krish Chakrabarty 43 Pseudo-NMOS NAND Gate V DD GND ECE 261 Krish Chakrabarty 44 22
Pass-Transistor Logic B Inputs S w i t c h N e t w o r k O u t A B B O u t Is this transmission gates necessary? AND gate Need a low impedance path to ground when B = 0 N o s t a t i c c o n s u m p t i o n ECE 261 Krish Chakrabarty 45 Pass-Transistor Based Multiplexer F = AS + BS V DD S S Out F GND In 1 S S In 2 ECE 261 Krish Chakrabarty 46 23
Transmission Gate XOR B 6 transistors only! M 2 B Case 1: B = 1, M3/M4 turned off, F = AB A M 1 F B A M 3 / M 4 Case 2: B = 0, M3/M4 turned on, F = AB B F always has a path to V DD or Gnd, hence low impedance node If not, node would be dynamic, requiring refresh due to charge leakage ECE 261 Krish Chakrabarty 47 Delay in Transmission Gate Networks 5 5 5 5 I n V 1 V i - 1 V i V i + 1 V n - 1 V n C 0 0 C 0 C C 0 C ( a ) I n R e q R V e q R e q R 1 V i V i + 1 V e q n - 1 V n C C C C C m ( b ) R e q R e q R e q R e q R e q R e q I n C C C C C C C C ( c ) Insert buffers after every m switches ECE 261 Krish Chakrabarty 48 24
Delay in Transmission Gate Networks Consider Kirchoff s Law at node V i V i+1 -V i + V i-1 -V i C dv i = R eq R eq dt Therefore, dv i = dt V i+1 + V i-1-2v i R eq C Propagation delay can be determined using Elmore delay analysis ECE 261 Krish Chakrabarty 49 Delay Optimization Delay can be reduced by adding buffers after m stages (t buf = delay of a buffer) ECE 261 Krish Chakrabarty 50 25
Transmission Gate Full Adder ECE 261 Krish Chakrabarty 51 NMOS Only Logic: Level Restoring Transistor L e v e l R e s t o r e r B A M n V D D M r X V D D M 2 O u t M 1 A d v a n t a g e : F u l l S w i n g D i s a d v a n t a g e : M o r e C o m p l e x, L a r g e r C a p a c i t a n c e O t h e r a p p r o a c h e s : r e d u c e d t h r e s h o l d N M O S ECE 261 Krish Chakrabarty 52 26
Single Transistor Pass Gate with V T =0 ECE 261 Krish Chakrabarty 53 Complimentary Pass Transistor Logic A A B B Pass-Transistor Network The image cannot be displayed. Your computer may not have enough F (a) A A B B Inverse The image cannot be displayed. Your Pass-Transistor computer may not have enough Network F B B B B B B A A A B F=AB B F=A+B A F=A A A A (b) B F = AB B F = A+B A F = A AND/NAND OR/NOR EXOR/NEXOR ECE 261 Krish Chakrabarty 54 27
4 Input NAND in CPL ECE 261 Krish Chakrabarty 55 28