Synthesis o Hzrd-Free Multilevel Logi Under Multiple-Input Chnges rom Binry Deision Digrms Bill Lin, Memer, IEEE, Srinivs Devds, Memer, IEEE Astrt We desrie new method or diretly synthesizing hzrdree multilevel logi implementtion rom given logi speiition. The method is sed on ree/ordered Binry Deision Digrms (BDD s), nd is nturlly pplile to multiple-output logi untions. Given n inompletely-speiied (multiple-output) Boolen untion, the method produes multilevel logi network tht is hzrd-ree or speiied set o multiple-input hnges. We ssume n ritrry (unounded) gte nd wire dely model under pure dely (PD) ssumption, we permit multipleinput hnges, nd we onsider oth stti nd dynmi hzrds under the undmentl-mode ssumption. Our rmework is thus generl nd powerul. While it is not lwys possile to generte hzrd-ree implementtions using our tehnique, we show tht in some ses hzrd-ree multilevel implementtions n e generted when hzrd-ree two-level representtions nnot e ound. This prolem is generlly regrded s diiult prolem nd it hs importnt pplitions in the ield o synhronous design. The method hs een utomted nd pplied to numer o exmples. The results we hve otined re very promising. A I. INTRODUCTION SYNCHRONOUS design styles re eoming inresingly populr euse they oer the potentil eneits o improved system perormne, voidne o loking prolems, low-power opertion, nd modulr design [8], [7], [8], [4], [26], [9], [2], [28], [2], [2], [5], [6], [27], []. However, the design o orret synhronous iruitry is diiult tsk sine n synhronous iruit n mluntion (i.e. produe unexpeted ehvior) during exeution i it is not ree o hzrds, whih orrespond to undesired glithes in iruit. This is in ontrst with synhronous design styles where the prolem is voided y the use o glol loking sheme tht oordintes nd synhronizes ll olletive tivities. In this pper, we ous on prtiulr lss o hzrds nmely hzrds in omintionl logi. Hzrd-ree omintionl logi is ritil to the orretness o most synhronous designs. Our gol in this work is to develop method tht n synthesize omintionl logi tht voids ll omintionl hzrds under speiied set o multiple-input hnges. This is generl omintionl synthesis prolem whih rises in mny synhronous sequentil pplitions. For exmple, the prolem rises in the urrent synthesis trjetories or synhronous inite stte mhines [2], [28]. In this work, we ssume tht gtes nd wires n hve ritrry delys, whih mens we do not require ounded dely ssumptions or orret opertion or the use o dely elements to ix or ilter out glithes. We lso ssume pure dely (PD) model, whih mens we do not ssume Mnusript reeived Deemer 8, 993; Ferury 7, 995. This pper ws reommended y Assoite Editor K. Keutzer. B. Lin is with IMEC, B-3 Leuven, Belgium. S. Devds is with the Deprtment o EECS, MIT, Cmridge, MA 239 USA. IEEE Log Numer 9423. the presene o slow inertil delys to insure orretness. The two-level minimiztion version o the prolem hs een ddressed y numer o reserhers in the pst [25], [6], [], [5], [3], [4], []. More reently, Nowik [22] hs developed n ext two-level minimizer tht omines numer o previous ides on this prolem. A limittion o the two-level implementtion pproh is tht it is not lwys possile to ind two-level over tht n insure reedom rom ll stti nd dynmi hzrds even though hzrd-ree multilevel implementtion my exist. In this pper, we desrie new rmework sed on Binry Deision Digrms (BDD s) or synthesizing hzrd-ree multilevel logi implementtion diretly rom logi desription. A Binry deision digrm is direted yli grph representtion o Boolen untion. BDD s hve gined widespred use in the res o orml veriition nd logi synthesis due to the nonil nd esily mnipulle nture o lss o BDD s [7]. Our rmework is sed on the use o oth ree s well s ordered BDD s nd is nturlly pplile to multiple-output logi untions. We permit multiple-input hnges, nd we onsider oth stti nd dynmi hzrds, whih mens the resulting rmework is generl nd powerul. In prtiulr, we show tht multiplexor logi network derived rom redued ree or ordered BDD y repling eh node in the BDD y twoinput multiplexor is ree o ll stti logi hzrds. For dynmi logi hzrds, we hve developed the Trigger Signl Ordering Requirement (or TSO-Requirement or short) on the BDD vrile ordering tht, i stisied, will led to multiplexor logi network tht is lso ree o ll dynmi logi hzrds or the given set o llowle input trnsitions. The resulting multiplexor logi network is proved to e ully hzrd-ree under ritrry gte nd wire delys. While it is not lwys possile to generte hzrd-ree implementtions using our tehnique, even i n implementtion theoretilly exists, in mny ses we re le to generte hzrd-ree multilevel implementtions when hzrd-ree two-level implementtions nnot e ound. We hve lso developed se replement strtegies tht n reple multiplexor y untionl equivlent sum-o-produts representtion whih preserves the hzrd-ree properties. We provide hrteriztion on when suh replements re possile. The prt o the network tht n e sely repled y AND- nd OR- gtes n e urther optimized using nonhzrd-inresing logi trnsormtions, suh s the ones disussedin[3]. Our omintionl logi synthesis method n e pplied diretly to the synthesis o hzrd-ree logi or synhronous stte mhines tht operte under the undmentl mode s-
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 4, NO. 8, AUGUST 995 2 sumption [2], [28]. Further, it n e generlized to the extended urst-mode stte mhine se [29]. We hve utomted our method nd hve pplied it to numer o exmples. The results we hve otined re very promising. A. Bsi Deinitions II. BACKGROUND To simpliy the disussion, we will onsider single-output untions only with inry input nd output vriles. Extension to multiple-output untions is strightorwrd. Let ; g n e Boolen spe. Eh A 2 ; g n,orresponding to point in the Boolen spe, is reerred to s minterm. It will lso e reerred to s n input stte or simply stte. A Boolen untion,, on vriles, x ;x 2 ;:::;x n,isdeined s mpping: : ; g n!;;æg. TheON-set o untion is the set o minterms or whih the untion hs vlue. The OFF-set is the set o minterms or whih the untion hs vlue. TheDC-set (don t-re set) is the set o minterms or whih the untion hs the vlue æ. A ue o Boolen untion is written s = ë ; æææ; n ë.for ç i ç n, i is i vrile x i ppers omplemented in, i is i vrile x i ppers unomplemented in, nd i is, i x i does not pper in. Thus, ue is set o minterms. We will write 2 d, i ue is suh tht or eh position in tht hs the orresponding position in ue d hs or,, nd or eh position in tht hs the orresponding position in d hs or,. The intersetion o two ues nd d is empty i there is position i where i = nd d i = or vie vers. I the intersetion is not empty, then it n e omputed s new ue e = ë d, wheree i =i either i =or d i =, e i =i either i =or d i =,nde i =, otherwise. A trnsition ue is ue with strt point nd n end point. Given input sttes A nd B, the trnsition ue ëa; Bë rom A to B hs strt point A nd end point B nd ontins ll minterms tht n e rehed during trnsition rom A to B. It n e represented y the smllest ue tht ontins oth A nd B. The open trnsition ue ëa; Bè rom A to B is deined s ëa; Bë, B. A multiple-input hnge or input trnsition rom input stte A to B is desried y trnsition ue ëa; Bë. We will use the nottion A è B to denote the the input trnsition rom A to B. Input vriles re ssumed to hnge simultneously. Equivlently, sine inputs my e skewed ritrrily y wire delys, inputs n e ssumed to hnge monotonilly in ny order nd t ny time. One multiple-input hnge ours, no urther input hnges my our until the iruit hs stilized. An input trnsition rom stte A to B or Boolen untion is sttitrnsitioni èaè = èbè;itis dynmi trnsition i èaè 6= èbè. In the se o n inompletely speiied untion, we ssume tht is ully deined or every speiied stti nd dynmi trnsition; tht is, or every X 2 ëa; Bë, èxè 2 ; g. B. Modeling Delys We ssume gtes nd wires in omintionl iruit n hve ritrry inite delys. Eh gte is modelled s n instntneous Boolen opertor with dely element tthed to its output wire. This dely element desries the totl gte dely. Eh wire is modelled s onnetion with n tthed dely element. This dely element desries the totl wire dely. The delys my hve ritrry ut inite vlues. Sine dely elements re tthed only to wires, this model hs een lled the unounded wire dely model. We ssume pure dely model, whih mens pulse o ny length n propgte. A dely ssignment is n ssignment o ixed inite dely vlues to every gte nd wire in iruit. C. Funtion Hzrds A untion whih does not hnge monotonilly during n inputtrnsition is sid to hveuntion hzrd in the trnsition. Deinition (Stti untion hzrd) A Boolen untion ontins stti untion hzrd or input trnsition rom A to C i:. èaè =ècè, nd 2. there exists some stte B 2 ëa; Cë suhtht èaè 6= èbè. Deinition 2 (Dynmi untion hzrd) A Boolen untion ontins dynmi untion hzrd or input trnsition rom A to D i:. èaè 6= èdè, nd 2. there exists pir o sttes B nd C (A 6= B; C 6= D) suh tht () B 2 ëa; Dë nd C 2 ëb; Dë nd () èbè =èdènd èaè =ècè. I trnsition hs untion hzrd, no implementtion o the untion n void glith on the trnsition, ssuming ritrry gte nd wire delys [], [5]. Thereore, we onsider only trnsitions whih re ree o untion hzrds (see [], [4], [3]). D. Logi Hzrds I is ree o untion hzrds or trnsition rom input A to B, it my still hve hzrds due to possile delys in the tul logi reliztion. Deinition 3 (Stti logi hzrds) A omintionl iruit or untion ontins stti logi hzrd or the input trnsition rom A to B i:. èaè =èbè 2. For some dely ssignment, the iruit s output hnges momentrily during the trnsition intervl. This mens tht we hve one or more!! (or!! ) trnsitions while the speiied ehvior is stti (or stti ). Deinition 4 (Dynmi logi hzrds) A omintionl iruit or untion ontins dynmi logi hzrd or the input trnsition rom A to B i:. èaè 6= èbè
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 4, NO. 8, AUGUST 995 3 2. For some dely ssignment, the iruit s output is not monotoni during the trnsition intervl. This mens tht we hve!!! (or!!! ) trnsitions while the speiied ehvior is single! trnsition (or! trnsition). III. BINARY DECISION DIAGRAMS AND DERIVED MULTIPLEXOR NETWORKS A. Binry Deision Digrms In this setion, we will restte rom [7] the deinitions or ree Binry Deision Digrms nd redued ordered Binry Deision Digrms. We will then indite how multiplexor-sed multilevel logi network n e derived rom them. Given Boolen untion, the untion resulting when some rgument x i o the untion is repled y onstnt 2 ; g is lled otor o the untion with respet to x i =, nd this is denoted s j xi=. Tht is, or ny rguments x ;:::;x n, j xi=èx ;:::;x n è=èx ;:::;x i, ;;x i+ ;:::;x n è hve indexèvè é indexèlowèvèè; ndihighèvè is lso nonterminl, then we must hve indexèvè é indexèhighèvèè. A redued ree Binry Deision Digrm (or simply ree BDD) is BDD where we require tht we enounter eh vrile t most one in ny pth in the BDD nd tht the BDD is redued, ut do not require strit vrile ordering restritions on BDD s. Tht is, dierent pths my hve dierent vrile ordering s long s eh vrile is enountered t most one long ny pth. B. Deriving Multilevel Multiplexor Logi Network A multilevel logi network n e derived diretly rom BDD y repling eh BDD vertex with two-input MUX- ELEMENT. An exmple is shown in Figure. A BDD nd its orresponding derived multiplexor multilevel network re shown in Figure () nd (), respetively. The multiplexor network n e simpliied y mens o onstnt propgtion. Tht is, the MUX-ELEMENTs n e repled y simpler gtes i one or more o its inputs is onstnt. This propgtion n e rried out topologilly rom inputs to outputs. The simpliied network is shown in Figure (). Using this nottion, the Shnnon expnsion o untion with respet to vrile x i is given y: = x i æ j xi= + x i æ j xi= Deinition 5 (BDD) A Binry Deision Digrm is rooted, direted yli grph with vertex set V ontining two types o verties. A non-terminl vertex v hs s ttriutes n rgument index indexèvè 2 ;:::;ng nd two hildren lowèvè; highèvè 2 V. A terminl vertex v hs s ttriute vlue vlueèvè 2;g. The orrespondene etween BDD s nd Boolen untions is deined s ollows: Deinition 6 A Binry Deision Digrm G hving root vertex v denotes untion v deined reursively s:. I v is terminl vertex: () I vlueèvè =,then v =. () I vlueèvè =,then v =. 2. I v is non-terminl vertex with indexèvè = i, then v is the untion: x i is lled the deision vrile or vertex v. We require the ollowing dditionl properties in Binry Deision Digrms:. When trversing ny pth rom terminl vertex to the root vertex we n enounter eh deision vrile t most one. 2. A redued BDD is one in whih lowèvè 6= highèvè or ny vertex v nd no two sugrphs in the BDD re identil. From Deinition 5, nonil orm lled redued ordered Binry Deision Digrm [7] (or simply ordered BDD) n e derived i the ollowing restritions re imposed: or ny nonterminl vertex v,ilowèvè is lso non-terminl, then we must () () () Fig.. () A BDD. () The derived multiplexor multilevel network. () Simpliition o multiplexors y onstnt propgtion. IV. STATIC HAZARD-FREE SYNTHESIS FROM BDD S The hzrd-ree synthesis prolem n e stted s ollows. Given: A (possily inompletely speiied) Boolen untion,ndset,t o speiied untion-hzrd-ree (oth stti nd dynmi) input trnsitions o. Find: A multilevel logi implementtion tht is ree o logi v èx ;:::;x n è=x i æ lowèvè èx ;:::;x n è+x i æ highèvè èx ;:::;x n è hzrds or every input trnsition t 2 T. In this pper, we propose synthesis proedures rom BDD s tht n produe hzrd-ree multilevel logi implementtions. Let us irst onsider simple proedure tht trnsorm n inompletely speiied untion to multiplexor network. I the untion is inompletely speiied, then some preproessing is required s ollows: in the se o n inompletely speiied untion, the don t-re minterms ontined inside some speiied trnsition t 2 T must e ssigned properlyso tht no untionl hzrds n our. The other don t re minterms n e used or optimiztion, or exmple using tehniques desried in [9], [24] (. the restrit nd the generlized otor opertors). So or ll prtil purposes, we only need to onsider
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 4, NO. 8, AUGUST 995 4 ompletely speiied untions. One this preproessing step is perormed, the synthesis proedure is s ollows:. Construt BDD G or the Boolen untion. The BDD here is ment to e either n ordered or ree redued BDD, where eh vrile n pper t most one long ny pth. 2. Generte multilevel iruit C y repling eh BDD node with two-input MUX-ELEMENT. For the hzrd nlysis in this setion, we will irst ssume tht the MUX-ELEMENT is n tomi gte with no internl hzrds, nd tht the MUX-ELEMENT nd the wires onneting them n hve ritrry delys. An implementtion o hzrdree multiplexor is shown in Figure 2. The only onstrint on the lyout o the gte is tht the dierene in the delys o the two pths rom the ontrol input tht pss through the uer nd the inverter should e smller thn the inertil dely orresponding to trnsistor turning on or o. Fig. 2. A trnsistor-level implementtion o hzrd-ree multiplexor. The logil untion implemented y the gte is = æ +æ. This untion is ree o ll dynmi hzrds, ut hs potentil stti logi hzrd on the! trnsition on with nd onstnt t. However, i the pth lning riterion stted ove is met, then the implementtion o the MUX-ELEMENT will not hve stti hzrd. We will irst nlyze stti hzrd properties o suh networks ssuming the MUX-ELEMENT s si hzrd-ree element. We will deer to Setion VI the disussion regrding the replement o MUX-ELEMENTs with si gtes, the onstnt propgtion issue, nd possile simpliition nd resynthesis steps. Theorem (Stti logi hzrd-reeness) Let C e iruit derived rom BDD G y repling eh node in G with hzrd-ree multiplexor. C is ree o ll possile stti hzrds under ny multiple-input hnge tht does not orrespond to untion hzrd. Proo: Without loss o generlity we will ssume single speiied stti trnsition A è B. The iruit C implements the Boolen untion whih is ree o untion hzrds or the speiied input trnsition A è B. Further the iruit C hs een derived using the synthesis proedure outlined. Assume tht the multiplexor driving the output o C hs s its ontrol vrile. The dt inputs to the multiplexor orresponds to untions nd, the Shnnon otors o with respet to nd. Assume tht is to mke stti! trnsition, i.e. èaè =nd èbè =. We will irst onsider the se when the input is t onstnt. Clerly, i is, will e ree o stti hzrds i remins t onstnt nd is ree o hzrds. We know tht èaè =nd èbè =. Further we know tht 8m 2 ëa; Bë, èmè =. Otherwise, it implies tht there is untion hzrd ssoited with. Sine n only mke stti trnsition in A è B, lerly will e ree o stti hzrds i is ree o stti hzrds. One n reursively pply the nlysis ove to to show tht it is ree o stti hzrds. We will inlly reh the se se where the ontrol vrile to the muliplexor is x nd oth the dt inputs re onstnts. I oth dt inputs re the sme, then this multiplexor will not exist in the BDD or the iruit C y the redution rules o BDDs. Otherwise, this multiplexor redues to either the literl untion x or its negtion x. Then the input x is ssumed to remin t onstnt in the se o x nd t onstnt in the se o x. Otherwise, there is untion hzrd ssoited with. In the se when the input is t onstnt, then will e ree o stti hzrds i is ree o hzrds. This ollows rom similr rguments s ove. Next onsider the se when the input mkes! trnsition or! trnsition orresponding to A è B. Clerly will e ree o stti hzrds i oth nd re ree o hzrds. We lim tht oth èaè = èbè = nd èaè = èbè =. Further we lim tht 8m 2 ëa; Bë, èmè = èmè=. Thereore, oth nd n only mke stti trnsition in A è B. Thus, it is suiient to show tht they re ree o stti hzrds. Agin, this rgument n e reursively pplied to nd with the sme se se s ove. Sine oth nd remin t onstnt nd re hzrd ree, only the ontrol vrile n hnge t the multiplexor ssoited t the output o. By the ssumption tht the multiplexor is n tomi gte nd is internlly hzrd-ree, then is lso ree o stti hzrds or the stti trnsition ëa; Bë. The proo or the se when mkes stti! trnsition ollows similrly. Theorem sttes tht the derived iruit is ree o stti hzrds or ny input trnsition tht does not use untion hzrd. So we now sy tht multiplexor implementtion rom either ree or n ordered BDD is ree o ll untion hzrds (y deinition) nd ree o ll stti logi hzrds. An importnt orollry is s ollows. Corollry The stti hzrd-reeness o C is independent o the vrile ordering hosen or the BDD G. Further, the BDD G n e ree BDD with dierent orderings long dierent pths. Proo: Follows rom Theorem. This mens tht there re no restritions on the vrile ordering or stti hzrds. This is however not lwys the se or dynmi logi hzrds, s will e desried next. V. DYNAMIC HAZARD-FREE SYNTHESIS FROM BDD S While multiplexor implementtion derived rom redued BDD is gurnteed to e ree o stti logi hzrds, it is not neessrily ree o dynmi logi hzrds. In this setion, we will irst hrterize the prolem. Then we will present method tht will ensure the non-existene o dynmi hzrds s well.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 4, NO. 8, AUGUST 995 5 A. The Prolem Let us onsider n exmple shown in Figure 3. Let us onsider the dynmi input trnsition æ æ è ; where èè = nd èè = : We will use " æ " to indite tht the orresponding signl is exited to hnge. In this se, the signls nd re exited to mke the trnsitions + nd +. The orresponding trnsition ue is ë; ë =,,: Now suppose we implement n ordered BDD with the vrile ordering éé. The orresponding BDD is shown in Figure 4. T Fig. 3. Dynmi-hzrd exmple. T2 T3 = T T2 Fig. 4. BDD implementtion with ordering éé. Let us onsider multiplexor implementtion trnslted rom this BDD. This multiplexor implementtion n exhiit dynmi hzrd s ollows:. Initilly, =, =, =. This implies T =, T2=, T3 =,ndf =, wheretheti s re the output o the multiplexors nd F is the output o the iruit. 2. In the trnsition è, oth n + nd + n our onurrently. Rell tht under the unounded gte/wire dely ssumption, either + n our irst or + n our irst, ut we must onsider oth trnsition orderings. Let us ssume + ours irst nd mkes! trnsition. 3. Then T 2 mkes! trnsition, ut T is slow to hnge. F mkes! trnsition. 4. Then let + hppen, mking! trnsition, ut T is still slow to hnge to, mening it is still t vlue. This will use F to hnge! k to. 5. Finlly, T hnges rom!. This uses F to hnge! k to. Thus, the trnsition sequene!!! hs ourred on F, dynmi hzrd hs een mniested. However, when + ours irst, the dynmi trnsition tkes ple without ny dynmi logi hzrds. This is euse when + ours irst, nothing hnges. Then when + ours, T will hnge, whih will use F to hnge, ut F only hnges one. Now onsider insted n lterntive BDD implementtion using vrile orderings ééor éé, shown in Figure 5 () nd (), respetively. T (A) < < T2 T (B) < < Fig. 5. BDD implementtion with orderings () éénd () éé. Let us irst onsider multiplexor implementtion trnslted rom the BDD shown in Figure 5 (). This multiplexor implementtion is ree o dynmi hzrds under the trnsition è. The nlysis is s ollows.. Initilly, =, =, =. This implies T =, T2=, nd F =. 2. I + hppens irst, then F will hnge!. Then when + ours, nothing else hnges. Hene there is no dynmi hzrd. 3. I + hppens irst, nothing hppens. Then when + ours, F hnges rom!. Agin no dynmi hzrd ours. Let us now onsider multiplexor implementtion trnslted rom the BDD shown in Figure 5 (). This multiplexor implementtion is ree o dynmi hzrds under the trnsition è. The nlysis is s ollows.. Initilly, =, =, =. This implies T =, T2=, nd F =. 2. I + hppens irst, then F will hnge!. Then when + ours, nothing else hnges. Hene no dynmi hzrd ours. 3. I + hppens irst, nothing hppens. Then when + ours, F hnges rom!. Agin no dynmi hzrd ours. From this inorml introdution, we will show tht the vrile ordering in t plys very importnt role in gurnteeing reedom rom dynmi hzrds. Rell tht we hve lredy stted tht BDD implementtions re ree o stti hzrds. The removl o dynmi hzrds is ddressed next. B. Conditions or Dynmi Hzrd-Freeness In this setion, we will onsider the requirements on the BDD synthesis proedure in order to produe multiplexor implementtion ree o dynmi logi hzrds. We will irst onsider this requirement with respet to n ordered BDD implementtion. We will deer to Setion V-E the disussion regrding the employment o ree or unordered BDD s to stisy the sme requirement. The key to the nlysis is the onept o trigger signls. T2
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 4, NO. 8, AUGUST 995 6 Deinition 7 (Context signl) Given n input trnsition A è B, signl q is sid to e ontext signl i it hnges its vlue ross A nd B. I it remins t onstnt vlue in A nd B, then it is sid to e non-ontext signl. By the deinition o input trnsition (. Setion II-A), ontext signl n only monotonilly hnge one during A è B trnsition. Deinition 8 (Exited signl) Given stte X 2 ëa; Bë in the input trnsition A è B, ontext signl q is sid to e exited in X i nd only i its vlue in X is equl to its vlue in A. Deinition 9 (Quiesent signl) Given stte X 2 ëa; Bë in the input trnsition A è B, ontext signl q is sid to e quiesent signl in X i its vlue in X is equl to its vlue in B. In the exmple shown in Figure 3, signls nd re ontext signls in the trnsition è use oth re enled to hnge vlues, wheres is non-ontext signl in this trnsition. Signls nd re exited in stte euse oth signls n hnge. In the stte, only is exited ; the signl is quiesent in stte. Deinition (Trigger stte, signl, trnsition) A stte X 2 ëa; Bë in dynmi input trnsition A è B is sid to e trigger stte or A è B i nd only i there is n exited signl q (q+ or q,) suh tht the stte Y 2 ëa; Bë rehed y hnging q hs dierent output vlue rom X: i.e., èxè 6= èy è. The signl q is lled trigger signl o X in A è B, nd the orresponding trnsition, either q+ or q,, is lled trigger trnsition o X in A è B. In given trigger stte, n exited signl tht will not use the output to hnge is reerred to s non-trigger signl. Its orresponding trnsition is reerred to s non-trigger trnsition. Reerring gin to Figure 3, sttes nd sttes re trigger sttes sine èè nd èè re oth equl to, ut there exists signl trnsition rom either stte tht will use the output to hnge to. In the se o, oth nd re exited to hnge. Chnging will use the output to hnge to. In this se, is trigger signl nd + is trigger trnsition. Chnging irst will not use the output to hnge (it requires hnging lso). In this se, is non-trigger signl nd + is non-trigger trnsition. Inormlly, the si ide here is to onstrut BDD suh tht trigger signls re ordered eore non-trigger signls. Tht is, or every trigger stte or given dynmi input trnsition A è B, the BDD vrile ordering must e suh tht the trigger signls pper in the vrile ordering eore the non-trigger signls. This is ormlized in the ollowing requirement. Deinition (Trigger signl ordering (TSO-) requirement) Given untion, n ordered BDD G or is sid to stisy the Trigger Signl Ordering (TSO-) Requirement or dynmi input trnsition A è B in T i nd only i the ollowing two onditions hold:. For every trigger stte X 2 ëa; Bë, the trigger signl vriles in X pper in the vrile ordering eore the nontrigger signl vriles. 2. For every trigger stte X 2 ëa; Bë with multiple trigger signls, the trigger signl vriles in X ll pper eore eh o the quiesent signl vriles, or ll pper ter eh o the quiesent signl vriles. The BDD G is sid to stisy the TSO-requirement glolly i nd only i its vrile ordering stisies the TSO-requirement or every speiied dynmi input trnsition. The seond ondition ensures tht there is no quiesent signl in etween ny trigger signls during ny speiied trnsition. I strit vrile ordering n e ound tht n stisy the TSO-requirement glolly, then the derived multiplexor network is lso ree o dynmi hzrds. Theorem 2 (Dynmi logi hzrd-reedom) Let C e iruit derived rom BDD G y repling eh node in G with hzrd-ree multiplexor. C is ree o dynmi hzrds or ll speiied dynmi trnsitions, i the TSO-requirement is stisied glolly. Proo: Without loss o generlity we will ssume single speiied dynmi trnsition A è B. The iruit C implements the Boolen untion whih is ree o untion hzrds or the speiied input trnsition A è B. Further the iruit C hs een derived using the synthesis proedure outlined. Assume tht the multiplexor driving the output o C hs s its ontrol vrile. The dt inputs to the multiplexor orrespond to untions nd, the Shnnon otors o with respet to nd. Assume tht is to mke! trnsition, i.e. èaè = nd èbè =.. We will irst onsider the se when the input is t onstnt. Clerly, i is, will e ree o dynmi hzrds i is ree o dynmi hzrds. 2. I is onstnt, will e ree o dynmi hzrds i is ree o dynmi hzrds. 3. Next onsider the se when the input mkes! trnsition orresponding to A è B. () Consider the se when èaè = nd èbè =. We lim tht èaè = èbè =. Suppose èaè =. Then, lerly, èaè 6=. Thereore, èaè =. Suppose èbè =. There exists ue m 2 ëa; Bë suh tht èmè =. Clerly the ue m does not ontin the literl or sine the otor is not dependent on. There re two possiilities. In the irst se èmè =. I there is suh ue, then we hve untion hzrd on, on the pth in the trnsition ue ëa; Bë orresponding to A è æ m è æ m è B, euse èaè =, èæmè=, èæmè=,nd èbè =. The seond se orresponds to èmè =. Consider the pth in the trnsition ue A è æ m è æ m è B. We lim tht is non-trigger signl in stte A. I is trigger signl in stte A, then when goes! so does. This mens tht èaè =. Oviously sine èbè = nd is mking! trnsition, èbè =. Cse elow orresponds to èaè = èbè=. Thereore, in stte A the signl is non-trigger signl. I only
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 4, NO. 8, AUGUST 995 7 single signl, ll it s, hnges rom A to æm,thensis lerly triggersignl in A. We lerly hve violtion o Condition o the TSO-requirement with non-trigger signl eing eore the trigger signl s in the ordering. Multiple signls ould hnge rom A to æ m. Without loss o generlity onsider the se where two signls s nd s 2 hnge rom A to æm. We hve two pths orresponding to s hnging irst nd s 2 hnging irst. Denote these pths A è æ m è æm nd A è æm 2 è æm. I èæm è=(èæm 2 è=) then s (s 2 ) is trigger signl in stte A. Sine is nontrigger signl in stte A we hve violted Condition o the TSO-requirement. Thereore, we require è æ m è = è æ m 2 è =. I is non-trigger signl in either stte æ m or stte æ m 2,thenwe gin hve violtion o Condition o the TSO-requirement, sine s 2 nd s re, respetively, trigger signls in sttes æ m nd æ m 2. Thereore, is trigger signl in oth sttes æ m nd æ m 2. Now, in stte æ m, we hve two trigger signls, nmely nd s 2 nd quiesent signl s. Similrly, in stte æ m 2,wehve two trigger signls, nmely nd s nd quiesent signl s 2. The orderings és és 2 or és 2 és will oth use violtion o Condition 2 o the TSO-requirement. (A quiesent signl ppers in etween two trigger signls.) In ll ses, the ordering requirement imposed in the onstrution o C hs een violted. Thereore èaè = èbè =. Sine is itsel iruit derived rom BDD, y Theorem, is ree o stti hzrds nd will sty t stedy throughout A è B. nnot hve untion hzrds sine tht would imply dynmi untion hzrd in on A è B. () Consider the se when èaè = èbè =. Sine itsel is iruit otined rom BDD, it is ree o stti hzrds y Theorem. Further, i hs untion hzrd on A è B, then would hve untion hzrd. Thereore is untion hzrd-ree on A è B. I is onstnt t, then y the ove rgument would e ree o stti hzrds s well. This mens would e ree o dynmi nd stti hzrds. I mkes! trnsition on A è B then will e dynmi hzrdree i is dynmi hzrd-ree. I either mkes! trnsition or i mkes! trnsition then ollows nd stys t. Thereore in ll ses, i either or is ree o dynmi hzrds in its! trnsition then will e ree o dynmi hzrds. 4. A similr rgument n e mde or the! trnsition on in A è B to show tht is dynmi hzrd-ree i or is dynmi hzrd-ree. For eh o the our possiilities orresponding to in A è B, we re gurnteed tht i t most one o or is ree o dynmi hzrds then so is. We lso know tht in eh se the prtiulr or will e ree o untion hzrds on A è B. Further the trigger signl ordering requirement is glol imposition on C, nd the hngein is used y the prtiulr or orresponding to eh se. Thereore, one n pply the rguments ove t ny level in C. We will inlly reh the primry inputs whih re dynmi hzrd-ree y deinition. Thereore, is dynmi hzrd-ree. The proo or the se when mkes! trnsition ollows similrly. As we hve shown lredy tht BDD implementtion is ree o stti logi hzrds nd is ree o untion hzrds y the prolem deinition, then C derivedusing theoveproedureisully hzrd-ree or ll hzrds under the speiied input trnsitions. Theorem 3 (Complete hzrd-reedom) C is ree o stti nd dynmi hzrds, oth untion nd logil, or ll speiied input trnsitions. Proo: Funtion hzrd-reedom is immedite rom the prolem deinition; stti logi hzrd-reedom is gurnteed y Theorem ; nd dynmi logi hzrd-reedom is gurnteed y Theorem 2. Corollry 2 (Hzrd-reedom under single-input hnges) A BDD-sed iruit C under ny ordering is ree o hzrds under ll single-input hnges. Proo: Funtion hzrd-reedom is immedite rom the prolem deinition; stti logi hzrd-reedom is gurnteed y Theorem ; nd dynmi logi hzrd-reedom under singleinput hnges is gurnteed y Theorem 2 sine no ordering onstrints n exist or single-input hnges. Corollry 3 (Hzrd-reedom under multiple-input dynmi trnsitions) A Ciruit C derived rom BDD G is hzrd-ree to ll multiple-input dynmi trnsitions A è B s long s either 8X 2 èa; Bë, èxè is onstnt or 8X 2 ëa; Bè, èxè is onstnt. Proo: Rell tht èa; Bë orresponds to ëa; Bë, A nd ëa; Bè orresponds to ëa; Bë, B. For oth ses, i.e., 8X 2 èa; Bë èxè is onstnt or 8X 2 ëa; Bè èxè is onstnt, or eh trigger stte we hve only two possiilities: () ll the exited signls in the trigger stte re trigger signls or (2) the single exited signl in trigger stte is trigger signl. Hene, in either se, there re no ordering onstrints on G imposed y Condition o the TSO requirement. In se (), the trigger stte must e A. Hene, there is no quiesent signl. In se (2), there is only single trigger signl nd ll other signls re quiesent. Hene, in either se, there re no ordering onstrints on G imposed y Condition 2 o the TSO requirement. Thereore, dynmi logi hzrd-reedom is gurnteed y Theorem 2. Note tht this orollry shows tht there will no ordering onstrints generted on urst-mode trnsitions. C. Finding Vrile Order We now give systemti proedure or inding vrile ordering, i one exists, tht stisies the TSO-requirement:. Let, = èv;eè e direted grph where the eh vertex v 2 V represents unique vrile, nd eh edge x è y 2 E mens tht signl x must pper eore the signl y in the vrile order (i.e., indexèxè é indexèyè). I there is pth x è, p y in,, then it lso mens x must pper eore y in the vrile order. 2. Initilize, with V s the set o vriles nd E = ;.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 4, NO. 8, AUGUST 995 8 3. For eh dynmiinputtrnsition A è B, dd the ollowing onstrints to stisy ondition o the TSO-requirement (. Deinition ): () For eh trigger stte X 2 ëa; Bë (. Deinition ), determine the set o trigger signls S T nd the set o non-trigger signls S NT. () For eh x 2 S T nd y 2 S NT, dd the direted edge x è y to E. 4. Chek i the grph, is still yli. I yes, proeed; otherwise, ort euse no solution exists. 5. For eh dynmiinputtrnsition A è B, dd the ollowing onstrints to stisy ondition 2 o the TSO-requirement: () For eh trigger stte X 2 ëa; Bë, determine the set o trigger signls S T nd the set o quiesent signls S Q in tht stte. () For eh y 2 S Q, hek i there lredy exists pth p x i è, y rom y to some x i 2 S T in, nd i there lredy exists pth y è, p x j rom some x j 2 S T to y in,. i. I no suh pth exists, then either or ll x k 2 S T,ddthe direted edges x k è y; 8y to E, oror ll x k 2 S T,ddthe direted edges y è x k ; 8y to E. p ii. I there re only pths x i è, y rom some y to some x i 2 S T in,, thenor ll x k 2 S T, dd the direted edges x k è y; 8y to E. p iii. I there re only pths y è, x j rom some x j 2 S T to some y in,, thenor ll x k 2 S T, dd the direted edges y è x k ; 8y to E. iv. Otherwise, ktrk to the most reently mde deision t step (i) nd hnge the set o direted edges dded to E. I ktrking is not possile, then ort euse no solution exists. 6. Find BDD vrile ordering, suh tht 8x è y 2 E : indexèxè é indexèyè. I there hoies selet one ritrrily. 7. Construt the BDD with the hosen vrile ordering. Derive multiplexor network C. Theorem 4 (Strit vrile ordering) A strit vrile ordering n e derived i nd only i n yli grph n e derived. Proo: Neessity: I, ontins yle etween x nd y, it mens we require oth indexèxè é indexèyè nd indexèyè é indexèxè. This is not possile with strit BDD vrile ordering. Suiieny: I, does not ontin yle etween x nd y, it mens either we hve only x è, p y, whih n e stisied y indexèxè é indexèyè, or we hve only y è, p x, whih n e stisied y indexèyè é indexèxè. In essene, the resulting direted yli grph (DAG), represents prtil order. Any strit BDD vrile ordering tht stisies this prtil order n e used. One n e hosen to minimize the resulting BDD size. When n yli grph nnot e ound, then it mens no strit BDD vrile ordering exists. In this se, we n mke use o ree BDD s. This disussion will e deerred to Setion V-E. We now illustrte the ides with n exmple. D. An Exmple To illustrte the ides, we hve n exmple rom Nowik [2] tht ws used to illustrte his two-level minimizer. The Krnugh mp o the exmple is shown in Figure 6. For this exmple, this is set o our speiied input trnsitions T = t ;t 2 ;t 3 ;t 4 g. These trnsitions re: t æ æ è - stti input hnges trnsition +;d,g t 2 æ è - stti input hnges trnsition d+g t 3 æ æ è - dynmi input hnges trnsition,;d+g t 4 æææ è - dynmi input hnges trnsition +;,;d,g d t3 t4 Fig. 6. Another dynmi hzrd exmple. The input trnsitions re indited in Figure 6. The strting point o eh trnsition is desried y dot, nd its trnsition ue is desried y dotted irle. From Theorem, the BDD implementtion is ree o stti hzrds, so trnsitions t nd t 2 will not use prolem. For dynmi trnsitions t 3 nd t 4, we need to nlyze the vrile ordering requirements to gurntee tht the BDD implementtion is dynmi hzrd-ree or these two speiied trnsitions. Indeed, the vrile ordering ééédwill ensure the stistion o the TSO-requirements or dynmi trnsitions t 3 nd t 4. Thereore, the resulting BDD implementtion is lso ree o dynmi hzrds. The BDD is shown in Figure 7. d d Fig. 7. Dynmi hzrd ree BDD implementtion with ordering ééé d. It hs een shown tht it is not lwys possile to produe hzrd-ree two-level SOP over. For exmple, i we dd the t t5 t2
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 4, NO. 8, AUGUST 995 9 ollowing speiied trnsition to the ove exmple (shown in Figure 6), then it n e shown tht no hzrd-ree two-level SOP over exists. The reson why no SOP solution exists is the ollowing: in order to eliminte stti logi hzrds or the stti trnsition t 5 : æ è, the SOP solution must ontin t lest one ue, lled required-ue, tht ontins the trnsition ue,. However, this required-ue onlits with requirements or eliminting dynmi logi hzrds or the dynmi trnsitions t 4 :æææ è. Speiilly, the trnsition ue t5 =, intersets the trnsition ue o t4 = ë; ë,ut it does not ontin the strt stte, whih is dynmi hzrd violtion. See [], [4], [22] or more detils. t 5 æ è - stti input hnges trnsition +g However, with the BDD pproh, the ove BDD implementtion is lso ree o hzrds or this trnsition (sine it is stti trnsition), s well s the other speiied trnsitions. E. Synthesis rom Free BDD s Although in the exmple shown in Setion V-D we n ind vrile ordering tht stisied ll ordering requirements, it is not lwys possile to ind suh strit vrile ordering in the generl se. It is possile to hve yli ordering onstrints tht nnot e stisied using strit vrile ordering. For exmple, it ould e tht in one speiied dynmi input trnsition, x is required to pper eore y; ut in nother speiied dynmi input trnsition, y is required to pper eore x. In this se, we hve yli onstrint. Cyli onstrints n requently e resolved y using ree BDD s where dierent vrile orderings my e used long dierent pths. (Note tht ree BDD still hs the onstrint o vrile ppering t most one long ny pth.) Rell tht eh pth in redued BDD orresponds to ue in disjoint over. In this sense, pth overs seto sttes ontined in the ue. Intuitively, we n derive lol ordering requirements or eh speiied dynmi input trnsition A è B seprtely.thenwederivereebddwherethe ordering onstrints re respeted or eh dynmi input trnsition A è B. The ugmented proedure is s ollows.. For eh speiied dynmi trnsition T i 2 G, otin, Ti èv;eè s desried erlier. 2. Attempt to onstrut glol ordering tht stisies, Ti èv;eè or ll T i 2 G. I this is possile go to Step 7. I this is not possile, identiy onlit tuples x; y; T j ;T k g, where or trnsition T j x ppers eore y, nd or trnsition T k y ppers eore x. (Note tht there my e multiple onlits or the sme pir o vriles x nd y resulting in multiple onlit tuples.) 3. In the trnsition ue ëa i ;B i ëor eh T i ind the set o vriles S i tht re onstnt t or. Cll this ssignment o vlues to S i the ue i. 4. Choose onlit tuple. Given onlit tuple tht reltes T j to T k, hek i j ë k = ç. I so, we ind vrile z in the j nd k ues tht hs dierent vlues nd urther does not pper s y in ny edge x è, p y in, Ti èv;eè. I we nnot ind suh vrile, we nnot resolve the onlit using ree BDD s with the given set o, Ti èv;eè s nd we exit the proedure. 5. We hoose z =, nd group the speiied trnsitions or whih z = in set G. G will ontin T j. Similrly, we group the speiied trnsitions or whih z =in set G. G will ontin T k.izhnges in T i then the T i n e grouped in either set. 6. Go to Step, reurring with G = G z= nd G = G z=. 7. Generte the ordering or G, ororg z= nd G z=. Add z to the top o oth these orderings with the pproprite vlue. Exit the proedure. I the proedure ompletes suessully, we will otin set o orderings o the input vriles eh tgged with n input omintion. For exmple, we my otin or the untion è; ; ; d; eè, the orderings: =;;;d;e =; =;d;;e =; =;e;;d This implies tht in the ree BDD, is the vrile losest to the output. The = input o the root multiplexor is onneted to n ordered BDD with ordering ; ; d; e. The =input is onneted to multiplexor with s its ontrol vrile. The = input is onneted to n ordered BDD with ordering d; ; e nd the =input is onneted to n ordered BDD with ordering e; ; d. To otin iruit C orresponding to the ove ordering, otor the given untion with respet to =nd =. Crete n ordered BDD under the speiied ordering o ; ; d; e or. Cotor with respet to =nd =to otin æ nd æ. Crete ordered BDD s under the speiied ordering or the otors. Theorem 5 (Dynmi logi hzrd-reedom in ree BDD) C is ree o dynmi hzrds or ll speiied dynmi trnsitions. Proo: For ny given input trnsition T i, C does not violte the ordering requirement. Thereore, y Theorem 2 C is dynmi hzrd-ree or T i. VI. REPLACEMENT STRATEGIES AND RESYNTHESIS A. Replement Ciruits It is worthwhile to reple the multiplexors with primitive gtes so non-hzrd-inresing logi trnsormtions (e.g., [3]) n e pplied on the network to urther redue the re or improve the perormne. Eh MUX-ELEMENT = æ + æ in the synthesized iruit C will hve the ollowing onditions t its inputs y Theorem 2.. I the ontrol input is onstnt t, nd n oth hnge! or!. 2. I the ontrol input is onstnt t, nd n oth hnge! or!. 3. I mkes trnsition, we hve t most one o or mking trnsition.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 4, NO. 8, AUGUST 995 We onsider the hrteristis o three primitive gte replement iruits or the MUX-ELEMENT. A: = æ + æ This iruit hs stti logi hzrd on the! trnsition on with nd onstnt t. It is ree o ll dynmi hzrds. B: =è+ èæ +æ This is ree o ll stti hzrds ut hs dynmi hzrds or the se where =, nd nd mke opposite polrity trnsitions. C: = æ +è+ èæ This is ree o ll stti hzrds ut hs dynmi hzrds or the se where =, nd nd mke opposite polrity trnsitions. Our replement strtegy is s ollows: æ I the MUX-ELEMENT hs the onditions ) nd/or 2) t its inputs, ut not 3), we use replement iruit A. æ I the MUX-ELEMENT hs the onditions ) nd/or 3) t its inputs, ut not 2), we use replement iruit B. æ I the MUX-ELEMENT hs the onditions 2) nd/or 3) t its inputs, ut not ), we use replement iruit C. æ I the MUX-ELEMENT hs the onditions ), 2) nd 3) t its inputs, we do not reple it. In the mjority o the ses, the multiplexor iruit n e trnsormed into one onsisting entirely o primitive gtes. The trnsormtion depends on the input onditions t eh multiplexor in the network. Note tht i we re suessul in repling ll multiplexors with the primitive gte implementtion A, then we n onvert the network into disjoint two-level over tht lso stisies the hzrd reedom requirements. However, the two-level network my e onsiderly lrger thn the multiplexor-sed network. B. Constnt Propgtion Sine some o the MUX-ELEMENTs re onneted to onstnt nd vlues, they n e simpliied. This simpliition does not hnge the hzrd hrteristis o the iruit. Ater replement, the primitive gte iruits n e simpliied i they hve onstnt inputs. For exmple the primitive gte iruit simpliies to i is onneted to logil. =è+ èæ +æ = æ C. Hndling Cyli Constrints Using Replement In some ses, when yli ordering onstrints exist tht nnot e stisied even using ree BDD implementtion it my e possile to simpliy ertin multiplexors in the iruit to produe hzrd-ree reliztion. Assume tht the TSO ordering requirement produes yli ordering grph. We disrd miniml numer o onstrints so s to produe n yli ordering grph. In prtiulr, we disrd onstrints generted y Condition 2 o the TSO-requirement. Then, we generte BDD nd multiplexor-sed network using n ordering tht stisies the yli set o onstrints. O A disjoint over is one in whih eh ue in the over does not interset ny other ue. ourse, given tht we hve violted the TSO ordering requirement, the resulting network is not neessrily hzrd-ree. (It is possile tht the resulting network otined under the smller set o onstrints is hzrd-ree euse the TSO-requirement is suiient, nd not neessry, ondition or hzrd reedom.) In some ses, it is possile to simpliy multiplexors to mke the network hzrd-ree. In prtiulr, we hek or the ollowing ses:. A dynmi hzrd is used t multiplexor euse its ontrol input, nd dt inputs nd ll mke! trnsitions. We hek i the logil untions nd re suh tht = è =. I so, we reple the multiplexor = æ + æ with = æ +. This elimintes the dynmi hzrd, sine when goes! the output goes!, nd oth nd hve to go! or the output to go!. 2. A dynmi hzrd is used t multiplexor euse its ontrol input mkes! trnsition, nd dt inputs nd mke! trnsitions. We hek i =è =.Iso, we reple the multiplexor with = + æ. Agin, this elimintes the dynmi hzrd. 3. Sme s Cse exept tht, nd mke! trnsitions. 4. Sme s Cse 2 exept tht mkes! trnsition, nd nd mke! trnsitions. VII. EXPERIMENTAL RESULTS We hve implemented the tehniques desried in this pper nd hve tested them on numer o exmples. The sotwre hs een implemented using the BDD pkge in SIS [23]. We present set o results using enhmrks rom the synhronous design enhmrk set. The results in Tle I orrespond to diret omprison with the two-level hzrd-ree synthesis proedure o [22]. Hzrd-ree two-level nd BDD-sed iruits were synthesized using the speiied set o stti nd dynmi trnsitions or the enhmrk exmples given in [22]. For the BDD-sed iruits, hzrd-ree MUX-ELEMENT requiring our literls ws ssumed. The two-level iruits ontin some very lrge nin gtes, however, we hve reported the literl ounts prior to deomposition (whih would inrese literl ount). Note tht hzrd noninresing trnsormtions n e pplied to oth the BDD-sed nd the two-level iruits improving their re hrteristis. The literl ounts or the BDD-sed reliztions ompre vorly to the two-level reliztions in most exmples. More sustntil improvements over two-level solutions n e otined using the BDD-sed method in sequentil synthesis trjetory suh s tht desried in [29]. The BDD solution hs less restritions on stte ssignment nd stte minimiztion, so etter results n e otined. For instne, ewer stte vriles re required in mny ses, resulting in ewer inputs nd outputs in the hzrd-ree omintionl logi. The interested reder is reerred to [29] or more omprehensive set o results. Our BDD-sed reliztions under ny ordering re gurnteed to e hzrd-ree or ll stti trnsitions y Theorem. However, this is not trueo the two-levelreliztionso Tle I. In order to mke two-level iruit hzrd-ree or stti trn-
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 4, NO. 8, AUGUST 995 TABLE I COMPARISON BETWEEN TWO-LEVEL AND MULTILEVEL REALIZATIONS WHEN HAZARD-FREEDOM IS REQUIRED UNDER A SPECIFIED SET OF MULTIPLE-INPUT STATIC AND DYNAMIC TRANSITIONS. Speiition Totl Sttes / Primry literls Trnsitions In Out 2-level BDD q42 4 4 2 2 27 5 ring-ounter 8 8 2 45 68 inry-ounter 32 32 4 94 7 inry-ounter-o 32 32 5 4 8 pe-send-i 4 5 3 9 88 he-trl 38 49 6 9 74 23 tsend 22 3 7 4 328 5 tsend-m 4 6 4 96 9 isend-m 2 5 6 4 77 88 s 23 33 9 7 99 27 stetson-p 3 38 3 4 376 455 stetson-p2 25 27 8 2 78 95 iu-io2dm 3 5 2 25 9 ioelltrl 3 3 2 2 6 4 ssi-trg-send 7 8 4 2 53 57 ssi-init-send 7 8 4 2 3 43 ssi-init-rv-syn 4 5 3 2 2 sitions, ll the prime implints o the logi untion hve to e inluded in the reliztion. This n result in sustntilly greter numer o literls. By Corollry 2, BDD-sed reliztions (under ny ordering) re hzrd-ree under ll single-input dynmi trnsitions. In order to ensure hzrd-reedom under ll single-input dynmi trnsitions signiint numer o dditionl prime implints hve to e dded to the two-level iruits o Tle I. VIII. CONCLUSIONS In this pper, we hve desried new synthesis method sed on ordered nd ree Binry Deision Digrms or synthesizing hzrd-ree multilevel logi implementtions. Methods or produing hzrd-ree logi implementions hve importnt pplitions in the ield o synhronous design. We hve given utomted synthesis proedures tht n produe iruits tht re ree o oth stti nd dynmi hzrds or given set o multiple-input hnges. The iruits produed using our method remin hzrd-ree under ny ritrry gte or wire delys. Our method is sed on pure dely model ssumption, whih mens we do not need to rely on potentilly slow inertil delys to ilter out unexpeted spurious trnsitions. The method hs een implemented nd its eetiveness hs een shown on numer o exmples. We elieve our rmework is quite generl nd powerul. As indited in Setion VII, it hs een used to hndle the synthesis prolems rising in extended urst-mode synhronous iruits [29]. ACKNOWLEDGEMENTS The uthors would like to thnk Steve Nowik o Columi University nd Peter Vnekergen o Synopsys or numer o very helpul disussions onerning the hzrd-ree synthesis prolem nd or the enhmrk exmples. Thnks to Kenneth Yun nd Alex Kondrtyev or providing detiled nd onstrutive omments, nd helping with the proo o Theorem 5.. Thnks to Ken Yun nd Dve Dill or pointing out the ppliility o BDD-sed networks to extended urst-mode FSMs. REFERENCES [] V. Akell nd G. Goplkrishnn. Shilp: high-level synthesis system or sel-timed iruits. In ICCAD-992. [2] P.A. Beerel nd T. Meng. Automti gte-level synthesis o speedindependent iruits. In ICCAD-992. [3] J. Beister. A uniied pproh to omintionl hzrds. IEEE Trnstions on Computers, C-23(6), 974. [4] J.G. Bredeson. Synthesis o multiple input-hnge hzrd-ree omintionl swithing iruits without eedk. Int. J. Eletronis, 39(6):65 624, 975. [5] J.G. Bredeson nd P.T. Hulin. Elimintion o stti nd dynmi hzrds or multiple input hnges in omintionl swithing iruits. Inormtion nd Control, 2:4 224, 972. [6] E. Brunvnd nd R. F. Sproull. Trnslting onurrent progrms into dely-insensitive iruits. In ICCAD-989. [7] R. E. Brynt. Grph-sed lgorithms or oolen untion mnipultion. IEEE Trnstions on Computers, C-35(8):677 69, August 986. [8] T.-A. Chu. Synthesis o sel-timed VLSI iruits rom grph-theoreti speiitions. Tehnil Report MIT-LCS-TR-393, Msshusetts Institute o Tehnology, 987. [9] O. Coudert nd J.C. Mdre. A uniied rmework or the orml veriition o sequentil iruits. In ICCAD-9, pges 26 29, Novemer 99. [] E.B. Eihelerger. Hzrd detetion in omintionl nd sequentil swithing iruits. IBM J. Res. Develop., 9(2):9 99, 965. [] J. Frkowik. Methoden der nlyse und synthese von hsrdrmen shltnetzen mit minimlen kosten I. Elektronishe Inormtionsverreitung und Kyernetik, (2/3):49 87, 974. [2] A. Kondrtyev, M. Kishinevsky, B. Lin, P. Vnekergen, nd A. Ykovlev. On the onditions or gte-level speed-independene o synhronous iruits. In TAU-993. [3] D.S. Kung. Hzrd-non-inresing gte-level optimiztion lgorithms. In ICCAD-992. [4] L. Lvgno, K. Keutzer, nd A. Sngiovnni-Vinentelli. Algorithms or synthesis o hzrd-ree synhronous iruits. In DAC-9. [5] Alin J. Mrtin. Compiling ommuniting proesses into delyinsensitive VLSI iruits. Distriuted Computing, :226 234, 986. [6] E.J. MCluskey. Introdution to the Theory o Swithing Ciruits. MGrw-Hill, 965. [7] Teres H.-Y. Meng, Roert W. Brodersen, nd Dvid G. Messershmitt. Automti synthesis o synhronous iruits rom high-level speiitions. IEEE Trnstions on CAD, 8():85 25, Novemer 989. [8] C.W. Moon, P.R. Stephn, nd R.K. Bryton. Synthesis o hzrd-ree synhronous iruits rom grphil speiitions. In ICCAD-99. [9] C. Myers nd T. Meng. Synthesis o timed synhronous iruits. In ICCD-992. [2] S. Nowik, 993. Privte ommunition. [2] S.M. Nowik nd D.L. Dill. Automti synthesis o lolly-loked synhronous stte mhines. In ICCAD-99. [22] S.M. Nowik nd D.L. Dill. Ext two-level minimiztion o hzrd-ree logi with multiple-input hnges. In ICCAD-992. [23] E. M. Sentovih, K. J. Singh, C. Moon, H. Svoj, R. K. Bryton, nd A. Sngiovnni-Vinentelli. Sequentil Ciruit Design Using Synthesis nd Optimiztion. In Proeedings o the Int l Conerene on Computer Design: VLSI in Computers nd Proessors, pges 328 333, Otoer 992. [24] H. J. Touti, H. Svoj, B. Lin, R. K. Bryton, nd A. Sngiovnni- Vinentelli. Impliit stte enumertion o inite stte mhines using BDD s. In ICCAD-9, pges 3 33, Novemer 99. [25] S.H. Unger. Asynhronous Sequentil Swithing Ciruits. New York: Wiley-Intersiene, 969. [26] P. Vnekergen, B. Lin, G. Goossens, nd H. De Mn. A generlized stte ssignment theory or trnsormtions on signl trnsition grphs. In ICCAD-992. [27] M.L. Yu nd P.A. Surhmnym. A pth-oriented pproh or reduing hzrds in synhronous designs. In DAC-992. [28] K. Y. Yun nd D. L. Dill. Uniying Asynhronous/Synhronous Stte Mhine Synthesis. In ICCAD-93, pges 255 26, Novemer 993. [29] K. Y. Yun, B. Lin, D. L. Dill, nd S. Devds. Perormne-Driven Synthesis o Asynhronous Controllers. In ICCAD-94, Novemer 994.