Computer Organization I Lecture 13: Design of Combinational Logic Circuits
Overview The optimization of multiple-level circuits Mapping Technology Verification
Objectives To know how to optimize the multiple-level circuits To know how to map circuits with AND, OR, Inverters into circuits with NAND (NOR) gates To understand how to verify the circuits
Multiple-level optimization Multiple-level circuits are circuits that are not twolevel (with or without input and/or output inverters) Multiple-level circuits can have reduced gate input cost compared to two-level (SOP and POS) circuits eg G = ABC + ABD + E + ACF + ADF, after simplification G = A(B+F)(C+D) + E Multiple-level optimization is performed by applying transformations to circuits represented by equations while evaluating cost
Important Transformation Rules Factoring - finding a factored form from SOP or POS expression Decomposition - expression of a function as a set of new functions Substitution of G into F - expression function F as a function of G and some or all of its original variables Elimination - Inverse of substitution
Transformation Examples Algebraic Factoring F = ACD + ABC + ABC + ACD G = 16 Factoring: F = A ( CD + BC ) + A (BC + CD) Factoring again: F = ( AC + AC) (B + D) G = 10 Note: G is the Gate Input Cost without Inverters, it is equal to the number of AND inputs and the number of OR gate inputs
Transformation Examples Decomposition The simplified function: F = ( AC + AC) (B + D) The terms B + D and AC + AC can be defined as new functions E and H respectively, decomposing F: F = E H, E = B + D, and H = AC + AC G = 10 This series of transformations has reduced G from 16 to 10, a substantial savings The resulting circuit has three levels plus input inverters
Transformation Examples Elimination Beginning with a new set of functions: X = B + C Y = A + B Z = A X + C Y G = 10 Eliminating X and Y from Z: Z = A (B + C) + C (A + B) G = 10 Flattening (Converting to SOP expression): Z = AB + AC + AC + BC G = 12 This has increased the cost, but has provided an new SOP expression for two-level optimization
Transformation Examples Two-level Optimization The result of 2-level optimization is: Z = A B + C G = 4 This example illustrates that: Optimization can begin with any set of equations, not just with minterms or a truth table Increasing gate input count G temporarily during a series of transformations can result in a final solution with a smaller G
Extraction Beginning with two functions: E = ABD + ABD Transformation Examples H = BCD + BCD G = 16 Finding a common factor and defining it as a function: F = BD + BD We perform extraction by expressing E and H as the three functions: F = BD + BD, E = AF, H = CF G = 10 The reduced cost G results from the sharing of logic between the two output functions
Mapping Technologies Technology Mapping Mapping AND, OR, NOT To NAND gates Mapping AND, OR, NOT To NOR gates The mapping is accomplished by: Replacing AND and OR symbols, Pushing inverters through circuit fan-out points, and Canceling inverter pairs
1 Replace ANDs and ORs: Technology Mapping - NAND Mapping Algorithm 2 Repeat the following pair of actions until there is at most one inverter between : a A circuit input or driving NAND gate output, and b The attached NAND gate inputs
Technology Mapping - NAND Mapping Example A B C D E (a) F A B C D E 7 8 Y 5 X 1 3 (b) OI 6 2 4 9 F A B 5 7 Y X 5 6 C D F E (c) (d)
1 Replace ANDs and ORs: Technology Mapping - NOR Mapping Algorithm 2 Repeat the following pair of actions until there is at most one inverter between : a A circuit input or driving NOR gate output, and b The attached NOR gate inputs
Technology Mapping - NOR Mapping Example A B A B C D E (a) A B F C D E 1 X (b) 3 2 F C F D E (c)
Verification Verification - show that the final circuit designed implements the original specification Simple specifications are: truth tables Boolean equations To verify if the above result from formulation are the same with the original specification or not, it is critical that the formulation process be flawless for the verification to be valid!
Manual Logic Analysis Verification - Basic Verification Methods Find the truth table or Boolean equations for the final circuit Compare the final circuit truth table with the specified truth table, or Show that the Boolean equations for the final circuit are equal to the specified Boolean equations Simulation Simulate the final circuit and the specified truth table or equations using test input values that fully validate correctness The obvious test for a combinational circuit is application of all possible care input combinations from the specification
Verification Example - Manual Analysis BCD-to-Excess 3 Code Converter Find the SOP Boolean equations from the final circuit Find the truth table from these equations Compare to the formulation truth table Finding the Boolean Equations: T 1 = C + D = C + D A W W = A (T 1 B) = A + B T 1 X = (T 1 B) (B CD ) = B T 1 + B CD Y = C D+ C D = CD + CD B C X D Y Z
Input BCD A B C D Output Excess -3 WXYZ 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 1 1 0 0 0 0 1 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 0 0 0 1 0 1 1 1 0 0 1 1 0 1 1 Verification Example - Manual Analysis Find the circuit truth table from the equations and compare to specification truth table: The tables match!
Summary Multiple Level Optimization Mapping Technology Verification Approach
Thank you Q & A