10.1149/1.3035362 The Electrochemical Society In-Situ Measurement of the Relative Thermal Contributions of Chemical Reactions and Ions During Plasma Etching M.R. Tesauro a, and G. Roche b a Qimonda Dresden GmbH & Co. OHG, D-01099 Dresden, Germany b Greg Roche, KLA-Tencor, SensArray Division, Santa Clara, California 95054, USA Plasma etch behavior is often explained in terms of physical and chemical components: both critically related to surface temperatures generated during plasma etching. In an attempt to measure the chemical etch rate component, a specially prepared, 300mm autonomous temperature sensor wafer was used to simultaneously record dynamic surface temperature during plasma etching of photo resist coated and bare silicon surfaces. Data for N 2 / H 2, Ar / O 2, O 2 and Cl 2 etching chemistries were then compared with measured resist etch rates and RF sensor wafer data. Although insulation of the temperature sensors from the plasma by the 3 micron resist coating prevented calculation of the etch rate chemical component, the capability of this methodology with resist coatings < 500nm was shown. In addition the use of both RF and temperature sensor wafers to quickly identify and correct semiconductor etch process development issues related to isotropic etch non-uniformity was shown. Introduction Classic experimental results by Coburn and Winters clearly demonstrated the possible synergy between purely chemical and purely ion driven removal of materials during plasma etch processing (1). Subsequently much plasma etch behavior has been explained in terms of physical and chemical components, both of which are critically related to the surface temperatures generated during plasma etching. The physical component of ion bombardment generates anisotropic etch conditions and promotes high vertical film removal rates. The same ion bombardment and neutralization also provides much of the thermal energy during plasma etching, and the resulting surface temperature drives chemical reactions per Arrhenius rate of reaction equations. This purely chemical removal provides an isotropic component of the film removal rate which can play a key role (along with deposition) in determining final feature sizes as measured in the direction normal to ion incidence (2). Recent work using a 300mm autonomous temperature measurement sensor wafer in production etch chambers has shown reasonable correlation between surface temperature and bulk film etch rate and critical dimension, for some process conditions (3, 4). However, the relative contributions of the physical and chemical components are not clear. Increasingly stringent requirements for process uniformity in semiconductor fabrication require ever closer control of both physically driven, vertical etch rates and chemically driven isotropic etch rates in order to maintain structure uniformity across the wafer. Etch processes in which a feature s critical dimension (CD) is actively tuned within a feedback or feedback / feed-forward control loop demand special care for 3
temperature sensitive isotropic etch uniformity. This holds true both for process uniformity across the substrate surface as well as differences between like processing tools in a mass production environment. Temperature regulation in etching is commonly realized by controlling the temperature of the substrate mount, or chuck. In more modern etch equipment this is an electrostatic chuck (ESC) where wafers are attached by electrostatic forces. In the chuck, a heat transfer fluid flows through channels at a relatively constant temperature maintained by a chiller / heater and feedback control algorithm. The use of Helium carrier gas improves heat transfer between the chuck and substrate, and changes in He pressure and flow serve as additional temperature control knobs as well as sources of variability (5, 6). Demands for improved uniformity have recently prompted development of various multi-zoned chucks in which process non-uniformity can be compensated by independent temperature control in multiple radial zones (7). This can be accomplished by using separate coolant zones and temperatures, as well as by maintaining different chuck surface temperatures with resistively heated surface zones operated at temperatures above that of the cathode body temperature maintained by coolant flow. Despite the important role of wafer surface temperature in plasma processing it is typically monitored indirectly by measurement of chuck coolant temperature, carrier gas pressure / flow, and / or temperature sensors within the body of the chuck near the surface. Incorporation of additional measurement sensors into plasma etching equipment is difficult due to the severe environment and requirements to avoid process perturbations and defectivity. Fortunately improvements in miniaturization and power storage have more recently made possible autonomous sensor wafers with large numbers of sensors and dynamic temperature data recording capability (8-13). Making use of such autonomous sensor wafers, the dynamic surface temperature during plasma etching was measured in both capacitively coupled (CCP), medium density and inductively coupled (ICP), high-density plasma etch chambers. (The chambers studied are used in advanced semiconductor memory fabrication where measurements are restricted by limited access time due to demands of mass production, and the requirement that such measurements do not adversely affect subsequent manufacturing quality.) In order to directly compare surface temperatures during plasma etch processing with N 2 / H 2, Ar / O 2, O 2 and Cl 2 etching chemistries a silicon covered sensor wafer was specially prepared with one-half of the wafer surface coated by resist while the other half remained bare silicon. This enabled simultaneous collection of dynamic temperature data for both the photo resist and bare silicon surfaces. For chemistries where the etch rate of resist is much larger than silicon such data measure the heating caused by ions as well as additional heating caused by exothermic chemical reactions occurring during plasma etching. For the N 2 / H 2 and Ar / O 2 chemistries a series of temperature measurements were made in the CCP etch chamber in which the process pressure, RF power and center / edge gas flow ratio were systematically varied. Results for Cl 2 and O 2 chemistries in the ICP etch chamber were measured at different pressures, and included temperature data collected during the clearing of the resist material in an O 2 plasma. In order to estimate the impact of ion related energy these process variants were also measured using a new type of autonomous sensor wafer which measures an induced peak-to-peak RF voltage 4
sensitive to the combined effects of both DC bias and ion current (14), and the photo resist etch rate was measured using test wafers coated with the same resist used to prepare the half-coated temperature sensor wafer. Materials and Equipment Experimental Measurements were made on a CCP dielectric etch chamber (300mm, multifrequency RF) and an ICP conductor etch chamber (300mm, 13.5 MHz source / bias powers). Both were in normal mass-production status at the time of measurement, having passed the appropriate regular qualification tests and demonstrating acceptable statistical process control (SPC) behavior. Following each experimental run with either sensor wafers or etch rate measurement wafers a waferless, plasma cleaning process was used which is designed to restore initial chamber conditions for each subsequent run. Etch removal rates (ER) were measured using blanket polysilicon and i-line photo resist films (PFR IX420H). Immediately before ER measurement, 2 resist coated warmup were processed using an ER recipe / plasma clean to ensure consistent results. A KLA-Tencor FX-100 tool was used to measure either 13 or 49 sites across the wafer surface both before and after etching. Product CD measurements were made with an Applied Materials Nano SEM using automatic pattern recognition / measurement. The CD of each structure is an average of multiple line width measurements of the same line. A special recipe measuring 56 sites across the wafer was used for improved spatial resolution of CD non-uniformity patterns. All sites are chosen from the same location within the lithographic exposure field to exclude some sources of lithographic non-uniformity. To compare temperatures during etching of resist coated Si and bare Si, dynamic temperature measurements at 62 sites were collected at 1 Hz with a commercially available Integral wireless sensor wafer (available from KLA Tencor, SensArray Division) with Si cover (see Figure 1, below). The wafer is calibrated using the ITS-90 temperature scale and is traceable to US NIST standards. Figure 1. Cutaway view of the Integral wireless sensor wafer showing temperature sensors, circuitry and electronics located below the Si cover. 5
The Integral sensor wafer was specially prepared for these experiments by spin coating a 3um i-line resist film (again, PFR IX420H) with 2mm wafer edge exclusion using a TEL ACT12 lithography coating track. Acetone solvent and clean-room wipes were then used to manually remove the resist coating from one half of the wafer, producing two sets of sensors, one covered only by the Si cover, and the other covered by the Si cover coated with resist. A smaller subset of sensors located close to the border of the resist covered half was excluded from all data analysis (Figure 2., below). The initially coated resist film was used throughout the experimental runs, becoming progressively thinner as it was eroded during repeated plasma etch exposures. Figure 2. Sensor wafer after resist coat (top left), after resist removal (top right) and the grouping and exclusion of sensors by location (bottom center). Following the completion of all experiments the wafer was allowed to equilibrate in a precision adiabatic bath at 50.0874 C. The temperature was then measured using all sensors for 1305 seconds. The differences between bath temperature and time-averaged individual sensor readings had a mean of -0.1683 C with a range from -0.5959 C to 0.1661 C. These differences were then applied to each sensor as correction factors for all the experimental temperature data, assuming that any offset was linear with respect to temperature and remained constant during the time of the experiment. This correction was necessary due to drift after the initial factory calibration caused by several RF hours of sensor wafer use in harsh plasma environments prior to this set of experiments, and allowed for more accurate calculation of small temperature differences between coated and bare Si wafer areas. To measure ionic contributions to the etch process variants an autonomous, polyimide coated sensor wafer was used (Plasma Volt, available from KLA-Tencor, SensArray Division) which measures an induced peak-to-peak surface voltage on 7 capacitive 6
sensors distributed over the wafer surface as shown in Figure 3 (below). This measurement (referred to in this study as VRF ) is that of a voltage drop across a surface-mounted capacitor, hence it is proportional to the RF current through the wafer, at each sensor location. All sensors on each wafer are calibrated in a vertically-oriented 13.56MHz electric field. The calibration field strength is established utilizing commercially available RF sensors and instruments. Figure 3. Plasma Volt sensor wafer (left) showing locations of the capacitor sensors (two on each radial arm and one in the center) and electronics module (larger, white circle). A schematic of the measurement capacitor in the plasma environment is shown on the right. Measurements for the Trim Etch Case Study (Results and Discussion section, below) were made with a second type of autonomous temperature measuring sensorwafer (PlasmaTemp, available from KLA-Tencor, SensArray Division). This sensor wafer comprises 54 temperature sensors and associated electronics placed on the surface of a standard silicon wafer, all coated with polyimide. As with the Integral wafer, this wafer is calibrated using the ITS-90 temperature scale and is traceable to US NIST standards. Experimental Plan Following the resist coating / selective removal of the temperature sensor wafer a series of different plasma etch processes were characterized sequentially until the resist was completely removed from the wafer surface (see Table I., below). Table I. Experimental Run Summary 1. Coat temperature wafer remove resist from left side 2. CCP Etch: 11 step N 2 / H 2 DOE 3. CCP Etch: 5 single-factor N 2 / H 2 test runs 4. CCP Etch: 5 step N 2 / H 2 screening test 5. CCP Etch: 5 step Ar / O 2 screening test 6. CCP Etch: 2 step N 2 / H 2 & Ar / O 2 higher pressure (200mT) pressure test 7. ICP Etch: 2 step Cl 2 test (5mT, 50mT) 8. ICP Etch: 2 step O 2 test (5mT, 50mT) 50mT to endpoint 7
ER measurements and VRF measurements for each of the processes described in Table I were made shortly after the temperature measurements. Results and Discussion Temperature Measurement and the Chemical Etch Component In order to estimate the chemical etching component of the process variants the temperature measurements for sensor groups on the bare Si and resist coated areas of the wafer were averaged and plotted versus time. An exponential fit was then made in order to extrapolate to steady-state values. This allows a calculation of heat input difference after the method of Hussla, et al. (5), where the wafer temperature (T W ) in the case of active cooling and negligible radiative cooling can be expressed as follows: T W = T H + (Q IN /A)/k 1 [1 exp(-tk 1 /k 0 )] [1] where T H is the temperature of the wafer holder (ESC), Q IN is the power flux in Js -1, A is the area of the wafer (m 2 ), t is the time, k 0 is the product of the density, heat capacity and thickness of the wafer (Jm -2 K -1 ), and k 1 is the conduction coefficient (Jm -2 K -1 ). At steady-state conditions, where T W is a constant (T WSS ), it is possible to solve for Q IN as follows: Q IN = A k 1 (T WSS - T H ) [2] Assuming that there is no difference between resist and bare Si in the heating caused by ion bombardment and recombination, and that the thermal mass of the resist coating is negligible compared to that of the wafer, the calculated difference in heat input between resist and bare surfaces will approximate the heat of exothermic chemical etch removal of resist for processes which have a high ER for resist and a very low ER for Si (e.g. N 2 / H 2 and Ar / O 2 or O 2 etch chemistries). Through the use of an appropriate average C-C bond strength (Jmol -1 ) for the resist material the calculated power flux difference between resist and bare Si wafer halves can be converted into a removal rate of resist in a method similar to the treatment used by Durandet, et al. (15). It should be noted that this methodology is appropriate only for the CCP etch experiments in which a chamber with an ESC at a relatively constant temperature was used. The ICP chamber uses an ESC with an actively heated surface under feedback temperature control in which the conduction coefficient (k 1 ) is variable. Although temperature differences on the wafer halves can still be observed, a convenient solution for Q IN based on the exponential extrapolation to steady-state conditions as described above is not possible. Following the application of the temperature correction factors during the data analysis it was discovered that in all cases but one the average temperature of the resist 8
coated wafer half was lower than that of the bare silicon half as exemplified in Figure 4 (below). This is an unfortunate result of the insulative properties of the 3 um thick resist coating, as shown by the one exception where a higher temperature is measured for resist relative to bare Si for O 2 plasma etch chemistry. N2 / H2 Chemistry: CCP Etch Chamber 44.7 44.6 44.5 Temp (C) 44.4 44.3 44.2 44.1 44.0 43.9 0 20 40 60 Time (s) Resist Bare Si Figure 4. Average temperature plotted versus time showing cooler resist coated half and hotter bare Si half of the temperature sensor wafer during plasma etch with N 2 / H 2 chemistry. The final experimental run with the half-resist coated sensor wafer was made on the ICP chamber using O 2 chemistry (Figure 5). During this run the resist, which was previously thinned by all prior experiments, was finally etched away completely. The resist thickness at the beginning of this final etch to clear run was approximately 550 nm based on the measured resist ER (605 nm min -1 ) and the time to clear / endpoint time (55 s). During this run the resist half maintains a temperature approximately 2 C higher than the bare Si half until the resist film begins to clear from the wafer. At this point the temperatures converge, as expected. Clearing was verified by a corresponding drop in plasma CO emission commensurate with a characteristic RF tuning shift. 9
Figure 5. Average temperature plotted versus time showing hotter resist coated half (filled diamonds) and cooler bare Si half (open squares) of the temperature sensor wafer during plasma etch with O 2 chemistry. Note convergence of the temperature as the resist is cleared, and the temperature effects of feedback controlled ESC temperature initial temperature spiking with plasma strike followed by recovery with visible pulsing of the heating units after resist clears. VRF and the Physical Etching Component During the screening test experiments on the CCP etch chamber 13 MHz RF power was varied at 100, 200 and 300W for Ar / O 2 and N 2 / H 2 chemistries. At each power level the VRF was averaged over a 10 second interval after the plasma ignition spike (shown in Figure 6, below). Both the VRF and ER values increase linearly with increasing RF power (Figure 7, left), and the linear correlation of VRF to ER has an R 2 value of 0.91 for Ar / O 2 and 0.99 for N 2 / H 2. 10
Figure 6. An example of VRF data for two chemistry variations on the CCP etch chamber. Average values were determined following stabilization (after the initial plasma-strike spike ). Similarly the maximum temperature values for both the resist coated and bare Si halves of the temperature sensor wafer were recorded at each RF power level. As expected the maximum step temperature increases with increasing RF power for both resist and bare Si surfaces (Figure 7, right). The insulating effect of the resist coating is also clearly visible in the increasing temperature difference between resist and bare Si surfaces as RF power is increased. CCP, Ar / O2 CCP Ar / O2 VRF (V) 2000 115 1900 110 1800 105 100 1700 95 1600 90 1500 85 1400 80 1300 75 1200 70 50 150 250 350 13 MHz RF Power (W) Etch Rate (nm / min) Step T max (C) 45.6 45.4 45.2 45 44.8 44.6 44.4 50 100 150 200 250 300 350 13 MHz RF Power (W) VRF ER Resist Si Figure 7. Comparison of VRF and ER vs RF Power (left) for Ar / O 2 chemistry in the CCP etch chamber, and average step maximum temperature for three RF power settings for both the resist and bare Si wafer halves (right). Results for N 2 / H 2 are similar, although have lower etch rates coinciding with lower VRF values (as shown in Fig. 6). 11
Case-Study: Isotropic Trim Etch Process The importance of the temperature dependence of the chemical removal rate in current microelectronics plasma processing was underscored by an analysis of a realworld problem using both temperature and VRF sensor wafers. In this Trim process a controlled shrink is made to a lithographically printed pattern, and the reduced feature sizes are then transferred into a hard-mask material for use in subsequent structuring. The isotropic etch component involved in shrinking the mask CD, being a product of chemistries which are largely independent of the directional energy of bombarding ions, is highly dependent on temperature. The Trim process showed an unacceptably large increase in CD non-uniformity after etching (Figure 9). Measurement of temperature and VRF for key process steps revealed that the pattern of CD non-uniformity closely matched that of temperature variation across the wafer, but did not match the pattern of VRF uniformity (Figure 10). In addition a larger CD was observed in areas of lower temperature exactly as expected when the chemical / isotropic etch component providing the shrink in CD is reduced due to lower temperatures. That the temperature non-uniformity did not match the VRF nonuniformity indicated that the root-cause was not heat input non-uniformity from RF driven ion bombardment, but instead non-uniform cooling from the actively heated and temperature feedback controlled surface of the ESC. Figure 9. 56 site CD mapping showing Trim non-uniformity pattern with 7nm CD range. 12
Figure 10. Trim temperature non-uniformity (8C range) pattern across the wafer (left) and VRF non-uniformity pattern across the wafer (right). Note that the highest values for VRF (crescent left of center is highest, top edge is lowest) correspond to the lowest temperature values (dark area in lower, left quadrant). One possible improvement was to raise the ESC cathode body temperature from 20C to a value closer to the surface temperatures used in the process. This reduces the required heat output from the resistive heating elements near the ESC surface, and could then reduce the impact of any non-uniformity arising from these elements. Temperature measurements taken to compare the range at 20, 30 and 40C cathode temperatures showed improved uniformity with higher cathode temperature. Raising the cathode temperature to a value of 35C resulted in an approximately 30% reduction of the CD range, which matched the 30% interpolated temperature range reduction between measurements at 30 and 40C. Figure 11. Temperature non-uniformity (4.3C range) measured at 40C cathode temperature (left) and 56 site CD mapping at 35C showing Trim non-uniformity pattern with 5nm CD range (right). 13
Conclusions A specially prepared autonomous sensor wafer was used for dynamic measurement of the temperature difference caused by exothermic chemical etching of a resist coated portion of the wafer and a bare Si surface which had extremely low etch rate, in order to estimate the chemical etch component for related process variants. Although the scheme was not successful due to the insulator effect of a thick resist coat during tests with a constant temperature ESC, it shows capability proof of concept - for thin resist films. Unfortunately it is difficult to carry out such experiments with thin resist in a production environment, because frequent thin resist coat, experiment and strip cycles would be required to provide good results. The strong correlation of ER to VRF for different RF power levels in both Ar / O 2 and N 2 / O 2 systems demonstrates that ion bombardment plays a dominant role in determining the vertical removal rate of resist. However, in many cases the isotropic chemical etch component, although small, is more important than the vertical / anisotropic etch component in determining critical structural parameters. This was shown in the example of a CD trim etch process where temperature non-uniformity was the primary cause of structure CD non-uniformity. Determining whether this is due to ion bombardment / recombination heating or ESC cooling is critical in order to address such problems effectively and quickly. In such cases the comparison of both VRF and temperature data collected by autonomous sensor wafers can clearly indicate whether the non-uniformity root cause is the power flux into or out of the wafer. Acknowledgments The authors are grateful for the assistance of lithography track Equipment Expert Matthias Voigt of Qimonda Dresden for help in resist coating and preparation of the sensor wafer, and for insightful data analysis and especially helpful conversations with Professor Costas Spanos of the University of California, Berkeley. References 1. J.W. Coburn and H.F. Winters, J. Appl. Phys., 50, 3189 (1979) 2. J. Min, S. Hwang, G. Lee, and S. Moon, J. Vac. Sci. Technol. B, 21(5), 2198 (2003). 3. M.R. Tesauro, R. Koepe, T. Remus; G.A. Roche, P. MacDonald, Plasma Process Development and Control with Real-Time Critical Process Parameter Detection at the Wafer Surface, 54 th Meeting of the AVS October 2007 Seattle WA. 4. M. Klick and M. Berndt, J. Vac. Sci. Technol. B, 24(6), 2509 (2002). 5. Solid State Technology Article 6. I. Hussla, K. Enke, H. Grünwald, G. Lorenz and H. Stoll, J. Phys. D: Appl. Phys., 20 889 (1987). 7. C. Gabriel, J. Vac. Sci. Technol. B, 20(4), 1542 (2002). 8. M. Freed, M. Kruger, C.J. Spanos and K. Poolla, IEEE Transactions on Semiconductor Manufacturing, 14(3), 255 (2001). 14
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