74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function.

Similar documents
Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.

2-input EXCLUSIVE-OR gate

74AHC02; 74AHCT02. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function.

74AHC86; 74AHCT86. Quad 2-input EXCLUSIVE-OR gate. The 74AHC86; 74AHCT86 provides a 2-input exclusive-or function.

2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device.

74AHC14; 74AHCT14. Hex inverting Schmitt trigger

The 74LV08 provides a quad 2-input AND function.

The 74LV32 provides a quad 2-input OR function.

74HC2G34; 74HCT2G34. The 74HC2G34; 74HCT2G34 is a high-speed Si-gate CMOS device. The 74HC2G34; 74HCT2G34 provides two buffers.

XC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger

74AHC125; 74AHCT125. Quad buffer/line driver; 3-state

74HC1G86; 74HCT1G86. 2-input EXCLUSIVE-OR gate. The standard output currents are half those of the 74HC/HCT86.

74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02.

74AHC541; 74AHCT541. Octal buffer/line driver; 3-state. The 74AHC541; 74AHCT541 is a high-speed Si-gate CMOS device.

Octal bus transceiver; 3-state

74AHC244; 74AHCT244. Octal buffer/line driver; 3-state. The 74AHC244; 74AHCT244 is a high-speed Si-gate CMOS device.

74AHC2G126; 74AHCT2G126

74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter

74HC02; 74HCT02. The 74HC02; 74HCT02 provides a quad 2-input NOR function.

74AHC1G00; 74AHCT1G00

The 74LVC1G02 provides the single 2-input NOR function.

The 74LVC1G11 provides a single 3-input AND gate.

74AHC1G14; 74AHCT1G14

Dual 2-to-4 line decoder/demultiplexer

74LV General description. 2. Features. 8-bit addressable latch

Temperature range Name Description Version 74LVC74AD 40 C to +125 C SO14 plastic small outline package; 14 leads;

74HC238; 74HCT to-8 line decoder/demultiplexer

74LVT125; 74LVTH General description. 2. Features. 3. Quick reference data. 3.3 V quad buffer; 3-state

74HC3G14; 74HCT3G14. Triple inverting Schmitt trigger. The 74HC3G14; 74HCT3G14 is a high-speed Si-gate CMOS device.

74AHC259; 74AHCT259. The 74AHC259; 74AHCT259 has four modes of operation:

Dual 3-channel analog multiplexer/demultiplexer with supplementary switches

74AHC373; 74AHCT373. Octal D-type transparant latch; 3-state

74LVU General description. 2. Features. 3. Applications. Hex inverter

HEF4028B. 1. General description. 2. Features. 3. Applications. 4. Ordering information. BCD to decimal decoder

Hex inverter with open-drain outputs

The 74LVC10A provides three 3-input NAND functions.

74HC154; 74HCT to-16 line decoder/demultiplexer

Dual buffer/line driver; 3-state

Octal D-type transparent latch; 3-state

74HC1G125; 74HCT1G125

The 74HC21 provide the 4-input AND function.

74HC2G08-Q100; 74HCT2G08-Q100

74HC30-Q100; 74HCT30-Q100

74HC32-Q100; 74HCT32-Q100

74LVC07A-Q100. Hex buffer with open-drain outputs

74AHC30-Q100; 74AHCT30-Q100

74AHC14-Q100; 74AHCT14-Q100

8-bit binary counter with output register; 3-state

74ALVC04. 1 General description. 2 Features and benefits. 3 Ordering information. Hex inverter

74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate

74HC4050-Q100. Hex non-inverting HIGH-to-LOW level shifter

74LV General description. 2. Features. 3. Applications. 8-bit serial-in/serial-out or parallel-out shift register; 3-state

Dual buffer/line driver; 3-state

74LVC125A. 1. General description. 2. Features and benefits. Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

74AUP1G04-Q100. The 74AUP1G04-Q100 provides the single inverting buffer.

Hex inverting Schmitt trigger with 5 V tolerant input

Dual JK flip-flop with reset; negative-edge trigger

The 74LV08 provides a quad 2-input AND function.

74LVC General description. 2. Features and benefits. Ordering information. Octal D-type flip-flop with data enable; positive-edge trigger

74LVC32A. 1. General description. 2. Features and benefits. 3. Ordering information. Quad 2-input OR gate

74LVC General description. 2. Features and benefits. 3. Ordering information. Triple 3-input OR gate. The 74LVC332 is a triple 3-input OR gate.

74HC244; 74HCT244. Octal buffer/line driver; 3-state

74HC08-Q100; 74HCT08-Q100

74HC03-Q100; 74HCT03-Q100

74HC2G16; 74HCT2G16. The 74HC2G16; 74HCT2G16 is a high-speed Si-gate CMOS device. The 74HC2G16; 74HCT2G16 provides two buffers.

Octal buffer/line driver with 5 V tolerant inputs/outputs; 3-state

74AHC541-Q100; 74AHCT541-Q100

74HC1G02-Q100; 74HCT1G02-Q100

74HC00; 74HCT00. The 74HC00; 74HCT00 provides a quad 2-input NAND function.

74HC4017; 74HCT4017. Johnson decade counter with 10 decoded outputs

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate

8-bit binary counter with output register; 3-state

74HC1G32-Q100; 74HCT1G32-Q100

74HC273; 74HCT273. Octal D-type flip-flop with reset; positive-edge trigger

74HC123; 74HCT123. Dual retriggerable monostable multivibrator with reset

2-input single supply translating NAND gate

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate

74HC123; 74HCT123. Dual retriggerable monostable multivibrator with reset

74HC1G08; 74HCT1G08. 1 General description. 2 Features. 3 Ordering information. 2-input AND gate

74HC86; 74HCT86. Quad 2-input EXCLUSIVE-OR gate. The 74HC86; 74HCT86 provides a 2-input EXCLUSIVE-OR function.

74LVC126A. 1. General description. 2. Features and benefits. 3. Ordering information. Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

8-channel analog multiplexer/demultiplexer with injection-current effect control

74HC245; 74HCT245. Octal bus tranceiver; 3-state. The 74HC245; 74HCT245 is similar to the 74HC640; 74HCT640 but has true (non-inverting) outputs.

Single supply translating buffer/line driver; 3-state

74HC2G02; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. 4. Marking. Dual 2-input NOR gate

74AHC123A; 74AHCT123A

5-stage Johnson decade counter

74LVC273-Q100. Octal D-type flip-flop with reset; positive-edge trigger

Low-power 3-input EXCLUSIVE-OR gate. The 74AUP1G386 provides a single 3-input EXCLUSIVE-OR gate.

74LVC541A-Q100. Octal buffer/line driver with 5 V tolerant inputs/outputs; 3-state

74LVC14A-Q100. Hex inverting Schmitt trigger with 5 V tolerant input

Low-power buffer with voltage-level translator

The 74LVC00A provides four 2-input NAND gates.

74HC08; 74HCT General description. 2. Features and benefits. 3. Ordering information. Quad 2-input AND gate

74HC3G04; 74HCT3G General description. 2. Features and benefits. 3. Ordering information. 4. Marking. Triple inverter

Triple inverting Schmitt trigger

74HC4002; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NOR gate

Transcription:

Rev. 0 30 June 2009 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard JESD7-. The provide the quad 2-input ND function. Balanced propagation delays ll inputs have a Schmitt-trigger action Inputs accepts voltages higher than V CC Input levels: The 74VHC08 operates with CMOS logic levels The 74VHCT08 operates with TTL logic levels ESD protection: HBM JESD22-4E exceeds 2000 V MM JESD22-5- exceeds 200 V CDM JESD22-C0C exceeds 000 V Multiple package options Specified from 40 C to +85 C and from 40 C to +25 C Table. Ordering information Type number Package Temperature range Name Description Version 74VHC08D 40 C to +25 C SO4 plastic small outline package; 4 leads; SOT08-74VHCT08D 74VHC08PW 40 C to +25 C TSSOP4 body width 3.9 mm plastic thin shrink small outline package; 4 leads; SOT402-74VHCT08PW 74VHC08BQ 40 C to +25 C DHVQFN4 body width 4.4 mm plastic dual in-line compatible thermal enhanced very SOT762-74VHCT08BQ thin quad flat package; no leads; 4 terminals; body 2.5 3 0.85 mm

4. Functional diagram 2 & 3 2 4 5 B 2 2B Y 2Y 3 6 4 5 & 6 9 0 2 3 3 3B 4 4B 3Y 4Y mna222 8 9 0 2 3 & & 8 B Y mna22 mna223 Fig. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5. Pinning 74VHC08 74VHCT08 74VHC08 74VHCT08 4 V CC terminal index area VCC B 2 3 4B B 4 2 3 4B Y 3 2 4 Y 3 2 4 2 2B 2Y 4 5 6 0 9 4Y 3B 3 2 4 4Y 2B 5 GND () 0 3B 2Y 6 9 3 7 8 GND 7 8 3Y GND 3Y 00aak04 00aak040 Transparent top view () The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration SO4 and TSSOP4 Fig 5. Pin configuration DHVQFN4 Product data sheet Rev. 0 30 June 2009 2 of 4

5.2 Pin description Table 2. Pin description Symbol Pin Description data input B 2 data input Y 3 data output 2 4 data input 2B 5 data input 2Y 6 data output GND 7 ground (0 V) 3Y 8 data output 3 9 data input 3B 0 data input 4Y data output 4 2 data input 4B 3 data input V CC 4 supply voltage 6. Functional description Table 3. Function selection [] Input Output n nb ny L X L X L L H H H [] H = HIGH voltage level; L = LOW voltage level; X = don t care 7. Limiting values Table 4. Limiting values In accordance with the bsolute Maximum Rating System (IEC 6034). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage 0.5 +7.0 V V I input voltage 0.5 +7.0 V I IK input clamping current V I < 0.5 V [] 20 - m I OK output clamping current V O < 0.5 V or V O >V CC + 0.5 V [] - ±20 m I O output current V O = 0.5 V to (V CC + 0.5 V) - ±25 m I CC supply current - 75 m I GND ground current 75 - m T stg storage temperature 65 +50 C Product data sheet Rev. 0 30 June 2009 3 of 4

Table 4. Limiting values continued In accordance with the bsolute Maximum Rating System (IEC 6034). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit P tot total power dissipation T amb = 40 C to +25 C SO4 package [2] - 500 mw TSSOP4 package [3] - 500 mw DHVQFN4 package [4] - 500 mw [] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] P tot derates linearly with 8 mw/k above 70 C. [3] P tot derates linearly with 5.5 mw/k above 60 C. [4] P tot derates linearly with 4.5 mw/k above 60 C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74VHC08 74VHCT08 Unit Min Typ Max Min Typ Max V CC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V V I input voltage 0-5.5 0-5.5 V V O output voltage 0 - V CC 0 - V CC V T amb ambient temperature 40 +25 +25 40 +25 +25 C t/ V input transition rise V CC = 3.3 V ± 0.3 V - - 00 - - - ns/v and fall rate V CC = 5.0 V ± 0.5 V - - 20 - - 20 ns/v 9. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +25 C Unit Min Typ Max Min Max Min Max For type 74VHC08 V IH HIGH-level V CC = 2.0 V.5 - -.5 -.5 - V input voltage V CC = 3.0 V 2. - - 2. - 2. - V V CC = 5.5 V 3.85 - - 3.85-3.85 - V V IL LOW-level V CC = 2.0 V - - 0.5-0.5-0.5 V input voltage V CC = 3.0 V - - 0.9-0.9-0.9 V V CC = 5.5 V - -.65 -.65 -.65 V V OH HIGH-level output voltage V I = V IH or V IL I O = 50 µ; V CC = 2.0 V.9 2.0 -.9 -.9 - V I O = 50 µ; V CC = 3.0 V 2.9 3.0-2.9-2.9 - V I O = 50 µ; V CC = 4.5 V 4.4 4.5-4.4-4.4 - V I O = 4.0 m; V CC = 3.0 V 2.58 - - 2.48-2.4 - V I O = 8.0 m; V CC = 4.5 V 3.94 - - 3.8-3.7 - V Product data sheet Rev. 0 30 June 2009 4 of 4

Table 6. Static characteristics continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +25 C Unit Min Typ Max Min Max Min Max V OL I I LOW-level output voltage input leakage current V I = V IH or V IL I O = 50 µ; V CC = 2.0 V - 0 0. - 0. - 0. V I O = 50 µ; V CC = 3.0 V - 0 0. - 0. - 0. V I O = 50 µ; V CC = 4.5 V - 0 0. - 0. - 0. V I O = 4.0 m; V CC = 3.0 V - - 0.36-0.44-0.55 V I O = 8.0 m; V CC = 4.5 V - - 0.36-0.44-0.55 V V I = 5.5 V or GND; - - 0. -.0-2.0 µ V CC = 0 V to 5.5 V I CC supply current V I =V CC or GND; I O = 0 ; - - 2.0-20 - 40 µ V CC = 5.5 V C I input capacitance - 3.0 0-0 - 0 pf For type 74VHCT08 V IH HIGH-level V CC = 4.5 V to 5.5 V 2.0 - - 2.0-2.0 - V input voltage V IL LOW-level V CC = 4.5 V to 5.5 V - - 0.8-0.8-0.8 V input voltage V OH HIGH-level output voltage V I = V IH or V IL ; V CC = 4.5 V I O = 50 µ 4.4 4.5-4.4-4.4 - V I O = 8.0 m 3.94 - - 3.8-3.7 - V V OL LOW-level output voltage V I = V IH or V IL ; V CC = 4.5 V I O = 50 µ - 0 0. - 0. - 0. V I O = 8.0 m - - 0.36-0.44-0.55 V I I input leakage current V I = 5.5 V or GND; V CC = 0 V to 5.5 V I CC supply current V I =V CC or GND; I O = 0 ; V CC = 5.5 V I CC C I additional supply current input capacitance per input pin; V I =V CC 2. V; I O = 0 ; other pins at V CC or GND; V CC = 4.5 V to 5.5 V - - 0. -.0-2.0 µ - - 2.0-20 - 40 µ - -.35 -.5 -.5 m - 3.0 0-0 - 0 pf Product data sheet Rev. 0 30 June 2009 5 of 4

0. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure 7. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +25 C Unit Min Typ [] Max Min Max Min Max For type 74VHC08 t pd propagation n, nb to ny; see Figure 6 [2] delay V CC = 3.0 V to 3.6 V C L = 5 pf - 4.0 8.8.0 0.5.0.0 ns C L = 50 pf - 5.6 2.3.0 4.0 5.5 ns V CC = 4.5 V to 5.5 V C L = 5 pf - 3.0 5.9.0 7.0.0 7.5 ns C L = 50 pf 4.2 7.9.0 9.0.0 0.0 ns C PD power dissipation capacitance C L = 50 pf; f i = MHz; V I = GND to V CC [3] - 0.0 - - - - - pf For type 74VHCT08 t pd propagation n, nb to ny; see Figure 6 [2] delay V CC = 4.5 V to 5.5 V C L = 5 pf - 3.2 6.9.0 8.0.0 9.0 ns C L = 50 pf - 4.2 7.9.0 9.0.0 0.0 ns C PD power dissipation capacitance [] Typical values are measured at nominal supply voltage (V CC = 3.3 V and V CC = 5.0 V). [2] t pd is the same as t PLH and t PHL. [3] C PD is used to determine the dynamic power dissipation (P D in µw). P D =C PD V CC 2 f i N+Σ(C L V CC 2 f o ) where: f i = input frequency in MHz, f o = output frequency in MHz C L = output load capacitance in pf V CC = supply voltage in Volts C L = 50 pf; f i = MHz; V I = GND to V CC N = number of inputs switching Σ(C L V 2 CC f o ) = sum of the outputs. [3] - 2.0 - - - - - pf Product data sheet Rev. 0 30 June 2009 6 of 4

. Waveforms V I n, nb input GND t PHL t PLH V OH ny output V OL mna224 Fig 6. Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. The input (n, nb) to output (ny) propagation delays Table 8. Measurement points Type Input Output 74VHC08 0.5V CC 0.5V CC 74VHCT08.5 V 0.5V CC Product data sheet Rev. 0 30 June 2009 7 of 4

V I negative pulse 0 V 90 % 0 % t W t f t r t r t f V I positive pulse 0 V 0 % 90 % t W V CC V CC G VI DUT VO RL S open RT CL 00aad983 Fig 7. Test data is given in Table 9. Definitions test circuit: R T = Termination resistance should be equal to output impedance Z o of the pulse generator. C L = Load capacitance including jig and probe capacitance. R L = Load resistance. S = Test selection switch. Load circuit for switching times Table 9. Test data Type Input Load S position V I t r, t f C L R L t PHL, t PLH t PZH, t PHZ t PZL, t PLZ 74VHC08 V CC 3.0 ns 5 pf, 50 pf kω open GND V CC 74VHCT08 3.0 V 3.0 ns 5 pf, 50 pf kω open GND V CC Product data sheet Rev. 0 30 June 2009 8 of 4

2. Package outline SO4: plastic small outline package; 4 leads; body width 3.9 mm SOT08- D E X c y H E v M Z 4 8 Q pin index 2 ( ) 3 θ L p 7 L e b p w M detail X 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max. 0.25.75 0.0 0.069 0.00 0.004 2 3 b p c D () E () e H () E L L p Q v w y Z.45.25 0.057 0.049 0.25 0.0 0.49 0.36 0.09 0.04 0.25 0.9 0.000 0.0075 8.75 8.55 0.35 0.34 4.0 3.8 0.6 0.5.27 6.2 5.8 0.244 0.228 Note. Plastic or metal protrusions of 0.5 mm (0.006 inch) maximum per side are not included. 0.05.05 0.04.0 0.4 0.039 0.06 0.7 0.6 0.028 0.024 0.25 0.25 0. 0.0 0.0 0.004 θ 0.7 0.3 o 8 o 0.028 0 0.02 OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT08-076E06 MS-02 99-2-27 03-02-9 Fig 8. Package outline SOT08- (SO4) Product data sheet Rev. 0 30 June 2009 9 of 4

TSSOP4: plastic thin shrink small outline package; 4 leads; body width 4.4 mm SOT402- D E X c y H E v M Z 4 8 pin index 2 Q ( ) 3 θ 7 e b p w M detail X L p L 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT 2 3 b p c D () E (2) e H () E L L p Q v w y Z max. mm. 0.5 0.05 0.95 0.80 0.25 0.30 0.9 0.2 0. 5. 4.9 4.5 4.3 0.65 6.6 6.2 0.75 0.50 0.4 0.3 0.2 0.3 0. 0.72 0.38 θ o 8 o 0 Notes. Plastic or metal protrusions of 0.5 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT402- MO-53 EUROPEN PROJECTION ISSUE DTE 99-2-27 03-02-8 Fig 9. Package outline SOT402- (TSSOP4) Product data sheet Rev. 0 30 June 2009 0 of 4

DHVQFN4: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 4 terminals; body 2.5 x 3 x 0.85 mm SOT762- D B E c terminal index area detail X terminal index area e e b 2 6 v M w M C C B y C C y L 7 E h e 4 8 3 9 D h X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT () max. b c D () D h E () E h e e L v w y y mm 0.05 0.00 0.30 0.8 0.2 3. 2.9.65.35 2.6 2.4.5 0.85 0.5 2 0.5 0.3 0. 0.05 0.05 0. Note. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT762- - - - MO-24 - - - EUROPEN PROJECTION ISSUE DTE 02-0-7 03-0-27 Fig 0. Package outline SOT762- (DHVQFN4) Product data sheet Rev. 0 30 June 2009 of 4

3. bbreviations Table 0. cronym CMOS LSTTL ESD HBM MM CDM TTL bbreviations Description Complementary Metal Oxide Semiconductor Low-power Schottky Transistor-Transistor Logic ElectroStatic Discharge Human Body Model Machine Model Charged Device Model Transistor-Transistor Logic 4. Revision history Table. Revision history Document ID Release date Data sheet status Change notice Supersedes 20090630 Product data sheet - - Product data sheet Rev. 0 30 June 2009 2 of 4

5. Legal information 5. Data sheet status Document status [][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 5.2 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 5.3 Disclaimers General Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use Nexperia products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia accepts no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IEC 6034) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by Nexperia. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 5.4 Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 6. Contact information For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Product data sheet Rev. 0 30 June 2009 3 of 4

7. Contents General description...................... 2 Features............................... 3 Ordering information..................... 4 Functional diagram...................... 2 5 Pinning information...................... 2 5. Pinning............................... 2 5.2 Pin description......................... 3 6 Functional description................... 3 7 Limiting values.......................... 3 8 Recommended operating conditions........ 4 9 Static characteristics..................... 4 0 Dynamic characteristics.................. 6 Waveforms............................. 7 2 Package outline......................... 9 3 bbreviations.......................... 2 4 Revision history........................ 2 5 Legal information....................... 3 5. Data sheet status...................... 3 5.2 Definitions............................ 3 5.3 Disclaimers........................... 3 5.4 Trademarks........................... 3 6 Contact information..................... 3 7 Contents.............................. 4 For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 30 June 2009