In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

Similar documents
INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download:


74LV373 Octal D-type transparent latch (3-State)

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

74HC4051; 74HCT channel analog multiplexer/demultiplexer

74HC4053; 74HCT4053. Triple 2-channel analog multiplexer/demultiplexer

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.


INTEGRATED CIRCUITS. For a complete data sheet, please also download:

74LVC573 Octal D-type transparent latch (3-State)

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

74LVC823A 9-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

8-channel analog multiplexer/demultiplexer. For operation as a digital multiplexer/demultiplexer, V EE is connected to V SS (typically ground).

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

74HC4067; 74HCT channel analog multiplexer/demultiplexer

74HC General description. 2. Features. 3-to-8 line decoder, demultiplexer with address latches; inverting

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

DATA SHEET. HEF4067B MSI 16-channel analogue multiplexer/demultiplexer. For a complete data sheet, please also download: INTEGRATED CIRCUITS

74HC General description. 2. Features. 3-to-8 line decoder, demultiplexer with address latches; inverting. Product data sheet

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. 74LV259 8-bit addressable latch. Product specification Supersedes data of 1997 Jun 06 IC24 Data Handbook.

INTEGRATED CIRCUITS. 74LV00 Quad 2-input NAND gate. Product specification Supersedes data of 1998 Apr 13 IC24 Data Handbook.

The 74HC21 provide the 4-input AND function.

INTEGRATED CIRCUITS. 74LV688 8-bit magnitude comparator. Product specification Supersedes data of 1997 May 15 IC24 Data Handbook.


INTEGRATED CIRCUITS. 74LV273 Octal D-type flip-flop with reset; positive-edge trigger. Product specification 1997 Apr 07 IC24 Data Handbook

INTEGRATED CIRCUITS. 74LV stage binary ripple counter. Product specification 1998 Jun 23 IC24 Data Handbook

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

74LVC574A Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State)

74LV74 Dual D-type flip-flop with set and reset; positive-edge trigger

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

INTEGRATED CIRCUITS. 74LVC138A 3-to-8 line decoder/demultiplexer; inverting. Product specification 1998 Apr 28

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

Octal buffer/line driver (3-State)

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

Dual 3-channel analog multiplexer/demultiplexer with supplementary switches

74LV393 Dual 4-bit binary ripple counter

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

8-bit binary counter with output register; 3-state

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

74HC4051-Q100; 74HCT4051-Q100

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device.

74HC573; 74HCT573. Octal D-type transparent latch; 3-state. The 74HC573; 74HCT573 is functionally identical to:

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

74HC4051; 74HCT channel analog multiplexer/demultiplexer

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

2-input EXCLUSIVE-OR gate

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

Hex inverting Schmitt trigger with 5 V tolerant input

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

Quad bus transceiver; 3-state. The output enable inputs (OEA and OEB) can be used to isolate the buses.

Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.

Transcription:

Imptant notice Dear Customer, On 7 February 217 the fmer NP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, ogic and PowerMOS semiconducts with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NP Philips Semiconducts references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ http://www.semiconducts.philips.com/, use http://www.nexperia.com Instead of sales.addresses@www.nxp.com sales.addresses@www.semiconducts.philips.com, use salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page elsewhere in the document, depending on the version, as shown below: - NP N.V. (year). All rights reserved Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail telephone (details via salesaddresses@nexperia.com). Thank you f your cooperation and understanding, Kind regards, Team Nexperia

INTEGRATED CIRCUITS DATA SEET F a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Infmation The IC6 74C/CT/CU/CMOS ogic Package Outlines 74C/CT431 8-channel analog multiplexer/demultiplexer File under Integrated Circuits, IC6 December 199

8-channel analog multiplexer/demultiplexer 74C/CT431 FEATURES Wide analog input voltage range: ± V ow ON resistance: 8 (typ.) at = V 7 (typ.) at = 6. V 6 (typ.) at = 9. V ogic level translation: to enable V logic to communicate with ± V analog signals Typical break befe make built in Address latches provided Output capability: non-standard I CC categy: MSI GENERA DESCRIPTION The 74C/CT431 are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no. 7A. The 74C/CT431 are 8-channel analog multiplexers/demultiplexers with three select inputs (S to S 2 ), two enable inputs (E 1 and E 2 ), a latch enable input (E), eight independent inputs/outputs (Y to Y 7 ) and a common input/output (Z). With E 1 OW and E 2 is IG, one of the eight switches is selected (low impedance ON-state) by S to S 2. The data at the select inputs may be latched by using the active OW latch enable input (E). When E is IG the latch is transparent. When either of the two enable inputs, E 1 (active OW) and E 2 (active IG), is inactive, all 8 analog switches are turned off. and GND are the supply voltage pins f the digital control inputs (S to S 2, E, E 1 and E 2 ). The to GND ranges are 2. to 1. V f C and to. V f CT. The analog inputs/outputs (Y to Y 7, and Z) can swing between as a positive limit and as a negative limit. may not exceed 1. V. F operation as a digital multiplexer/demultiplexer, is connected to GND (typically ground). QUICK REFERENCE DATA = GND = V; T amb =2 C; t r =t f = 6 ns TYPICA SYMBO PARAMETER CONDITIONS C CT UNIT t PZ / t PZ turn ON time E 1, E 2 S n to V os C = 1 pf; R =1 k; = V 27 3 ns t PZ / t PZ turn OFF time E 1, E 2 S n to V os 21 23 ns C I input capacitance 3. 3. pf C PD power dissipation capacitance per switch notes 1 and 2 2 2 pf C S max. switch capacitance independent (Y) pf common (Z) 2 2 pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i + {(C + C ) S V 2 CC f o } where: f i = input frequency in Mz f o = output frequency in Mz C = output load capacitance in pf C S = max. switch capacitance in pf {(C + C ) S V 2 CC f o } = sum of outputs = supply voltage in V 2. F C the condition is V I = GND to F CT the condition is V I = GND to 1. V ORDERING INFORMATION See 74C/CT/CU/CMOS ogic Package Infmation. December 199 2

74C/CT431 PIN DESCRIPTION PIN NO. SYMBO NAME AND FUNCTION 4 Z common 3, 14 n.c. not connected 7 E 1 enable input (active OW) 8 E 2 enable input (active IG) 9 negative supply voltage 1 GND ground ( V) 11 E latch enable input (active OW) 1, 13, 12 S to S 2 select inputs 17, 18, 19, 16, 1, 6, 2, Y to Y 7 independent inputs/outputs 2 positive supply voltage Fig.1 Pin configuration. Fig.2 Fig.3 IEC logic symbol. December 199 3

74C/CT431 FUNCTION TABE INPUTS E 1 E 2 E S 2 S 1 S CANNE ON none none Y Y 1 Y 2 Y 3 Y 4 Y Y 6 Y 7 (1) (2) Notes 1. ast selected channel ON. 2. Selected channels latched. 3. = IG voltage level = OW voltage level = don t care = IG-to-OW E transition APPICATIONS Analog multiplexing and demultiplexing Digital multiplexing and demultiplexing Signal gating Fig.4 Functional diagram. Fig. Schematic diagram (one switch). December 199 4

74C/CT431 RATINGS imiting values in accdance with the Absolute Maximum System (IEC 134) Voltages are referenced to = GND (ground = V) SYMBO PARAMETER MIN. MA. UNIT CONDITIONS DC supply voltage. +11. V ±I IK DC digital input diode current 2 ma f V I <. V V I > +. V ±I SK DC switch diode current 2 ma f V S <. V V S > +. V ±I S DC switch current 2 ma f. V < V S < +. V ±I EE DC current 2 ma ±I CC; ±I GND DC GND current ma T stg stage temperature range 6 +1 C P tot power dissipation per package f temperature range: 4 to +12 C 74C/CT plastic DI 7 mw above +7 C: derate linearly with 12 mw/k plastic mini-pack (SO) mw above +7 C: derate linearly with 8 mw/k P S power dissipation per switch 1 mw Note to ratings 1. To avoid drawing current out of terminal Z, when switch current flows in terminals Y n, the voltage drop across the bidirectional switch must not exceed.4 V. If the switch current flows into terminal Z, no current will flow out of terminals Y n. In this case there is no limit f the voltage drop across the switch, but the voltages at Y n and Z may not exceed. RECOMMENDED OPERATING CONDITIONS SYMBO PARAMETER 74C 74CT min. typ. max. min. typ. max. UNIT CONDITIONS DC supply voltage GND 2.. 1... V see Figs 6 and 7 DC supply voltage 2.. 1. 2.. 1. V see Figs 6 and 7 V I DC input voltage range GND GND V V S DC switch voltage range V T amb operating ambient temperature range 4 +8 4 +8 C see DC and AC T amb operating ambient temperature range 4 +12 4 +12 C CARACTERISTICS t r, t f input rise and fall times 1 = 2. V 6. V 6. ns CC = V 4 = 6. V 2 = 1. V December 199

74C/CT431 1 handbook, halfpage - GND 8 MBA334 6 operating area 4 2 2 4 6 8 1 - Fig.6 Guaranteed operating area as a function of the supply voltages f 74C431. Fig.7 Guaranteed operating area as a function of the supply voltages f 74CT431. DC CARACTERISTICS FOR 74C/CT F 74C: GND = 2.,, 6. and 9. V F 74CT: GND = and. V; = 2.,, 6. and 9. V T amb ( C) TEST CONDITIONS 74C/CT SYMBO PARAMETER +2 4 to +8 4 to +12 UNIT I S (µa) V is V I min. typ. max. min. max. min. max. R ON R ON R ON R ON ON resistance (rail) ON resistance (rail) ON resistance (rail) maximum ON resistance between any two channels 1 9 7 1 8 7 6 1 9 8 6 9 8 6 18 16 13 14 12 1 16 14 12 22 2 16 17 1 13 2 17 1 27 24 19 21 18 16 24 21 18 2. 6. 2. 6. 2. 6. 2. 6. 1 1 1 1 1 1 1 1 1 1 1 1 to to V IN V I V I V I V I V I V I V I Notes to DC characteristics 1. At supply voltages ( ) approaching 2. V, the analog switch ON-resistance becomes extremely non-linear. There it is recommended that these devices be used to transmit digital signals only, when using these supply voltages. 2. F test circuit measuring R ON see Fig.8. December 199 6

74C/CT431 DC CARACTERISTICS FOR 74C Voltages are referenced to GND (ground = V) T amb ( C) TEST CONDITIONS SYMBO PARAMETER 74C +2 4 to +8 4 to +12 min. typ. max. min. max. min. max. UNIT V I OTER V I IG level input voltage 1. 3.1 4.2 6.3 1.2 2.4 3.2 4.7 1. 3.1 4.2 6.3 1. 3.1 4.2 6.3 V 2. 6. 9. V I OW level input voltage.8 2.1 2.8 4.3. 1.3 1.8 2.7. 1.3 1.8 2.7. 1.3 1.8 2.7 V 2. 6. 9. ±I I input leakage current.1.2 1. 2. 1. 2. µa 6. 1. GND ±I S analog switch OFF-state current per channel.1 1. 1. µa 1. V I V I V S = (see Fig.1) ±I S analog switch OFF-state current all channels.4 4. 4. µa 1. V I V I V S = (see Fig.1) ±I S analog switch ON-state current.4 4. 4. µa 1. V I V I V S = (see Fig.11) I CC quiescent supply current 8. 16. 8. 16. 16. 32. µa 6. 1. GND V is = ; V os = December 199 7

74C/CT431 AC CARACTERISTICS FOR 74C GND = V; t r =t f = 6 ns; C = pf SYMBO t P / t P t PZ / t PZ t PZ / t PZ t PZ / t PZ t PZ / t PZ t PZ / t PZ t PZ / t PZ t PZ / t PZ t PZ / t PZ PARAMETER propagation delay 14 V is to V os 4 4 turn ON time 8 E 1 to V os 31 2 28 turn ON time 8 E 2 to V os 31 2 2 turn ON time 91 E to V os 33 26 27 turn ON time 88 S n to V os 32 26 2 turn OFF time 69 E 1 to V os 2 2 2 turn OFF time 72 E 2 to V os 26 21 19 turn OFF time 83 E to V os 3 24 26 turn OFF time 8 S n to V os 29 23 24 T amb ( C) 74C +2 4 to +8 4 to +12 min. typ. max. min. max. min. max. 6 12 1 8 3 6 1 3 6 1 3 6 1 3 6 1 2 43 4 2 43 4 27 47 4 27 47 48 7 1 13 1 37 7 64 69 37 7 64 69 37 7 64 69 37 7 64 63 31 63 4 31 63 4 34 69 9 6 34 69 9 6 9 18 1 12 4 9 77 83 4 9 77 83 4 9 77 83 4 9 77 7 37 7 64 6 37 7 64 6 41 83 71 68 41 83 71 72 UNIT ns 2. 6. ns 2. 6. ns 2. 6. ns 2. 6. ns 2. 6. ns 2. 6. ns 2. 6. ns 2. 6. ns 2. 6. TEST CONDITIONS OTER R = ; C = pf (see Fig.17) R =1 k; C = pf R =1 k; C = pf R =1 k; C = pf R =1 k; C = pf R =1 k; C = pf R =1 k; C = pf R =1 k; C = pf R =1 k; C = pf December 199 8

74C/CT431 T amb ( C) TEST CONDITIONS SYMBO PARAMETER 74C +2 4 to +8 4 to +12 min. typ. max. min. max. min. max. UNIT OTER t su t h t W set-up time S n to E hold time S n to E E minimum pulse width IG 6 12 1 18 1 2 17 2 17 6 9 8 3 2 4 11 1 3 7 7 1 13 23 12 2 21 31 9 18 1 27 1 3 26 38 ns 2. 6. ns 2. 6. ns 2. 6. R =1 k; C = pf (see Fig.19) R =1 k; C = pf (see Fig.19) R =1 k; C = pf (see Fig.19) December 199 9

74C/CT431 DC CARACTERISTICS FOR 74CT Voltages are referenced to GND (ground = ) T amb ( C) TEST CONDITIONS SYMBO V I V I PARAMETER IG level input voltage OW level input voltage ±I I input leakage current ±I S analog switch OFF-state current per channel ±I S analog switch OFF-state current all channels ±I S analog switch ON-state current I CC I CC quiescent supply current additional quiescent supply current per input pin f unit load coefficient is 1 (note 1) 74CT +2 4 to +8 4 to +12 UNIT min. typ. max. min. max. min. max. 2. 1.6 2. 2. V to. 1.2.8.8.8 V to..1 1. 1. µa. GND.1 1. 1. µa 1. V I V I.4 4. 4. µa 1. V I V I.4 4. 4. µa 1. V I V I 8. 16. 8. 16. 16. 32. µa.. 1 36 4 49 µa to.. V I GND 2.1 V OTER V S = (see Fig.1) V S = (see Fig.1) V S = (see Fig.11) V is = ; V os = other inputs at GND Note to CT types 1. The value of additional quiescent supply current ( I CC ) f a unit load of 1 is given here. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT E 1, E 2 S n E UNIT OAD COEFFICIENT.. 1. December 199 1

74C/CT431 AC CARACTERISTICS FOR 74CT GND = V; t r =t f = 6 ns; C = pf SYMBO t P / t P t PZ / t PZ t PZ / t PZ t PZ / t PZ t PZ / t PZ t PZ / t PZ t PZ / t PZ t PZ / t PZ t PZ / t PZ t su t h t W PARAMETER propagation delay 6 V is to V os 4 turn ON time 4 E 1 to V os 31 turn ON time 3 E 2 to V os 26 turn ON time 42 E to V os 37 turn ON time 39 S n to V os 3 turn OFF time 27 E 1 to V os 2 turn OFF time 32 E 2 to V os 26 turn OFF time 33 E to V os 3 turn OFF time 33 S n to V os 29 set-up time S n to E hold time S n to E E minimum pulse width IG T amb ( C) 74CT +2 4 to +8 4 to +12 min. typ. max. min. max. min. max. 12 14 2 2 6 7 1 2 13 13 12 8 7 6 7 7 6 7 6 4 6 6 6 1 1 94 7 88 63 94 7 94 7 69 7 63 7 69 81 69 1 18 31 31 18 12 113 9 1 7 113 9 113 9 83 6 9 7 9 83 98 83 18 21 38 38 UNIT ns ns ns ns ns ns ns ns ns ns ns ns TEST CONDITIONS OTER R = ; C = pf (see Fig.17) R =1 k; C = pf R =1 k; C = pf R =1 k; C = pf R =1 k; C = pf R =1 k; C = pf R =1 k; C = pf R =1 k; C = pf R =1 k; C = pf R =1 k; C = pf (see Fig.19) R =1 k; C = pf (see Fig.19) R =1 k; C = pf (see Fig.19) December 199 11

74C/CT431 Fig.8 Test circuit f measuring R ON. Fig.9 Typical R ON as a function of input voltage V is f V is = to. Fig.1 Test circuit f measuring OFF-state current. Fig.11 Test circuit f measuring ON-state current. December 199 12

74C/CT431 ADDITIONA AC CARACTERISTICS FOR 74C/CT Recommended conditions and typical values GND = V; T amb =2 C SYMBO PARAMETER typ. UNIT V is(pp) CONDITIONS V (pp) f max C S sine-wave disttion f = 1 kz sine-wave disttion f = 1 kz switch OFF signal feed-through crosstalk voltage between control and any switch (peak-to-peak value) minimum frequency response (3dB) maximum switch capacitance independent (Y) common (Z).4.2.12.6 12 22 16 17 2 % % % % db db mv mv Mz Mz pf pf 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 4. 8. 4. 8. note 1 note 2 R = 1 k; C = pf (see Fig.14) R = 1 k; C = pf (see Fig.14) R = 6 ; C = pf (see Figs 12 and 1) R = 6 ; C = pf; f = 1 Mz (E 1, E 2 S n, square-wave between and GND, t r =t f = 6 ns) (see Fig.16) R =; C = 1 pf (see Figs 13 and 14) Notes to AC characteristics 1. Adjust input voltage V is to dbm level ( dbm = 1 mw into 6 ). 2. Adjust input voltage V is to dbm level at V os f 1 Mz ( dbm = 1 mw into ). V is is the input voltage at a Y n Z terminal, whichever is assigned as an input. V os is the output voltage at a Y n Z terminal, whichever is assigned as an output. Test conditions: = V; GND = V; = V; R =; R source =1 k. Fig.12 Typical switch OFF signal feed-through as a function of frequency. December 199 13

74C/CT431 Test conditions: = V; GND = V; = V; R =; R source =1 k. Fig.13 Typical frequency response. Fig.14 Test circuit f measuring sine-wave disttion and minimum frequency response. Fig.1 Test circuit f measuring switch OFF signal feed-through. The crosstalk is defined as follows (oscilloscope output): Fig.16 Test circuit f measuring crosstalk between control and any switch. December 199 14

74C/CT431 AC WAVEFORMS C : V M = %; V I = GND to. CT: V M = 1.3 V; V I = GND to 3 V. Fig.17 Wavefms showing the input (V is ) to output (V os ) propagation delays. Fig.18 Wavefms showing the turn-on and turn-off times. C : V M = %; V I = GND to. CT: V M = 1.3 V; V I = GND to 3 V. Fig.19 Wavefms showing the set-up and hold times from S n inputs to E input, and minimum pulse width of E. December 199 1

74C/CT431 TEST CIRCUIT AND WAVEFORMS Conditions TEST SWITC V is t PZ t PZ t PZ t PZ others open pulse t r ; t f FAMIY AMPITUDE V M f max ; OTER PUSE WIDT 74C % < 2 ns 6 ns 74CT 3. V 1.3 V < 2 ns 6 ns C = load capacitance including jig and probe capacitance (see AC CARACTERISTICS f values). R T = termination resistance should be equal to the output impedance Z O of the pulse generat. t r = t f = 6 ns; when measuring f max, there is no constraint on t r, t f with % duty fact. Fig.2 Test circuit f measuring AC perfmance. Conditions TEST SWITC V is t PZ t PZ t PZ t r ; t f FAMIY AMPITUDE V M f max ; PUSE WIDT OTER t PZ others open pulse 74C % < 2 ns 6 ns 74CT 3. V 1.3 V < 2 ns 6 ns C = load capacitance including jig and probe capacitance (see AC CARACTERISTICS f values). R T = termination resistance should be equal to the output impedance Z O of the pulse generat. t r = t f = 6 ns; when measuring f max, there is no constraint on t r, t f with % duty fact. Fig.21 Input pulse definitions. December 199 16

74C/CT431 PACKAGE OUTINES See 74C/CT/CU/CMOS ogic Package Outlines. December 199 17