Review: What s an FSM? EECS Components and Design Techniques for Digital Systems

Similar documents
1 Finite Automata and Regular Expressions

Library Support. Netlist Conditioning. Observe Point Assessment. Vector Generation/Simulation. Vector Compression. Vector Writing

Math 266, Practice Midterm Exam 2

Revisiting what you have learned in Advanced Mathematical Analysis

Transfer function and the Laplace transformation

Digital Signal Processing. Digital Signal Processing READING ASSIGNMENTS. License Info for SPFirst Slides. Fourier Transform LECTURE OBJECTIVES

Fourier Series and Parseval s Relation Çağatay Candan Dec. 22, 2013

CSE 245: Computer Aided Circuit Simulation and Verification

ELECTRIC VELOCITY SERVO REGULATION

Laplace Transform. National Chiao Tung University Chun-Jen Tsai 10/19/2011

A Tutorial of The Context Tree Weighting Method: Basic Properties

3.4 Repeated Roots; Reduction of Order

Inverse Fourier Transform. Properties of Continuous time Fourier Transform. Review. Linearity. Reading Assignment Oppenheim Sec pp.289.

2 T. or T. DSP First, 2/e. This Lecture: Lecture 7C Fourier Series Examples: Appendix C, Section C-2 Various Fourier Series

Jonathan Turner Exam 2-10/28/03

Control Systems. Modelling Physical Systems. Assoc.Prof. Haluk Görgün. Gears DC Motors. Lecture #5. Control Systems. 10 March 2013

READING ASSIGNMENTS. Signal Processing First. Fourier Transform LECTURE OBJECTIVES. This Lecture: Lecture 23 Fourier Transform Properties

Advanced Engineering Mathematics, K.A. Stroud, Dexter J. Booth Engineering Mathematics, H.K. Dass Higher Engineering Mathematics, Dr. B.S.

where: u: input y: output x: state vector A, B, C, D are const matrices

16.512, Rocket Propulsion Prof. Manuel Martinez-Sanchez Lecture 3: Ideal Nozzle Fluid Mechanics

Final Exam : Solutions

More on FT. Lecture 10 4CT.5 3CT.3-5,7,8. BME 333 Biomedical Signals and Systems - J.Schesser

Fourier. Continuous time. Review. with period T, x t. Inverse Fourier F Transform. x t. Transform. j t

Parity Checker Example. EECS150 - Digital Design Lecture 9 - Finite State Machines 1. Formal Design Process. Formal Design Process

Chapter 5 The Laplace Transform. x(t) input y(t) output Dynamic System

Physics 160 Lecture 3. R. Johnson April 6, 2015

Lecture 2: Current in RC circuit D.K.Pandey

Statistics Assessing Normality Gary W. Oehlert School of Statistics 313B Ford Hall

REPETITION before the exam PART 2, Transform Methods. Laplace transforms: τ dτ. L1. Derive the formulas : L2. Find the Laplace transform F(s) if.

CS 541 Algorithms and Programs. Exam 2 Solutions. Jonathan Turner 11/8/01

More Digital Logic. t p output. Low-to-high and high-to-low transitions could have different t p. V in (t)

Relation between Fourier Series and Transform

MEM 355 Performance Enhancement of Dynamical Systems A First Control Problem - Cruise Control

Chapter4 Time Domain Analysis of Control System

Optimality of Myopic Policy for a Class of Monotone Affine Restless Multi-Armed Bandit

Poisson process Markov process

Trigonometric Formula

EECS Components and Design Techniques for Digital Systems. FSMs 9/11/2007

Lecture 21 : Graphene Bandstructure

Multipath Interference Characterization in Wireless Communication Systems

Pupil / Class Record We can assume a word has been learned when it has been either tested or used correctly at least three times.

Mathcad Lecture #4 In-class Worksheet Vectors and Matrices 1 (Basics)

Boyce/DiPrima 9 th ed, Ch 2.1: Linear Equations; Method of Integrating Factors

PFC Predictive Functional Control

x, x, e are not periodic. Properties of periodic function: 1. For any integer n,

The Laplace Transform

4.8 Improper Integrals

Process Modeling of Short-Circuiting GMA Welding and Its Application to Arc Sensor Control

Instructors Solution for Assignment 3 Chapter 3: Time Domain Analysis of LTIC Systems

Introduction to Laplace Transforms October 25, 2017

The model proposed by Vasicek in 1977 is a yield-based one-factor equilibrium model given by the dynamic

Mixing Real-Time and Non-Real-Time. CSCE 990: Real-Time Systems. Steve Goddard.

FL/VAL ~RA1::1. Professor INTERVI of. Professor It Fr recru. sor Social,, first of all, was. Sys SDC? Yes, as a. was a. assumee.

Explaining Synthesis of Three-Phase Sinusoidal Voltages Using SV-PWM in the First Power Electronics Course

Review: Designing with FSM. EECS Components and Design Techniques for Digital Systems. Lec09 Counters Outline.

LaPlace Transform in Circuit Analysis

e t dt e t dt = lim e t dt T (1 e T ) = 1

PHA Second Exam. Fall 2007

Partial Fraction Expansion

T h e C S E T I P r o j e c t

Chapter 3: Fourier Representation of Signals and LTI Systems. Chih-Wei Liu

Bipartite Matching. Matching. Bipartite Matching. Maxflow Formulation

The Procedure Abstraction Part II: Symbol Tables and Activation Records

Midterm. Answer Key. 1. Give a short explanation of the following terms.

Fourier Series: main points

6 Synchronous State Machine Design

A Study of the Solutions of the Lotka Volterra. Prey Predator System Using Perturbation. Technique

EE Control Systems LECTURE 11

AE57/AC51/AT57 SIGNALS AND SYSTEMS DECEMBER 2012

INTERQUARTILE RANGE. I can calculate variabilityinterquartile Range and Mean. Absolute Deviation

DEPARTMENT OF ELECTRICAL &ELECTRONICS ENGINEERING SIGNALS AND SYSTEMS. Assoc. Prof. Dr. Burak Kelleci. Spring 2018

Minimum Squared Error

Minimum Squared Error

Engine Thrust. From momentum conservation

Wave Phenomena Physics 15c

1. Be a nurse for 2. Practice a Hazard hunt 4. ABCs of life do. 7. Build a pasta sk

EEO 401 Digital Signal Processing Prof. Mark Fowler

Review Lecture 5. The source-free R-C/R-L circuit Step response of an RC/RL circuit. The time constant = RC The final capacitor voltage v( )

CPSC 211 Data Structures & Implementations (c) Texas A&M University [ 259] B-Trees

P a g e 5 1 of R e p o r t P B 4 / 0 9

0 for t < 0 1 for t > 0

EXERCISE - 01 CHECK YOUR GRASP

A L A BA M A L A W R E V IE W

1. Accident preve. 3. First aid kit ess 4. ABCs of life do. 6. Practice a Build a pasta sk

EEE 303: Signals and Linear Systems

EECS150 - Digital Design Lecture 23 - FSMs & Counters

Behaviors and Attitudes

Lecture 1: Numerical Integration The Trapezoidal and Simpson s Rule

Voltage v(z) ~ E(z)D. We can actually get to this wave behavior by using circuit theory, w/o going into details of the EM fields!

Boyce/DiPrima 9 th ed, Ch 7.8: Repeated Eigenvalues

PHYSICS 1210 Exam 1 University of Wyoming 14 February points

Control System Engineering (EE301T) Assignment: 2

Ma/CS 6a Class 15: Flows and Bipartite Graphs

Review: Designing with FSM. EECS Components and Design Techniques for Digital Systems. Lec 09 Counters Outline.

Wave Equation (2 Week)

rank Additionally system of equation only independent atfect Gawp (A) possible ( Alb ) easily process form rang A. Proposition with Definition

PHA Final Exam Fall On my honor, I have neither given nor received unauthorized aid in doing this assignment.

Sequential Logic. Digital Integrated Circuits A Design Perspective. Latch versus Register. Naming Conventions. Designing Sequential Logic Circuits

Physical Limitations of Logic Gates Week 10a

EE 434 Lecture 22. Bipolar Device Models

Transcription:

EECS 5 - Componn nd Dign Tchniqu for Digil Sym Lc 8 Uing, Modling nd Implmning FSM 9-23-4 Dvid Cullr Elcricl Enginring nd Compur Scinc Univriy of Cliforni, Brkly hp://www.c.brkly.du/~cullr hp://www-in.c.brkly.du/~c5 Rviw: Wh n FSM? Nx i funcion of nd inpu Moor Mchin: oupu i funcion of h inpua S / oupu inpub Mly Mchin: oupu i funcion of nd inpu S inpua/oupua inpub/oupub Ofn PLA 9/23/4 EECS5 F4 Cullr Lc 8 9/23/4 EECS5 F4 Cullr Lc 8 2 Rviw: Forml Dign Proc Logic quion from bl: OUT = PS NS = PS xor IN Circui Digrm: p n Rviw of Dign Sp:. Circui funcionl pcificion 2. S Trniion Digrm 3. Symbolic S Trniion Tbl 4. Encodd S Trniion Tbl 5. Driv Logic Equion 6. Circui Digrm FF for XOR g for n clculion for NS nd OUT DFF o hold prn no ndd for oupu 9/23/4 EECS5 F4 Cullr Lc 8 3 Rviw: Fini S Mchin Rprnion S: drmind by poibl vlu in qunil org lmn Trniion: chng of Clock: conrol whn cn chng by conrolling org lmn Squnil Logic Squnc hrough ri of Bd on qunc of vlu on inpu ignl Clock priod dfin lmn of qunc 9/23/4 EECS5 F4 Cullr Lc 8 4 Oulin Rviw Typicl u of FSM Synchronou Sq. Circui f compoiion Timing FSM in vrilog (rinforcing lb lcur) S rducion nd ignmn 9/23/4 EECS5 F4 Cullr Lc 8 5 Rcll: Prlll o Sril Convrr //Prlll o Sril convrr modul PrToSr(LD, X, ou, K); inpu [3:] X; inpu LD, K; oupu ou; rg ou; rg [3:] Q; ign ou = Q[]; lwy @ (podg K) bgin On common u of FSM i in dpr from on ubym o nohr. diffrn d widh diffrn bi r if (LD) Q <= X; diffrn proocol, l Q <= { b,q[3:]}; modul // PrToSr 9/23/4 EECS5 F4 Cullr Lc 8 6

Exmpl: By-bi rm By-bi rm wih R Mching By FIFO ini / LD bi /pop bi pop bi 2 conrollr bi 3 Shif rgir LD bi 4 Sril link bi 5 bi 6 bi 7 / LD 9/23/4 EECS5 F4 Cullr Lc 8 7 By FIFO ini / LD bi /pop ~ bi bi ~ ~ pop bi 2 ~ conrollr bi 3 Shif rgir ~ LD bi 4 ~ Sril link bi 5 ~ bi 6 How would you implmn hi FSM? ~ bi 7 / LD 9/23/4 EECS5 F4 Cullr Lc 8 ~ 8 Anohr xmpl: bu proocol A bu i: hrd communicion link ingl of wir ud o connc mulipl ubym Exmpl: Pnium Sym Orgnizion Procor/Mmory Bu Procor Conrol Mmory Inpu Dph Oupu PCI Bu A Bu i lo fundmnl ool for compoing lrg, complx ym (mor lr in h rm) ymic mn of brcion 9/23/4 EECS5 F4 Cullr Lc 8 9 I/O Bu 9/23/4 EECS5 F4 Cullr Lc 8 Arbirion for h bu Simpl Synchronou Proocol Bu Arbir Grn Dvic Rq Dvic 2 Dvic N BRq BG CMD Addr I wn h bu nop I ill wn h bu You go i Rd+Addr Mm grb ddr Proc grb d I m don fr hi D D D2 Cnrl rbirion hown hr Ud in nilly ll procor-mmory bu nd in highpd I/O bu 9/23/4 EECS5 F4 Cullr Lc 8 Evn mmory bu r mor complx hn hi mmory (lv) my k im o rpond i nd o conrol d r 9/23/4 EECS5 F4 Cullr Lc 8 2

Procor Sid of Proocol - kch Idl ~BR ~BG proc rd Rqu bu BR BG Mmory wi? Addiionl oupu? Mmory id? Addr BR,RD, ddr_nbl D BR, MDR_nbl D 2 ~BR, MDR_nbl BRq BG Simpl Synchronou Proocol (con) CMD Addr D I wn h bu nop I ill wn h bu You go i Rd+Addr Mm grb ddr D Proc grb d I m don fr hi D2 idl rq rq w-ddr r-d r-d2 idl 9/23/4 EECS5 F4 Cullr Lc 8 3 9/23/4 EECS5 F4 Cullr Lc 8 4 Fundmnl Dign Principl Divid circui ino combinionl nd Locliz fdbck loop nd mk i y o brk cycl Implmnion of org lmn ld o vriou form of qunil Form of Squnil Logic Aynchronou qunil chng occur whnvr inpu chng (lmn my b impl wir or dly lmn) Synchronou qunil chng occur in lock p cro ll org lmn (uing priodic wvform - h clock) 9/23/4 EECS5 F4 Cullr Lc 8 5 9/23/4 EECS5 F4 Cullr Lc 8 6 Gnrl Modl of Synchronou Circui clock inpu Compoing FSM ino lrgr dign FSM FSM inpu rg rg oupu opion fdbck All wir, xcp clock, my b mulipl bi wid. Rgir (rg) collcion of flip-flop clock diribud o ll flip-flop ypicl r? oupu Combinionl Logic Block () no inrnl (no fdbck) oupu only funcion of inpu Priculr inpu/oupu r opionl Opionl Fdbck ALL CYES GO THROUGH A REG! 9/23/4 EECS5 F4 Cullr Lc 8 7 9/23/4 EECS5 F4 Cullr Lc 8 8

Compoing Moor FSM Compoing Mly FSM nx Moor oupu nx Moor oupu Mly FSM Oupu Nx Oupu Nx Synchronou dign mhodology prrvd 9/23/4 EECS5 F4 Cullr Lc 8 9 Synchronou dign mhodology viold!!! Why do dignr ud hm? Fw, ofn mor nurl in iolion Sf if lch ll h oupu» Look lik mly mchin, bu in rlly» Wh hppn o h iming? 9/23/4 EECS5 F4 Cullr Lc 8 2 FSM iming Clock How long mu hi b? S Tim (Clock Priod) Announcmn Rding 8.4,7.4, 8. W ouchd on id from chpr, no in rdr. Will b vilbl on lin. Inpu Wh drmin hi? Oupu S (inrnl) Oupu propgion dly S rgir propgion dly Wh drmin min FSM cycl im (mx clock r)? 9/23/4 EECS5 F4 Cullr Lc 8 2 9/23/4 EECS5 F4 Cullr Lc 8 22 Fini S Mchin in Vrilog Mly oupu Vrilog FSM - Rduc xmpl Chng h fir o in ch ring of Exmpl Moor mchin implmnion inpu combinionl nx combinionl currn Moor oupu modul Rduc(Ou, Clock, R, In); oupu Ou; inpu Clock, R, In; rg Ou; rg [:] CurrnS; // rgir rg [:] NxS; // S ignmn loclprm STATE_Zro = 2 h, STATE_On = 2 h, STATE_Two = 2 h2, STATE_X = 2 hx; 9/23/4 EECS5 F4 Cullr Lc 8 23 9/23/4 EECS5 F4 Cullr Lc 8 24

Moor Vrilog FSM: combinionl pr Moor Vrilog FSM: pr lwy @(In or CurrnS) bgin NxS = CurrnS; Ou = b; c (CurrnS) STATE_Zro: bgin // l inpu w zro if (In) NxS = STATE_On; STATE_On: bgin // w'v n on if (In) NxS = STATE_Two; l NxS = STATE_Zro; STATE_Two: bgin // w'v n l 2 on Ou = ; if (~In) NxS = STATE_Zro; dful: bgin // in c w rch bd Ou = bx; NxS = STATE_X; c // Implmn h rgir lwy @ (podg Clock) bgin if (R) CurrnS <= l CurrnS <= modul STATE_Zro; NxS; No: podg Clock rquir NONBLOCKING ASSIGNMENT. Blocking Aignmn <-> Combinionl Logic Nonblocking Aignmn <-> Squnil Logic (Rgir) Compu: oupu = G() 9/23/4 EECS5 F4 Cullr Lc 8 nx = F(, in) 25 9/23/4 EECS5 F4 Cullr Lc 8 26 Mly Vrilog FSM for Rduc- xmpl modul Rduc(Clock, R, In, Ou); inpu Clock, R, In; oupu Ou; rg Ou; rg CurrnS; // rgir rg NxS; loclprm STATE_Zro = b, STATE_On = b; lwy @(podg Clock) bgin if (R) CurrnS <= STATE_Zro; l CurrnS <= NxS; No: mllr mchin lwy @ (In or CurrnS) bgin NxS = CurrnS; Ou = b; c (CurrnS) zro: if (In) NxS = STATE_On; on: bgin // w'v n on if (In) NxS = STATE_On; l NxS = STATE_Zro; Ou = In; Oupu = G(, inpu) c modul 9/23/4 EECS5 F4 Cullr Lc 8 27 Rricd FSM Implmnion Syl Mly mchin rquir wo lwy block Rgir nd podg Clock block Inpu o oupu nd combinionl block Moor mchin cn b don wih on lwy block, bu. E.g. impl counr Vry bd id for gnrl FSM» Thi will co you hour of confuion, don ry i» W will no ccp lb wih hi yl for gnrl FSM U wo lwy block! Moor oupu Shr wih rgir, u uibl ncoding 9/23/4 EECS5 F4 Cullr Lc 8 28 Singl-lwy Moor Mchin (No Allowd!) modul rduc (clk, r, in, ou); inpu clk, r, in; oupu ou; rg ou; rg [:] ; // rgir prmr zro =, on =, wo = 2; 9/23/4 EECS5 F4 Cullr Lc 8 29 Singl-lwy Moor Mchin (No Allowd!) # lwy @(podg clk) c () zro: bgin ou <= ; if (in) <= on; l <= zro; on: if (in) bgin <= wo; ou <= ; l bgin <= zro; ou <= ;! " wo: if (in) bgin <= wo; ou <= ; l bgin <= zro; ou <= ; dful: bgin <= zro; ou <= ; c modul 9/23/4 EECS5 F4 Cullr Lc 8 3

Fini S Mchin FSM Opimizion inpu combinionl nx Mly oupu combinionl currn Moor oupu Rcommd FSM implmnion yl Implmn combinionl uing on lwy block Implmn n xplici rgir uing cond lwy block S Rducion: Moivion: lowr co» fwr flip-flop in onho implmnion» poibly fwr flipflop in ncodd implmnion» mor don cr in NS» fwr g in NS Simplr o dign wih xr hn rduc lr. Exmpl: Odd priy chckr. Two mchin - idnicl bhvior. S [] S [] S2 [] S [] S [] 9/23/4 EECS5 F4 Cullr Lc 8 3 9/23/4 EECS5 F4 Cullr Lc 8 32 S Rducion S Rducion i bd on: Two r quivln if, for ch mmbr of h of inpu, hy giv xcly h m oupu nd h circui ihr o h m or o n quivln. If wo r quivln, on cn b limind wihou ffcing h bhvior of h FSM. Svrl lgorihm xi: Row mching mhod. Implicion bl mhod. Row Mching i bd on h -rniion bl: If wo hv h m oupu, nd boh rniion o h m nx, or boh rniion o ch ohr, or boh lf-loop, hn hy r quivln. Combin h quivln ino nw rnmd. Rp unil no mor r combind. No: Thi lgorihm i lighly diffrn hn h book. Row Mching Exmpl S Trniion Tbl NS oupu PS x= x= x= x= b b c d c d d f f f g f g f 9/23/4 EECS5 F4 Cullr Lc 8 33 9/23/4 EECS5 F4 Cullr Lc 8 34 Row Mching Exmpl (con) NS oupu PS x= x= x= x= b b c d c d d f f f f NS oupu PS x= x= x= x= b b c d c d d d d Rducd S Trniion Digrm S Rducion Th row mching mhod i no gurnd o rul in h opiml oluion in ll c, bcu i only look pir of. For xmpl: / / / S S S2 / / / Anohr (mor complicd) mhod gurn h opiml oluion: Implicion bl mhod: cf. Mno, chpr 9 Wh rul of humb huriic? 9/23/4 EECS5 F4 Cullr Lc 8 35 9/23/4 EECS5 F4 Cullr Lc 8 36

S Mp S S S3 S2 Aignmn S q2 q q S S S2 S3 S4 q q q q S4 q2 q2 S S4 S3 S S S3 S2 S S2 Aignmn S q2 q q S S S2 S3 S4 S4 K-mp r ud o hlp viuliz good ncoding. Adjcn in h STD hould b md djcn in h mp. 9/23/4 EECS5 F4 Cullr Lc 8 37 S Aignmn Alrniv huriic bd on inpu nd oupu bhvior wll rniion: α i/j β i/k Adjcn ignmn o: h hr common nx (group ' in nx mp) High Prioriy Mdium Prioriy α α i/j β β i/j Low Prioriy h hr common ncor (group ' in nx mp) h hv common oupu bhvior (group ' in oupu mp) 9/23/4 EECS5 F4 Cullr Lc 8 38 Summry FSM r criicl ool in your dign oolbox Adpr, Proocol, Dph Conrollr, Thy ofn inrc wih ohr FSM Imporn o dign ch wll nd o mk hm work oghr wll. Kp your vrilog FSM cln Spr combinionl pr from upd Good mchin dign i n iriv proc S ncoding Rducion Aignmn 9/23/4 EECS5 F4 Cullr Lc 8 39