PRACTICE PROBLEMS FOR CMOS ANALOG CIRCUIT DESIGN, 2 ND EDITION

Practice Problems (5/27/07) Page PRACTICE PROBLEMS FOR CMOS ANALOG CIRCUIT DESIGN, 2 ND EDITION TECHNOLOGY Problem (044430E3P5) The following questions pertain to a standard npn BJT process. a.) Give the relative doping levels of the emitter, base and collector for the vertical npn transistor. Emitter doping >> base doping > collector doping b.) Give the relative doping levels of the emitter, base and collector for the lateral pnp transistor. Emitter doping Collector doping > base doping c.) How is on vertical npn BJT electrically isolated from another? By reverse biasing the collectorsubstrate pn junction What is the purpose of the n buried layer? To reduce the value of the collector bulk resistance, RC. d.) Why is a p diffusion region used to contact the base? To form an ohmic contact, otherwise a schottky diode is formed between the metal and the base region. e.) What dimension is important for high and f t? f.) g.) h.) i.) Small base width the distance from the emitter to the collector Of the parasitic bulk resistances (RE, RB, and RC) for a vertical npn transistor, which is usually the largest? Smallest? RC is the largest andre is the smallest Of the depletion capacitors (C BE, C BC, and C CS ) for a vertical npn transistor, which is usually the largest? Smallest? C CS is largest and C BE is the smallest Of the parasitic bulk resistances (RE, RB, and RC) for a lateral pnp transistor, which is usually the largest? Smallest? RB is the largest and RE is the smallest Of the depletion capacitors (C BE, C BC, and C BS ) for a lateral pnp transistor, which is usually the largest? Smallest? C BS is the largest and C BE is the smallest

Practice Problems (5/27/07) Page 2 LAYOUT AND PARASITICS Problem (044430E3P) A top view of a npn lateral BJT built in a typical pwell CMOS technology is shown. The metal connections have been left out for purposes of clarity. a.) Using the information from the table on the following page, carefully sketch a crosssection along the indicated line AA. Show only the structures that are diffused into the substrate and none of the structures above the substrate. b.) Find the zerobias depletion capacitors C bc0, C be0, and C bs0 using the information on the previous page. c.) If the resistivity of the polysilicon used is 2.5x0 4 cm, what is its thickness? a.) See plot below. b.) C be0 = A ;; n diffusion ;; p well ;;;;;; ;;;;;; ;;;;;; ;;;;;; ;;;;;; n substrate ;Polysilicon Surface ;;;;;; ;;;;;; A' 0.33fF/μm 2 (6μm 2 ) 0.9fF/μm(6μm) = 5.28fF 4.4fF = 9.7fF C bc0 = 0.33fF/μm 2 (8 2 μm 2 8 2 μm 2 )0.9fF/μm(4x8μm4x8 μm) = 85.8fF 93.6fF = 79.4fF C bs0 = 0.2fF/μm 2 (900μm 2 ).6fF/μm(20μm) = 80fF 92fF = 372fF c.) T = 25/sq. T = 25 = 2.5x04 25 T = 0.5μm For the crosssection, expand the vertical scale x5 Each square is μm on the side Su04E3S

Practice Problems (5/27/07) Page 3 Some process parameters for a typical pwell CMOS process. Physical feature sizes T ox (gate oxide thickness) 500 ±00 Å Total lateral diffusion nchannel 0.45 ±0.5 μm pchannel 0.6 ±0.3 μm Diffusion depth n diffusion 0.45 ±0.5 μm p diffusion 0.6 ±0.3 μm p well 3.0 ±30% μm Capacitances C ox (gate oxide capacitance, n and pchannel) 0.7 ±0. ff/μm 2 n diffusion to pwell (junction, bottom) 0.33 ±0.7 ff/μm 2 n diffusion to pwell (junction, sidewall) 0.9 ±0.45 ff/μm p diffusion to substrate (junction, bottom) 0.38 ±0.2 ff/μm 2 n diffusion to substrate (junction, sidewall).0 ±0.5 ff/μm pwell to substrate (junction, bottom) 0.2 ±0. ff/μm 2 pwell sidewall (junction, sidewall).6 ±.0 ff/μm Resistances Substrate 25 ±20% cm pwell 5000 ±2500 /sq. n diffusion 35 ±25 /sq. p diffusion 80 ±55 /sq. Poly 25 ±25% /sq. Metal contact to p or n (2μm x 2μm) 4

Practice Problems (5/27/07) Page 4 Problem 2 (044430E3P3) A CMOS inverter is shown along with the top view of the circuit layout assuming a pwell CMOS technology. If this inverter is driving and identical inverter with the same layout, find magnitude of the pole at the output of the first inverter (v x ) and the input of the second inverter which is equal to the reciprocal product of the sum of all capacitances connected to this node and the output resistance which is assumed to be M. Express this pole magnitude in Hz. Use the table below to calculate the capacitances. Type PChannel NChannel Units CGSO 220 0 2 220 0 2 F/m CGDO 220 0 2 220 0 2 F/m CGBO 700 0 2 700 0 2 F/m CJ 560 0 6 770 0 6 F/m 2 CJSW 350 0 2 380 0 2 F/m MJ 0.5 0.5 MJSW 0.35 0.38 Based on an oxide thickness of 40 Å or Cox=24.7 0 4 F/m 2 (2.5V) M2 5V (2.5V) M v x M4 5V M3 (2.5V) Su04E3P3A ;;; ; n p Metal Poly pwell nsubstrate ;;;; ;; ;;;;; ; ;;;;; M2 ;;;; ;;;;;; ;;;;; ;; 5V M4 v ;; in v ;; ;; x ;;; ;;;; M ;;;; M3 Ground ;; ;; ;;;; Each square is μm x μm C i = C gd C gd2 C bd C bd2 C gs3 C gs4 C gd3 C gd4 C gd = C gd3 = 220x0 2 0x0 6 = 2.2fF C gd2 = C gd2 = 220x0 2 20x0 6 = 4.4fF Next, we must find the area and perimeter of each drain. AD = AD3 = 60m 2 & PD = PD3 = 32m AD2 = AD4 = 20m 2 & PD2 = PD4 = 52m Su04E3P3B

Practice Problems (5/27/07) Page 5 Problem 2 (044430E3P3) Continued CJ AD C bd = 2.5V MJ 2 F CJSW PD 2.5V = MJSW 2 F C bd = C bd3 = 22.75fF 7.0fF = 29.84fF 2 770x0 6 60x0 2.5V 0.8 0.5 6 380x0 2 32x0 2.5V 0.38 0.8 CJ AD2 C bd2 = 2.5V 2 F MJ CJSW PD2 2.5V = 560x0 6 20x0 2 350x02 52x06 MJSW 2 F 2.5V 0.7 0.5 2.5V 0.35 0.7 C bd2 = C bd4 = 3.43fF 0.69fF = 42.2fF C gs3 = C gd 0.67(C ox W 3 L 3 ) = 2.2fF 0.67(24.7x0 4 x20x0 2 ) = 35.3fF C gs4 = C gd2 0.67(C ox W 4 L 4 ) = 4.4fF 0.67(24.7x0 4 x40x0 2 ) = 70.2fF Now, p = C i = 2.2fF 4.4fF 29.84fF 42.2fF 35.3fF 70.2fF 2.2fF 4.4fF = 90.45fF. (C 0 6 = i) 90.45x0 5 0 6 = 5.25x0 6 p = 835.7 khz

Practice Problems (5/27/07) Page 6 Problem 3 (004430E2P3) A simple firstorder filter shown is to be built with a polysilicon resistor and a MOS capacitor. The polysilicon resistor has a sheet resistance of 50/sq. ± 30% and is 5m wide. The MOS capacitor is 2fF/m 2 ± 0%. The 3dB frequency of the lowpass filter is MHz. (a.) Choose the size of the resistor (the number of squares, N) to minimize the total area of the filter including both the resistor and the R poly C MOS F00E2P2 capacitor. Find the area of the resistor and the capacitor in m 2 and their values. (b.) Using the worstcase tolerance of the resistor and capacitor, find the maximum and minimum 3dB frequencies. (a.) Value of R = 50/sq.xN sq. = 50N Value of C = 2fF/m 2 xa C m 2 = 2A C ff Area of C = A C Area of R = A R = 25m 2 xn = 25N m 2 Total Area = A T = (25N A C ) m 2 We know that the RC product is given as A C = RC = 2x0 6 = (50N)(2A C x05 ) = NA C x0 3 2x0 7 N Thus, A T = 25N N = 2x0 7 N da T dn = 25 2x0 7 N 2 = 0 50x0 7 = 252 A R = 252x25m2 = 6308m 2 and A C = 6308m 2 Also, R poly = R = 252x50 = 2.6k (b.) Maximum 3dB frequency = Minimum 3dB frequency = and C MOS = 6308m 2 x2ff/m 2 = 2.6pF 2(0.7)(2.6k)(0.9)(2.6pF) =.6MHz 2(.3)(2.6k)(.)(2.6pF) = 0.7MHz

Practice Problems (5/27/07) Page 7 Problem 4 (004430E3P) A layout of a NMOS transistor is shown below. (a.) Find the values of RD, and RS in the schematic shown if the sheet resistance of the n is 35 /sq. and the resistance of a single contact is. (b.) Find the values of C BD and C BS assuming the transistor is cutoff and the drain and source are at ground potential if CJ and CJSW for an NMOS transistor are 770x0 6 F/m 2 and 380x0 2 F/m. Assume the capacitors are lumped and appear on the source/drain side of the bulk resistors in part (a.). (c.) What is the W and L of this transistor? (d.) If the overlap capacitor/unit length is 220x0 2 F/m, what is C GD? Blue Red Black White White External Gate External Drain R D R S External Source C BD C BS F00E2PY n Metal Poly Contact psubstrate External Drain External Source External Gate Each square is m x m Fig. F00E2PA (a.) The area between the edge of the contacts to the polysilicon is 5m by 22m. This represents a bulk resistance of (5/22)x35 /sq. = 7.95. Adding 5 contacts in parallel gives RD = RS = 7.950.2 = 8.5. (b.) The area or the source and drain are equal and are 9m by 22m or 98m 2. The perimeter of the source and drain are 2(9m22m) or 62m. Therefore, C BD = C BS = 770x0 6 F/m 2 x98x0 2 m 2 380x0 2 F/m x 62x0 6 m C BD = C BS = 52fF 24fF = 76fF (c.) The W = 22m and the L = 2m. (d.) The overlap capacitor is C GD = 220x0 2 F/m x 22x0 6 m = 4.8fF

Practice Problems (5/27/07) Page 8 Problem 5 (00642EP) This problem concerns the influences of the physical implementations of BJT and MOS transistors on their smallsignal electrical performance, namely, the transconductance parameter, g m. (a.) The layouts below are for an NPN bipolar transistor and an NMOS fieldeffect transistor. It is desired to increase the transconductance, g m, by a factor of two. Show how to do this by changing the shape of only one geometry (i.e. rectangle) for each of the transistors. The resolution of any changes is restricted to m. First describe in words how you would do this, then illustrate the changes on the layouts below. Use red ink on the layouts below to indicate the changes you would make. Identify which terminal is collector, base and emitter for the BJT and drain, gate and source for the MOSFET. Each square is ;;; ;; n emitter. p isolation Metal p base nepitaxial μm x μm n ;;;;;;;; ;; p ;;;;;;;; ;; ;; ;; ;;;; Metal ;;;;;;;; ;; ;; Poly ;;;;;;;; Each square is μm x μm C E B S G D S00ES ;; pwell nsubstrate The g m of a BJT is given as g m = I C = I s exp(v V t V BE /V t ). Noting that I s is proportional to t the emitter area tells us that the way to double g m is to double the emitter area as shown. 2K N WI D The g m of the MOSFET is given as. g L m can only be doubled by quadrupling the Wi/L ratio. Since there is not enough room to make W 4 times larger, we make L four times smaller as shown. (b.) If the dc currents in both NPN BJT and NMOS MOSFET are equal and 00A, find the W/L ratio of the MOSFET that will make the smallsignal transconductance of the MOSFET equal to the BJT. Assume that the large signal parameters for these transistors are o = 00, V t = 0.026V, K N = 00A/V 2 and V T = 0.7V (ignore the bulk effect and assume that V A = and N = 0). To make the transconductances equal means that 2K N WI D L = I C V t W L = I D 0 = 4 2K N V t 04 0.0262 = 479

Practice Problems (5/27/07) Page 9 CURRENT MIRRORS Problem (044430E3P2) A CMOS : current mirror layout is shown. Assuming both transistors are in saturation and that V DS = V DS2. a.) If I in = 00μA, the value of I out should be 00μA. Due to the layout, find the actual value of I out. Use the information in the table for a typical CMOS process on the front page of this exam and assume that K = 00μA/V 2 and V T = 0.5V. b.) How would you improve the error caused by the layout? I IN I OUT IN OUT : n diffusion n diffusion Polysilicon Su04E3P2A a.) We can see from the layout that the source bulk resistances are not equal. Designating these resistors as R S for M and R S2 for M2, we can find the values as follows. R S = 35/sq.(0.5 0.5 0.2) = 77 and R S2 = 35/sq.(0.5 0.2) = 24.5 n diffusion One square is μm x μm Therefore the current mirror can be modeled as, Thus, I IN I OUT 2 00μA 200μA/V 2 5 V T 00μA(77) M V GS R S V GS2 M2 R S2 2 I OUT = 200μA/V 2 5 V T 24.5 I OUT Assuming the V T s cancel, gives 0.64056 = 63.2456 I OUT 24.5 I OUT Su04E3S2 or I OUT 2.5845 I OUT 0.02629 = 0 I OUT =.290726 ±.3008 = 0.0008 I OUT = 02μA GRD Su04E3P2 b.) Move the GRD contacts and metal to the left 0 microns so that R S = R S2.

Practice Problems (5/27/07) Page 0 Problem 2 (044430E3P4) Four different layouts for a CMOS :2 current mirror are shown. a.) Show how to connect the n regions and the poly regions to form the current in mirror in each layout. Label the IN, OUT, and GRD nodes. (Just draw a line from the region to wherever to indicate the connection.) b.) Which of the four layouts has the most accurate current gain? Why? c.) Which of the four layouts is has the least accurate current gain from physical parasitic considerations? Why? a.) See below. IN 5 M OUT M2 0 GRD IN OUT 5 0 5 3 3 3 3 3 3 M M2 M2A GRD Layout OUT IN OUT 3 3 5 3 5 3 M M2B Layout 2 GRD Contacts Poly IN OUT OUT 5 3 3 3 3 5 3 3 3 n diffusion 3 3 3 GRD M2A M M2B M2A Su04E3S4 M GRD M2B Layout 3 Layout 4 b.) Layout 4 is the most accurate because it uses a common centroid geometry, all gates are oriented in the same direction and it uses the replication principle. 5 IN 5 OUT c.) Layout 3 is the least accurate due to physical parasitics. The bulk source resistors of M and M2A are different than M2B. Also, the bulkdrain capacitors of M and M2B are different than M2A.

Practice Problems (5/27/07) Page DIFFERENTIAL AMPLIFIERS Problem (04642E3P4) A differential CMOS amplifier using depletion mode V DD input devices is shown. Assume that the normal M3 M4 MOSFETs parameters are K N =0V/μA 2 0μm/μm, V TN = V BiasP 0.7V, N =0.04V and for the PMOS transistors are K P =0V/μA 2, V TP = 0.7V, P =0.04V. For the v M depletion mode NMOS transistors, the parameters are 00μm/μm the same as the normal NMOS except that V TN = M2 v 2 0.5V. (a.) What is the maximum input commonmode voltage, V icm (max)? (b.) What is the minimum M5 00μA V BiasN 00μm/μm input commonmode voltage, V icm (min)? (c.) What S02FEP8 value of V DD gives an ICMR = 0.5V DD? (a.) V icm (max) = V DD V SD3 (sat) V DS (sat) V GS (50μA) i D = 2 (V GS V T )2 V GS = 2i D V T = V DS (sat) V T V icm (max) = V DD V SD3 (sat) V T = V DD 2I D3 3 V T V icm (max) = V DD 0.305 0.5 = V DD 0.805 (b.) V icm (min) = V DS5 (sat) V GS (50μA) = V DS5 (sat) V DS (sat) V T V icm (min) = 2I D5 5 2I D V T = 0.348 0.0953 0.5 = 0.2698V (c.) ICMR = V icm (max) V icm (min) = V DD 0.805 0.2698 = V DD 0.537 V DD 0.537 = 0.5V DD V DD = 2(0.537) =.063V

Practice Problems (5/27/07) Page 2 Problem 2 (03642EP3) Find the numerical values of all roots and the midband gain of the transfer function / of the differential amplifier shown. Assume that K N = 0μA/V 2, V TN = 0.7V, and N = 0.04V. The values of C gs = 0.2pF and C gd = 20fF. A smallsignal model appropriate for this circuit is shown. 2 C gs C gd v R L C out L g m v gs r ds 2 Fig. S03ES4 Summing the currents at the output nodes gives, g m v gs sc gd ( ) (g ds G L ) sc L = 0 (Note: we are ignoring the fact that and should be divided by two since it makes no difference in the results and is easier to write.) Replacing v gs by gives (g m sc gd ) = [(g ds G L ) sc L sc gd ] = (g m sc gd ) s(c L C gd ) (g ds G L ) = g m g ds G L R L = 0kΩ C L =pf sc gd g m s C L C gd g ds G L M 00/ V DD M2 00/ ma R L = 0kΩ C L =pf S03EP4 MGB = g m (r ds R L ), Zero = g m C gd and Pole = g ds G L C gd C L g m = 2 0 00 500 = 336.7μS and r ds = 25 I = D 500μA = 50 k MGB = 3.367mS (0k 50k) = 27.64 V/V Zero = 3.367x03 20x0 5 =.658x0 radians/sec. Pole =.02x0 2 (0k 50k) =.76x08 radians/sec.

Practice Problems (5/27/07) Page 3 Problem 3 (02642FE3) A current mirror load, CMOS differential amplifier is shown. The current in M5 is 00μA. Assume the parameters of the NMOS transistors are K N =0V/μA 2, V TN = 0.7V, N =0.04V and for the M3 V DD M4 PMOS transistors are K P =0V/μA 2, V TP = 0.7V, P =0.04V. (a.) Find the smallsignal output resistance and voltage gain if the W/L ratio of M and M2 is 00μm/μm. (b.) If the W/L ratio of M3 and M4 is 50μm/μm and C ox = 24.7x0 4 F/m 2, and the effective output capacitance is pf, find all roots of this amplifier (ignore the influence of C gd4 ). (c.) What is the 3dB frequency in Hertz? The smallsignal model suitable for this problem is shown below. G V G2 D=G3=D3=G4 D2=D4 id V gs V gs2 C3 gmv gs gm3 V out gm2v rds2 C gs2 rds4 C2 V gm4v S=S2=S3=S4 S02FES4 C = 2(0.667)(50x0 2 m 2 )(24.7x0 4 F/m 2 ) = 0.647pF g m3 = 2 50 50 50 = 500μS V out = (g m4 V g m2 V gs2 )Z out = g m4 g m V gs g g m3 sc m2 V gs2 Z out = s C g m V in g m2 V in 2 2 sc L g ds2 g ds4 g m3 = g md s C 2 g m3 s C g m3 sc 2 g ds2 g ds4 V in 2 = g md s C 2g m3 s C g m3 sc 2 g ds2 g ds4 The smallsignal ourput resistance and voltage gain is, 0 R out = = 6 g ds2 g ds4 50 (0.050.04) = 222k A vd = g m R out g m = g m = 2 0 00 50 =.049mS A vd = g m R out = (.049)(222) = 233V/V g m3 The roots are, p = C = 500μS 0.647pF = 3.036x09 rps, z = 2p = 6.072x0 9 rps, and p 2 = M M2 VBias g ds2 g ds4 C = 2 222k pf = 4.504x06 rps f 3dB = 4.504x06 2 = 77kHz V SS M5 V in pf SO2FEP3

Practice Problems (5/27/07) Page 4 Problem 4 (05642E2P2) The CMOS equivalent of a 74 op amp input stage is shown. If the transistor model parameters are K N = 300μA/V 2, V TN = 0.5V, N = 0.02V and K P = 70μA/V 2, V TP = 0.5V, P = 0.04V find the numerical values of R i, G m, and R o for this input stage if all W/L s of every transistor are 0. V DD The smallsignal model for this problem is shown. First find the M9 M8 smallsignal model parameters: g m = g m2 = 2 300 0 5 =300μS g m3 = g m4 = 2 70 0 5 =45μS r ds = r ds2 = r ds5 = r ds6 = 50/5μA = 3.33M and r ds3 = r ds4 = 25/5μA =.67M Summing currents: v id 2 30μA M M3 M5 V SS M2 M4 M6 v o v id 2 v id R i R o v o G m v id S05E2P3 g m v gs v gs3 r v gs3 ds r g ds3 m3 v gs3 = 300v gs 0.3v gs 0.6v gs3 45v gs3 = 0 300.3v gs 45.6v gs3 = 0 v gs = 0.485v gs3 Voltage loop through M and M3: 0.5g m v id = v gs v gs3 =.485v gs3 v gs3 = 0.337v id v id 2 i d3 M3 M g m v gs r ds r ds3 i d3 v gs3 g m3 v gs3 S05E2S3 i d3 g m3 v gs3 = 0.337 45μSv id = 48.82μS v id G m v id = (i d3 i d4 ) = 97.65μS v id G m = 97.65μS R i = Ouput resistance: R o = r ds6 [(/g m2 )g m4 r ds4 ] = 3.33M 0.807M = 0.650M

Practice Problems (5/27/07) Page 5 OUTPUT AMPLIFIERS Problem (05642EP) An emitter follower, pushpull output stage is shown. Assume that N = P = 00, V t = 25mV, and I s = 0fA. a.) If the emitter areas of Q and Q2 are 0μm 2, find the emitter area of Q3 and Q4 so that the collector current in Q3 and Q4 is ma when v IN = v OUT = 0. b.) What is the ±peak output voltage of this amplifier? Assume the 00μA sources can have a minimum voltage across them of 0.2V. c.) What is the ±slew rate of this amplifier in V/μs? d.) What is the smallsignal input and output resistance of this amplifier when v IN = v OUT = 0? (Do not include the load resistance in the output resistance.) v IN 00μA R in 00μA I 2 C a.) V EB V BE2 = V BE4 V EB3 I s I = I C3 2 s2 I s3 I I s4 s3 = I s4 = I C3 I s I = 0I C s A E3 = A E4 = 0A E = 00μm 2 b.) V peak = ±(00μA)( o )R L = ±00μA 0 00 = ±.0V Check to make sure this answer is okay. V BE4 = V t ln 0.mA 0fA = 0.69V Maximum swing is 20.690.2 =.09V so V peak = ±.0V Q2 Q 2V 2V Q4 R out Q3 00pF 00Ω S05EP vout c.) ±SR = 0.mA 00pF = 0V/μs d.) Small signal model: V t = I t 2 g r m2 4 R L I t ( o ) g m2 = 00μA 25mV = 250 g m4 = ma 25mV = 25 R in V t I t /gm2 rπ4 i b4 /g m rπ2 = 0.5[250250)] 0(00) =.487k i b3 βi b4 R L βi b3 S05ES R out = 0.5 g /g m2 m4 = 0.5[25 (250/0)] = 3.37 o

Practice Problems (5/27/07) Page 6 Problem 2 (05642EP2) Find the value for the smallsignal output resistance R out ignoring R L and the value of the smallsignal input resistance for the amplifier shown. Let the dc currents through M and M2 be 500μA, W /L = 00μm/μm and W 2 /L 2 = 200μm/μm. Assume the parameters of the NMOS transistors are K N =0V/μA 2, V TN = 0.7V, and for the PMOS transistors are K P =50V/μA 2, V TP = 0.7V. Ignore r ds and r ds2. Calculating the smallsignal parameters gives, g m = 2 0 500 00 = 3.36mS, g m2 = 2 50 500 200 = 3.62mS The smallsignal model is given as, R i t R 2 i t v t v gs gm v gs g m2 v gs v t R L For R out, sum the currents at the output (with the LH v t =0) to get, v IN R in S05EP2 R = 0kΩ S05ES2 2.5V R 2 = 0kΩ 2.5V M2 R out R L = kω M v OUT i t =v tr R g m g m2 2 2 R out = v t i = t R R g m g m2 2 2 = 308 For R in, remove the RH v t and write a loop equation at the input to get, v t =i t (R R 2 ) (i t g m v gs g m2 v gs )R L = i t (R R 2 R L ) (g m g m2 )v gs But v gs = v t i t R which gives, R in = v t i = R R 2 R L (g m g m2 )R L R t (g m g m2 )R = 20k(3.363.62)()(00k) L (3.363.62)() R in = 3.5k

Practice Problems (5/27/07) Page 7 Problem 3 (05642E3P) A simple amplifier consisting of two cascaded CMOS inverters is shown. By using one transistor (either NMOS or PMOS) and ideal current sources and batteries as necessary, show how you would reduce the output resistance to as small as possible. Estimate the output resistance of your circuit assuming that all transistors (those in the amplifier and the one you use) have the same value of g m and r ds. Further assume, that the CMOS inverters are operating in class AB. There are two possibilities which will be examined below. V DD M2 M V DD M4 M3 R out S05E3P2 V DD V DD V DD V DD V DD M2 M4 R out M2 M4 R out M V DD M3 M M3 M5 M5 S05E3S2A S05E3S2B R out (no fb.) = 0.5r ds Loop gain g m r ds R out (fb.) 0.5r ds g m r = ds 2g m R out (no fb.) /g m Loop gain 2 g m ( r ds /3) = 0.667 g m r ds R out (fb.) /g m 0.667g m r ds = 3 2g 2 m r ds Therefore, the solution on the right has a low resistance by the amount of 3/g m r ds.

Practice Problems (5/27/07) Page 8 Problem 4 (05642FE3) A source follower, pushpull output stage is shown. Assume the parameters of the NMOS transistors are K N =0V/μA 2, V TN = 0.7V, N =0.04V and for the PMOS transistors are K P =50V/μA 2, V TP = 0.7V, P =0.05V. 00µA R in M2 2V M4 R out a.) If W /L = W 2 /L 2 = 0, find the W 3 /L 3 and W 4 /L 4 so that the drain current in M3 and M4 is ma when v IN = v OUT = 0. v IN M M3 00pF 00Ω vout b.) What is the ±peak output voltage of this amplifier? Assume the 00μA sources can 00µA have a minimum voltage across them of 0.2V. c.) What is the ±slew rate of this amplifier in V/μs? 2V S05FEP3 d.) What is the smallsignal input and output resistance of this amplifier when v IN = v OUT = 0? (Do not include the load resistance in the output resistance.) a.) With v IN = v OUT = 0, the W/L ratios of M3 and M4 are given by the current ratios. Thus, W 3 /L 3 = W 4 /L 4 = 00. b.) The current limit due to ma is ±V. Check to see if voltage limit is less. V GS4 (ma) = 2 ma 0 00 0.7 = 0.426 0.7 =.26V V out (max) = 2 0.2.26 = 0.674V V GS3 (ma) = 2 ma 50 00 0.7 = 0.632 0.7 =.332V V out (min) = 2 0.2.332 = 0.467V c.) The slew rate is ±SR = ma 00pF = 0V/μs d.) R in =. R out = g m3 g m4 g m4 = 2 0 000 00 μs = 4.69mS g m3 = 2 50 000 00 μs = 3.62mS R out = 000 3.62 4.69 = 27

Practice Problems (5/27/07) Page 9 Problem 5 (04642EP) A pushpull follower is shown with a 500 load. Assume that the MOSFETs have the following model parameters:. K N = 00μA/V 2, V TN = 0.5V, and K P = 50μA/V 2, V TP = 0.5V. Ignore the bulk effects and assume = 0. a.) Find the small signal voltage gain and the output resistance (not including R L ) for the conditions of part a.) if the dc current in M and M2 is 00μA. b.) What is the output voltage when v IN = 0.5V? a.) The smallsignal model is given as shown where g m = 2K N '(W /L )I D = 2 00 50 00 g m = ms, g m2 = 2 50 00 00 = ms Summing currents at the output node gives, g m ( ) g m2 ( ) = G L 0.7V v IN 0.7V S04EP M M2.5V 50 00.5V R L = 500Ω g m ( ) g m2 ( ) v OUT R L = 500Ω S04ES = g m g m2 g m g m2 G L = 2 = 0.5V/V and R out = g m g m2 = 2mS = 500 b.) Under the condition of v IN = 0.5V, the gate voltages are V G = 0.5V0.7V =.2V and V G = 0.5V0.7V = 0.2V We know that the output voltage can be expressed as V OUT = (I I 2 )0.5k where I andi 2 are the dc currents in M and M2. Next we need to make an assumption about the operating region of the two transistors. Let us assume that M is saturated and M2 is cutoff. Therefore, I 2 = 0 and I = 0.5(00)(50)[.2V OUT 0.5)] 2 (μa) = 2.5(0.7V OUT ) 2 (ma) V OUT = (I )0.5k =.25(0.7V OUT ) 2 2 0.8V OUT = 0.49.4V OUT V OUT The resulting quadratic, V OUT 2 2.2V OUT 0.49 = 0 gives V OUT =.9±0.5 2.2 2 4(0.49) =. ± 0.5(2.880) =.±0.845 = 0.252V Check the regions of M and M2. M: V DS =.50.252 =.25V >V GS V TN =.20.5 = 0.7 M is saturated. M2: V SG2 = 0.252 (0.2) = 0.452 < V TP = 0.5 M2 is cutoff

Practice Problems (5/27/07) Page 20 Problem 6 (04642FE) An output stage is shown. Assume the parameters of the NMOS transistors are K N =0A 2 /V, V TN = V DD V DD 0.7V, N =0.04V, the PMOS transistors are K P =50V/A 2, V TP = 0.7V, P =0.05V and the lateral npn BJT has a current gain of F = 50 and V t = 25mV. Find the smallsignal output resistance (not including R L ), the smallsignal voltage gain (ignore the bulk effect on M), and the large signal slew rate (plus and minus) if a 0pF capacitor is connected to the output. 50μA M V SS 0 0μA 500μA V SS Q2 0pF R L = 00Ω F04FESA Model parameters: M: g m = 2 40 0 50 = 0.2mS Q2: g m2 = 500A 25mV = 20mS and r 2 = 5 20mS = 2.55k Smallsignal model: v gs g m v gs R out = r 2 (/g m ) = i b i b v gs v gs = 2.55K5K 5 = 48 = [()R L ](g m ) g m [r 2 ()R L ] = g m [()R L ] g m [r 2 ()R L ] = 0.2mS 0 00 0.2mS(2.55k5.k) =.20 2.53 = 0.403V/V Slew rates: SR = v s SR = 500A 0pF i b r π2 βi b 50A(5) 50A 0pF R L = 50 V/s S04FES = 205 V/s

Practice Problems (5/27/07) Page 2 Problem 7 (03642EP) Find an algebraic expression for the voltage gain, /, and the output resistance, R out, of the source follower shown in terms of the smallsignal model parameters, g m and R L (ignore r ds ). If the bias current is ma find the numerical value of the voltage gain and the output resistance. Assume that K N = 0μA/V 2, V TN = 0.7V, and K P = 50μA/V 2, V TP = 0.7V. A smallsignal model for this circuit is shown below neglecting r ds of the transistors. 3V / 00/ M2 M3 M 00/ ma R out Widths and lengths are in microns. R L = 50Ω S03EP g m v gs g m3 v gs3 g m2 v gs3 RL Fig. S03ES it Summing currents at the output node gives, g m v gs = g m3 v gs3 G L Also, v gs3 = g m v gs (/g m2 ) g m v gs = g m3 g m g v m2 gs G L g m v gs g m3 g = G m2 L g m ( ) g m3 = G L = g m g m3 g m2 g m g m3 G L g m2 g m2 Setting = 0 and applying i t and solving for and ignoring R L gives, g m i t = g m3 v gs3 g m = g m3 g v m2 out g m i t = R out = g m g m3 g m2 Note that the ma splits between M(M2) and M3 in a ratio of to 00. Therefore, I D = I D2 = 9.9μA and I D3 = 990.μA. g m = 2 0 00 9.9 = 466.7μS, g m2 = 2 50 9.9= 3.47μS and g m3 = 2 0 00 990. = 346.7μS 466.7 0 v = in 466.7 0 /50 = 47.37 47.37 20 = 0.702 V/V R out = 000 47.37 = 2.2

Practice Problems (5/27/07) Page 22 Problem 8 (03642EP3) a) For the emitter follower output stage shown below, find the value of R for maximum efficiency and find the value of that efficiency. V CC =V EE =2.5V, V CE (sat)=0.2v, R L =0k, V BE (on)=0.7v. b) A load capacitor of 00pF is attached to the output voltage. If the input voltage suddenly drops from 2.5V to 2.5V, explain what happens at the output and accurately sketch the output voltage as a function of time, specifying its initial and final values and times. i IN v IN R Q3 I Q V CC Q i OUT R L Q2 v OUT The I Q for maximum efficiency is found as, I Q = V V (sat) CC CE =230μA R L R = V V EE BE =7.826k I Q P L (max) = V V (sat) CC CE I Q = 0.5(2.3V)(0.23mA) = 0.2645mW 2 2 P supply = 2V CC I Q = 2(2.5)(0.23mA) =.5mW = P L(max) = P supply 4 V CE (sat) =23% V CC V EE Fig. 04009 b) The output would slew under such condition. The current will be limited by the bias current: Slew rate=0.23ma/00pf=2.3v/μs.8v Vout.78s t 2.3V

Practice Problems (5/27/07) Page 23 Problem 9 (02642EP) Six versions of a source follower are shown below. Assume that K' N = 2K' P, P = 2 N, all W/L ratios of all devices are equal, and that all bias currents in each device are equal. Neglect bulk effects in this problem and assume no external load resistor. Identify which circuit or circuits have the following characteristics: (a.) highest smallsignal voltage gain, (b.) lowest smallsignal voltage gain, (c.) the highest output resistance, (d.) the lowest output resistance, (e.) the highest (max) and (f.) the lowest (max). M M2 M M2 M V BP M2 V DD vout M2 M vout M2 M M2 M V BN V SS Circuit Circuit 2 Circuit 3 Circuit 4 Circuit 5 Circuit 6 FS02EP (a.) and (b.) Voltage gain. Small signal model: The voltage gain is found as: g m G L = g m G g m g L m v out where G L is the load conductance. Therefore we get: Circuit 2 3 4 5 6 g mn g mp g mn g mp g mn g mp g mn g mn g mp g mp g mn g mp g mp g mn g mn g dsn g dsp g mp g dsn g dsp But g mn = 2 g mp and g dsn = 0.5g dsp, therefore Circuit 2 3 4 5 6 0.5858 0.442 g mp g mp 2 2 g mp (g dsp g dsn )/ 2 g mp g dsp g dsn Thus circuit 5 has the highest gain and circuit 4 the lowest gain (c.) and (d.) Output resistance. The denominators of the first table show the following: Circuit 6 has the highest output resistance and circuit the lowest output resistance. (e.) Assuming no current has to be provided by the output, circuits 2, 4, and 6 can pull the output to V DD. Circuits 2 and 4 and 6 have the highest output swing. (f.) Assuming no current has to be provided by the output, circuits, 3, and 5 can pull the output to ground. Circuits and 3 and 5 have lowest output swing. Summary (a.) Ckt. 5 has the highest voltage gain (d.) Ckt. has the lowest output resistance (b.) Ckt. 4 has the lowest voltage gain (e.) Ckts. 2,4 and 6 have the highest output (c.) Ckt. 6 has the highest output resistance (f.) Ckts.,3 and 5 have the lowest output

Practice Problems (5/27/07) Page 24 Problem 0 (02642EP2) An output stage using both MOSFETs and a BJT is shown. 2V Assume the transistor parameters are K N = 0μA/V 2, V T = 0.7V, and N = 0.04V for the NMOS; K P = 50μA/V 2 0 0, V T = 0.7V, and P = 0.05V for the PMOS and F = 00, M3 M4 Q R out V t = 0.025V, and I s = 0fA for the NPN BJT. (a.) If can 00μA i out vary between ±2V, what is the maximum positive and M 0 M2 negative value of i out when R L = 0? (b.) If can vary 0 between ±2V, what is the maximum and minimum output voltage when R L = 00? 2V S02EP2 (a.) The maximum i out occurs when = 2V. All of the 00μA through M4 is base current giving a maximum i out = ()00μA = 0.mA i out (max) = 0.mA The maximum i out occurs when = 3V. Since V DS = 2V and V GS V T = 3.3V, M2 is in the triode region. Under these conditions, we assume M absorbs all of the 00μA of M4 and therefore the BJT is off and maximum i out is, i out (max) = K N 'W L [(V GS2 V T )v DS 0.5v DS 2 ] = 0 0[3.3 2 0.5(2)2 ] = 5.06mA i out (max) = 5.06mA (b.) There are 2 possible answers for the maximum. The current limited max. is Max. = i out (max)r L = 0.mA 0.k =.0V The voltage limited (max) is, Max. = 2V V SD4 (sat) V BE (0.mA) = 2 2 00 50 0 0.025ln 0mA 0fA = 20.63250.6908 = 0.6768V Max. = 0.6768V For the maximum we see that the V GS2 = 4V which strongly suggests that M2 will be in the triode region. Equating the current in the 00 resistor with that in M2 gives, 2v DS 00 = K N 'W L [(V GS2 V T )v DS 0.5v DS 2 ] 0.02 0.0v DS =.x0 3 [3.3v DS 0.5v DS 2 ] v DS 2 24.782v DS 36.36 = 0 v DS = 2.39±0.8247 v DS =.5662V Max. = 2V.5662V = 0.4338V The current through M2 under this condition is 0 0 2 (.5662V)2 =.349mA It can be shown that if M2 remains saturated that Max. = I 00 = 0.85V So our assumption that M2 was in the triode region is valid. R L

Practice Problems (5/27/07) Page 25 Problem 0 (0642E2P3) A CMOS circuit used as an output buffer for an OTA is shown. Find the value of the small signal output resistance, R out, and from this value estimate the 3dB bandwidth if a 50pF capacitor is attached to the output. What is the maximum and minimum output voltage if a k resistor is attached to the output? What is the quiescent power dissipation of this circuit? Use the following model parameters: K N =0μA/V 2, K P = 50μA/V 2, V TN = V TP = 0.7V, N = 0.04V and P = 0.05V. Use feedback concepts to calculate the output resistance, R out. R out = R o LG where R o is the output resistance with the feedback open and LG is the loop gain. R o = The loop gain is, g ds6 g ds7 = ( N P )I 6 = LG = = 2 g m2 g m6 g m g m9 g m4 0 6 0.09 500 = 22.22k g m7 g m = g m2 = 2 0 50 0 = 33.67S, g m3 = g m4 = 2 50 50 0 = 223.6S, g m6 = 2 50 00 500 = 2236S and g m7 = 2 0 500 00 = 336.7S LG = = 2 33.67 2236 33.67 336.7 223.6 33.67 = 73.68V/V R o V DD = 3V 0/ 0/ 0/ 00/ M8 M3 50A M4 M6 500A M 50A R M2 out 0/ 0/ 50A M5 500A M9 00A M7 0/ 00/ V Bias W/L values in microns V SS = 3V S0E2S3 R out = R o LG = 22.22k 73.68 = 294.5 f 3dB = 2 R = out 50pF 2 294.5 50pF = 0.8MHz To get the maximum swing, we must check two limits. First, the saturation voltages of M6 and M7. 2 000 V ds6 (sat) = 50 00 = 0.6325V and V ds7 (sat) = 2 000 0 00 = 0.4264V Second, the maximum current available to the k resistor is ±ma which means that the output swing can only be ±V. Therefore, maximum/minimum output = ±V. P diss = 6V(650μA) = 3.9mW

Practice Problems (5/27/07) Page 26 Problem (0642FEP) An output amplifier is shown. Assume that v IN can vary from 2.5V to 2.5V. Let K P = 50μA/V 2, V TP = 0.7V, and P = 0.05V. Ignore bulk effects. a.) Find the maximum value of v OUT, v OUT (max). b.) Find the minimum value of v OUT, v OUT (min). c.) Find the positive slew rate, SR when v OUT = 0V in volts/microseconds. d.) Find the negative slew rate, SR when v OUT = 0V in volts/microseconds. e.) Find the small signal output resistance (excluding the 0k resistor) when v OUT = 0V. a.) When v IN = 2.5V, the transistor is shut off and v OUT (max) = 200A 0k = 2V b.) When v IN = 2.5V, the transistor is in saturation (drain = gate) and the minimum output voltage under steadystate is, v OUT = 0k(I D 200A) = 0k 50 300 (v 2 OUT 2.50.7) 2 200A v OUT = 75(v OUT.8) 2 2 v 2 OUT 3.633v OUT 3.2333 = 0 v OUT = 3.6333 (3.6333) ± 2 4 3.2333 =.80667 ± 0.2259 2 2 It can be shown that the correct choice is v OUT (min) =.80667 0.2259 =.585V c.) The positive slew rate is SR = 200A 50pF = 4V/s SR = 4V/s d.) The negative slew rate is found as follows. With v OUT = 0V, the drain current is I D = 7.5mA/V 2 (2.50.7) 2 = 24.3mA Therefore, the sourcing current is 24.3mA0.2mA = 24.mA which gives a negative slew rate of SR = 24.mA 50pF = 482V/s SR = 482V/s e.) The output resistance, R out, is approximately equal to /g m. Therefore, R out g m = L 2K P I D W = 2 50 200 300 = 408.2 R out 408

Practice Problems (5/27/07) Page 27 SMALL SIGNAL FREQUENCY RESPONSE Problem (05642EP3) Find the midband voltage gain and the 3dB frequency in Hertz for the circuit shown. R =kω C 2 =pf V in C = V R V 2 = C 3 = V 2 R V 3 = C 4 = Vout 0pF 000 00kΩ 5pF 2 000 kω 0pF S05EP3 The midband voltage gain can be expressed as, V out V = V out V 2 V in V 2 V V = in () R 2 R 2 000 () = 0.99V/V Finding the opencircuit, time constants: R CO : R CO = R = k R CO C = 0ns R C2O : v t = R i t R 2 i t V 000 V 2 000 But v t = V V 2 and V = R i t, v t = R i t R 2 i t 2R R 2 i t 000 R 2 v t 000 i t v t R V V 000 i t R 2 V 2 000 V 2 S05ES3 R C2O = v t i t = R R 2 0.002R R 2 0.00R 2 = k00k200k 00 = 2.98k R C2O C 2 = 2.98ns R C3O : R C3O = R 2 k = 0.99k R C3O C 3 = 4.95ns R C4O : R C4O = R 3 = k R C4O C 4 = 0ns T oc = (02.984.950)ns = 27.93ns 3dB T oc = 35.8x0 6 f 3dB = 5.698 MHz

Practice Problems (5/27/07) Page 28 Problem 2 (05642EP4) On page 54 of the text, the V CC statement is made that the common base input impedance is R L low at low frequencies and Z in Z in R 2 becomes inductive at high frequencies... Find the smallsignal input impedance to the E R L I common base amplifier and express the values of the S05EP4 equivalent circuit, R, R 2, and L in terms of the parameters of the BJT small signal model (r b, r, C, and ). Ignore r o and assume that R >R 2. Use the following small signal model for this problem. and I t V Z g m V = 0 I t = V g m Z V t = V V Z r b V t = V r b Z Z in = V t I = Z r b t g r m Z where Z = sc r Now, r b Z in = r sc r g m r sc r V t = r b (sc r ) r g m r sc r = (r b r )sc r r b o sc r Z in I t C π Vπ r b g m V π r π S05ES4 = (r b r ) o sc r r b (r b r ) o o sc r r b o o sc r = o r b r b o sc r r b o r b (r b r ) o sc r r b o r b sc r r b o r b Z in = R (R 2 sl) R R 2 sl R (R 2 sl) R sl if R >R 2 Equating the two expressions for Z in gives, R = r b, R 2 = (r b r ) o, and L = C r r b o

Practice Problems (5/27/07) Page 29 Problem 3 (05642FE6) Find the midband voltage gain and the 3dB frequency in Hertz for the circuit shown. V in R =kω C = 0pF C 2 =pf V R V 2 = 00 00kΩ C 3 = 5pF The midband voltage gain can be expressed as, V out V = V out V 2 V in V 2 V V = in (0) R 2 R 2 000 () = 9.9V/V V 2 R V 3 = 2 00 kω C 4 = 0pF S05FEP6 Vout Finding the opencircuit, time constants: R CO : R CO = R = k R CO C = 0ns R C2O : v t = R i t R 2 i t V 00 V 2 00 But v t = V V 2 and V = R i t, v t = R i t R 2 i t 2R R 2 i t 00 R 2 v t 00 i t v t R V V 000 i t R 2 V 2 000 V 2 S05ES3 R C2O = v t i t = R R 2 0.02R R 2 0.0R 2 = k00k2000k 000 = 2.099k R C2O C 2 = 2.ns R C3O : R C3O = R 2 00 = 99.9 R C3O C 3 = 0.5ns R C4O : R C4O = R 3 = k R C4O C 4 = 0ns T oc = (02.0.50)ns = 22.6ns 3dB T oc = 44.25x0 6 f 3dB = 7.04 MHz

Practice Problems (5/27/07) Page 30 Problem 4 (04642EP3) Find the voltage transfer function of the commongate amplifier shown. Identify the numerical values of the smallsignal voltage gain, /, and the poles and zeros. Assume that I D = 500μA, K N = 00μA/V 2, V TN = 0.5V, and K P = 50μA/V 2, V TP = 0.5V, 0V, C gs = 0.5pF and C gd = 0.pF. The small signal transconductance is, g m = 2 K N (W/L)I D = 2 00 0 500 = ms r ds = The small signal model is, R s C gs g m v gs vgs C gd RL S04ES3 V Bias R D = 0kΩ R S = kω S04EP3 V DD 0 I D The voltage gain can be expressed as follows, V out V out V gs V = in V gs V, in Sum currents at the source to get, V out V gs = g m R L (/sc gd ) R L (/sc gd ) V in V gs R s g m V gs sc gs V gs = 0 V gs V in = G s G s g m sc gs V = in g m R L g m R L sc gd R L sc gs g m G s V out The various values are, Voltage gain = p = g m R L g m R L = 0 = 5V/V C gd R = L 0 3 0 4 = 0 9 radians/sec. p 2 = (g m G s ) C gs = 03 0 3 0.5x0 2 = 4x0 9 radians/sec.

Practice Problems (5/27/07) Page 3 Problem 5 (02642EP3) Find the midband voltage gain and the 3dB frequency in Hertz for the circuit shown. R =kω C 2 =pf V in C = 0pF R 2 = 0kΩ The midband gain is given as, V out V R V 3 = 00 0kΩ V = 0k in 00 0k k = 90.9V/V C 3 = 0pF S02EP3 Vout To find the 3dB frequency requires finding the 3 opencircuit time constants. R C0 : R C20 : R C30 : R C0 = k 0k = 0.909k R C0 C = 0.909 0ns = 9.09ns v t = i t R C0 R 3 (i t 0.0V ) = i t (R C0 R 3 0.0R C0 R 3 ) R C20 = R C0 R 3 0.0R C0 R 3 = 0.909 0(0.0 909.)k = 0.82k R C20 C 2 = 0.82 ns =0.82ns R C30 = 0k R C30 C 3 = 0 0ns = 00ns T 0 = (9.09 0.82 00)ns = 20.9ns 3dB = T 0 = 4.74x0 6 rad/s f 3dB = 4.74x06 2 = 754.6kHz R c0 i t v t V V 00 S02ES3 R 3

Practice Problems (5/27/07) Page 32 Problem 6 (02642EP4) Find the midband voltage gain and the exact value of the two poles of the voltage transfer function for the circuit shown. Assume that R I = k, R L = 0K, g m = ms, C gs = 5pF and C gd = pf. Ignore r ds. R I V in S02EP4 The best approach to this problem is a direct analysis. Smallsignal model: R L V out R I g m V gs R I g m V s V in V gs C gs C gd RḺ Vout V in V s C gs C gd RḺ Vout S02ES4 V out = g m Z L V s where Z L = sr L C gd and V in V s R I = g m V s sc gs V s Solving for V s from the second equation gives, V in V s = g m R I sc gs R I Substituting V s in the first equation gives, V in V out = g m Z L g m R I sc gs R V out I V = g in m sr L C gd g m R I sc gs R I = g m R L g m R I sr L C gd sc gd R = MBG I g m R I s s MBG = g m R L g m R = 0 I = 5V/V p = R L C = gd 0 ns = 08 rad/s and p 2 = g m R I R I C = gs 5ns = 4x08 rad/s p p 2

Practice Problems (5/27/07) Page 33 COMPENSATION OF OP AMPS Problem (05642E2P2) If a twostage, Miller compensated CMOS op amp has a RHP zero at 5GB, a dominant pole due to the Miller compensation, and a second pole at p 2, find the value of the first stage transconductance (g mi ), the second stage transconductance (g mii ), and the value of the Miller capacitor, C c, if GB = 0MHz, the load capacitor is 0pF, and the phase margin is to be 50. Assume that the unity gain magnitude frequency is GB..) The phase margin gives p 2 which will give g mii. 80 90 tan GB p 2 tan (0.2) = 50 tan GB p 2 = 28.69 p 2 = GB 0.544 = 20MHz 0.544 = 5.5x06 rads/sec. We know that, p 2 = g mii C L g mii = p 2 C L = (5.5x0 6 rads/sec.)(0pf) =.55mS 2.) The Miller capacitor is found from the RHP zero location. g mii C = z c C c = g mii z =.5mS 5 GB =.5mS 0x0 7 = 3.55pF 3.) Finally, the input stage transconductance is given by, GB = g mi C c g mi = GB C c = (2x0 7 )(3.55pF) = 223μS

Practice Problems (5/27/07) Page 34 Problem 2 (04642E2P) A selfcompensated op amp has three higher order poles grouped closely around x0 9 radians/sec. What should be the GB of this op amp in Hz to achieve a 60 phase margin? If the low frequency gain of the op amp is 80dB, where is the location of the dominant pole, p? If the output resistance of this amplifier is 0M, what is the value of C L that will give this location for p? (Ignore any other capacitance at the output for this part of the problem). The key to this problem is to assume that the three closely grouped poles around x0 9 radians/sec. can be approximated as three poles at x0 9 radians/sec. Therefore, Phase margin = PM = 80 tan GB p 3 tan GB p H = 60 where p H is a pole at x0 9 radians/sec. Assuming that GB/ p is large then, we can write the above as, 80 90 3 tan GB p H = 60 30 = 3 tan GB p H GB p H = tan(0 ) = 0.763 GB = 0.763 p H = 76.3 Mradians/sec. GB = 28.06MHz 80dB 0,000 which gives p = GB A = 76.3x06 v 0 4 = 7,630 radians/sec. p = 2.806kHz The expression for p is p = R out C C L L = R out p =.763x0 4 07 = 5.672pF

Practice Problems (5/27/07) Page 35 Problem 3 (03642E2P2) A twostage, Miller compensated op amp has the following values: g mi = 00μS, g mii = 000μS, C c = 2pF, and C L = 0pF. a.) What value of nulling resistor, R z, will cancel the output pole? b.) If the output capacitance of the first stage is C I = pf, what is the phase margin in part a.) if R z is 5k. c.) If C L is increased to 20pF and R z = 5k, what is the new phase margin? a.) The zero is given as z = C c g and the output pole is p 2 = R mii z roots gives, R z = g mii C L C c C = c 000μS 2 2 = 6k b.) The pole due to R z is p 4 = Also, the GB is R z C = I 5k pf = 2x08 rads/sec. g mii C c. Equating these two GB = g mi C c = 00μS 2pF = 50x06 rads/sec. The phase margin is, PM = 80 90 tan GB p 4 = 90 tan 50 200 = 90 4 = 76 (You should assume that z still cancels p 2. If you do assume this, the answer is 7.2.) c.) The new phase margin is, PM = 80 90 tan GB p 2 tan 2GB p 2 tan GB p 4 z = g mii C L p 2 = g mii C L = 000μS 0pF = 00x06 rads/sec. = 000μS 20pF = 50x06 rads/sec. PM = 90 tan 50 50 tan 00 50 tan 50 200 = 90 43 63.43 4 = 57.52

Practice Problems (5/27/07) Page 36 Problem 4 (0642E2P2) The poles and zeros of a Miller compensated, twostage op amp are shown below. (a.) If the influence of p 3 and z are ignored, what is the GB in MHz of this op amp for 60 phase margin? (b.) What is the value of A v (0)? What is the value of C c if g m =g m2 =500S? (c.) If p 2 is moved to p 3, what is the new GB in MHz for 60 phase margin? What is the new C c if the input transconductances are the same as in (b.)? σ p 3 =200Mπ p 2 =20Mπ p =2Kπ z =200Mπ S0E2P2B (a.) The phase margin, PM, can be written as PM = 80 tan GB p tan 2 GB p tan 3 GB z 90 tan GB p = 60 2 tan GB p 2 = 30 GB = 0.5774 p 2 = 5.774MHz jω C c (b.) A v (0) = GB p = 5.774MHz khz = 5,774V/V g m = GB C C c = g m c GB = 500S 2 5.774x0 6 = 3.78pF (c.) The phase margin, PM, can be written as PM = 80 tan GB p 2 tan GB p 2 tan GB p 3 tan GB z 90 3 tan GB p 2 = 60 = 0 GB = 0.763 p 2 = 0.0763 00MHz = 7.63MHz C c = g m GB = 500μS 2 7.63x0 6 = 4.54pF

Practice Problems (5/27/07) Page 37 OP AMPS Problem (05642E2P) The CMOS op amp shown uses a complementary differential input stages to achieve a wider input voltage common mode range. Assume that all transistors are scaled from a X NMOS and PMOS that have been designed to have a smallsignal transconductance of 00μS and a channel conductance of μs at 25μA of current. Give your best estimate of the slew rate (V/μs), output resistance, R out, smallsignal voltage gain ( /v id ), and the gainbandwidth, GB, in MHz. M20 50μA M5 V DD X.5 X.5 X3 M7 M8 75μA 75μA 50μA M9 M2 25μA 25μA M0 V DD V T 2V DS (sat) 50μA 75μA M2 M3 M4 v id M M2 M3 M4 V T 2V DS (sat) 25μA 50μA M6 50μA 25μA 75μA M6 X.5 75μA M7 M8 25μA M v OUT M5 50μA 75μA M9 X.5 5pF S05E2SA The dc currents for v id = 0 are shown above. One can show that the maximum amount of current available to the output capacitor is twice the 50μA current sink/source or 00μA. Therefore, the slew rate is SR = 00μA/5pF = 20V/μs. The smallsignal voltage gain can be written by inspection as (note the M3M4M7M8 combination is used to recover the full differential output of both complementary input stages), v id = (g m g m2 )R out where g m = g m2 = 00μS R out [(r ds9 r ds4 )g m r ds ] (r ds8 g m4 r ds4 ) [(r ds3 r ds9 )g m5 r ds5 ] Scaling r ds for the currents gives, r ds9 = 000k/6 = 66.7k, r ds = 000k/5 = 200k, r ds8 = r ds4 = r ds9 = 000k/3 = 333.3k, r ds5 = 000k/2 = 500k

Practice Problems (5/27/07) Page 38 Problem (05642E2P) Continued Scaling g m for the currents gives, g m = 5 00μS = 223.6μS, g m4 = 3 00μS= 73μS, g m5 = 2 00μS= 4μS R out Now, [(67 000)(0.224)(200k)] [(333)(0.73)(333.3k)] [(333 000)(0.73)(500k)] R out = 6.390M 9.8M 7.62M = 3.768M v id = 200μS(3.768M) = 769 V/V The gainbandwidth is, GB = g m g m2 C L = 200μS 5pF = 40x06 rads/sec or 6.28MHz

Practice Problems (5/27/07) Page 39 Problem 2 (05642FE5) A twostage, BiCMOS op amp is shown. For.5V the PMOS transistors, the model parameters are K P =50μA/V 2, V TP = 0.7V and P = 0.05V 0/ 20/. For the NPN BJTs, the model 0/ M8 M5 parameters are F = 00, V CE (sat) = 0.2V, M7 50μA V A = 25V, V t = 26mV, I s = 0fA and n=. v (a.) Identify which input is positive and v 2 C c = 0/ 0/ 5pF which input is negative. (b.) Find the M M2 numerical values of differential voltage gain, A v (0), GB (in Hertz), the slew rate, SR, and W/L ratios Q6 the location of the RHP zero. (c.) Find the in microns numerical value of the maximum and Q3 Q4 minimum input common mode voltages. S0E2P.5V (a.) The plus and minus signs on the schematic show which input is positive and negative. (b.) The differential voltage gain, A v (0), is given as g m g m6 A v (0) = g ds2 g o4 g 6 g ds7 g o6 r ds2 = g m = g m2 = 2 50 25 0 = 58.S 20 = P I D 25A = 0.8M, r o4 = V A = 25V I C 25A = M, g m6 = I C = 00A V t 26mV = 3846S r 6 = F g m6 = 26k, r ds7 = GB = g m C c P I D = 20 00A = 0.2M and r o6 = V A I C = 25V 00A = 0.25M A v (0) = [58.(0.8 0.026)][3846(0.2 0.25)]= 3.888 427.36 =,659.6V/V = 58.S 5pF = 3.62x0 6 rads/sec GB = 5.0325MHz SR = 50μA 5pF = 0V/μs RHP zero = g m6 C c = 3.846mS 5pF = 769.24x0 6 rads/sec. (22MHz) (c.) The maximum input common mode voltage is given as 2 50 v icm = V CC V DS5 (sat) V SG =.5 50 0 0.7 2 25 = 0.8 0.4470.36 = 50 0 v icm = 0.0367V v icm =.5 V BE3 V T =.5 V t ln 25A 0fA 0.7 = 2.2 0.5626 =.6374V

Practice Problems (5/27/07) Page 40 Problem 3 (04642E2P2) Design the values of W for each of the transistors of the op amp shown assuming that the channel lengths of all transistors are μm. Also design the values of the bias voltages V BN and V BP. The transistor model parameters are K N = 300μA/V 2, V TN = 0.5V, and K P = 70μA/V 2, V TP = 0.5V. Ignore the bulk effects. Use the following constraints among the transistor widths: W =W 2, W 4 =W 5, W 6 = 0W 4, W 7 = 0W 5, W 8 =W 9, and W 0 =W =W 2 =W 3 Round the values of the transistor widths to the nearest integer that meets or exceeds the specifications. Do not use safety factors or worst case in your design. The op amp specifications assuming a load capacitance of 5pF are: V icm =0.75V, V icm = 0.25V, GB =200MHz, V out =0.5V, V out = 0.5V, SR = 00V/μs I Bias v IN.) SR = 00V/μs I out = C L SR = 5x0 2 08 = 500μA I 3 = 50μA 2.) V icm =0.75V V SG4 = V DD V icm V TN =.0 0.75 0.5 = 0.75V V ON3 = 0.75 0.5 = 0.25V W 4 L 4 = 2I 4 K N (V ON4 ) 2 = W 4 = W 5 = 2μm W 6 = W 7 = 20μm 3.) GB =200MHz or GB =400x0 6 rads/sec. M4 M M3 M5 M2 V V BP V BN V M7 M3 M9 M 50 70(0.25) 2 =.43 = 2 M6 M8 M0 M2 v OUT C L S04E2P2 GB = g m C L 0 g m = GB C L 0 = 400x06 5x0 2 0 = 628μS W 2 L = g m 2K N I = 6282 50 300 = 26.32 = 27 W = W 2 = 27μm 4.) V icm = 0.25V V DS3 = V icm V GS V SS 2 25 V GS = 300 27 0.5 = 0.5786V V DS3 = 0.25 0.5786 = 0.74V W 3 L 3 = 2I 3 K N (V ON3 ) 2 = 2 50 300(0.74) 2 =.34 = 2 W 3 = 2μm

Practice Problems (5/27/07) Page 4 Problem 3 (04642E2P2) Continued 5.) V out =0.5V V SD6 = 2 I 6 K N (W 6 /L 6 ) = 2 250 70 20 = 0.243V V SD8 = 0.256V W 8 L 8 = 2I 8 K P (V ON8 ) 2 = 2 250 70(0.256) 2 = 08.99 = 09 W 8 = W 9 = 09μm 6.) V out = 0.5V Let V DS0 = V DS2 = 0.25V W 2 L 2 = 2I 2 K N (V ON2 ) 2 = W 0 = W = W 2 = W 3 = 27μm 2 250 300(0.25) 2 = 26.67 = 27 6.) V BN = V ON0 V ON2 V TN V SS = 0.25V0.25V0.5VV = 0V V BN = 0V V BP = V DD V ON6 V ON8 V TP = V 0.25V 0.25V 0.5V = 0V V BP = 0V

Practice Problems (5/27/07) Page 42 Problem 4 (04642FE2) A differentialin, differentialout amplifier is V DD shown that eliminates the need for matching sinks and sources. Assume that all W/L values are equal and that each transistor has approximately M5 M6 M7 M8 the same current flowing through it. If all transistors are in the saturation region, find an v 3 v 4 algebraic expression for the voltage gain, /, v M2 M3 v 2 M M4 and the differential output resistance, R out, where = v 3 v 4 and = v v 2. R out is the resistance seen between the output terminals. Using the schematic approach to small signal V Bias M9A M9B M9C M9D S04FEP2 analysis, we apply /2 positively to M (M2) and negatively to M4 (M3). The resulting ac currents are shown on the schematic. At node, v 3, these currents flow out of a resistance whose value is r ds r ds5 to give v 3 as v 3 = g m g m3 2(g g m ds g ds5 ) = g ds g ds5 Similarly for v 4, we get v 4 = g m2 g m4 2(g g m2 ds2 g ds8 ) = g ds2 g ds8 g m g m2 g m g m2 v = in g ds g = ds5 g ds4 g ds8 The output resistance seen differentially is the sum of the resistances seen to ground which is R out = g ds g ds5 g ds4 g = r ds8 ds r ds5 r ds4 r ds8

Practice Problems (5/27/07) Page 43 Problem 5 (03642E2P) A CMOS op amp is shown. All W/L values of all transistors are 0μm/μm. Assume that K N = 0μA/V 2, K P = 50μA/V 2, V TN = 0.7V, V TP = 0.7V, N = 0.04V, and P = 0.05V. Find the low frequency differential voltage gain, /, the gainbandwidth, GB, the slew rate, SR, and the power dissipation, P diss if V DD = 2V. The smallsignal voltage gain can be expressed as, V DD M3 M4 M5 50μA M M2 M7 V BN2 5pF M8 00μA 50μA V BN All transistor W/Ls are 0μm/μm M6 V BP V BP2 Fig. S03EP = g m R out = g m2 R out * where R out [g m7 r ds7 (r ds4 r ds8 )] [g m6 r ds6 (r ds2 r ds5 )] Evaluating the small signal parameters, g m = g m2 = 2 0 0 50 = 33.7μS, r ds = r ds2 = (25/50)M = 0.5M g m6 = 2 50 0 00 = 36.2μS, r ds6 = (20/00)M = 0.2M r ds5 = (20/50)M = 0.33M, r ds4 = (20/50)M = 0.4M g m7 = 2 0 0 00 = 469μS, r ds7 = (25/00)M = 0.25M r ds8 = (25/50)M = 0.67M R out [469 0.25(0.4 0.67)] [36.2 0.2(0.5 0.33)]M = (3.796 6.644)M = 4.484 = 33.7 4.484 = 487 V/V GB = g m C L = 33.7x06 5x0 2 = 66.33x0 6 0.56MHz SR = 00μA C L = 00x06 5x0 2 = 20V/μs P diss = 2(50μA50μA50μA) = 500μW * This expression ignores the fact that about half the signal is lost due to the input resistances at the sources of M6 and M7 are at an r ds level.