Lecture 6: DC & Transient Response

Similar documents
Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response

EE5780 Advanced VLSI CAD

Lecture 4: DC & Transient Response

DC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.

5. CMOS Gate Characteristics CS755

DC & Transient Responses

EEE 421 VLSI Circuits

CPE/EE 427, CPE 527 VLSI Design I Delay Estimation. Department of Electrical and Computer Engineering University of Alabama in Huntsville

Lecture 12 CMOS Delay & Transient Response

MOS Transistor Theory

DC and Transient Responses (i.e. delay) (some comments on power too!)

MOS Transistor Theory

Outline. Chapter 2: DC & Transient Response. Introduction to CMOS VLSI. DC Response. Transient Response Delay Estimation

Delay and Power Estimation

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)

Topic 4. The CMOS Inverter

Lecture 4: CMOS Transistor Theory

ENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)

Based on slides/material by. Topic 3-4. Combinational Logic. Outline. The CMOS Inverter: A First Glance

ECE 342 Solid State Devices & Circuits 4. CMOS

ECE 546 Lecture 10 MOS Transistors

Very Large Scale Integration (VLSI)

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS

Lecture 11 VTCs and Delay. No lab today, Mon., Tues. Labs restart next week. Midterm #1 Tues. Oct. 7 th, 6:30-8:00pm in 105 Northgate

4.10 The CMOS Digital Logic Inverter

Introduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline

ECE321 Electronics I

Lecture 12 Circuits numériques (II)

THE INVERTER. Inverter

Lecture 13 - Digital Circuits (II) MOS Inverter Circuits. March 20, 2003

Lecture 14 - Digital Circuits (III) CMOS. April 1, 2003

Midterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.

CMOS Inverter (static view)

Integrated Circuits & Systems

Digital Integrated Circuits

VLSI Design and Simulation

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

EEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation

Chapter 9. Estimating circuit speed. 9.1 Counting gate delays

Static CMOS Circuits. Example 1

MOSFET and CMOS Gate. Copy Right by Wentai Liu

5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1

Digital Microelectronic Circuits ( ) The CMOS Inverter. Lecture 4: Presented by: Adam Teman

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: 1st Order RC Delay Models. Review: Two-Input NOR Gate (NOR2)

Name: Answers. Grade: Q1 Q2 Q3 Q4 Q5 Total. ESE370 Fall 2015

The CMOS Inverter: A First Glance

EE5311- Digital IC Design

CHAPTER 15 CMOS DIGITAL LOGIC CIRCUITS

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Integrated Circuits & Systems

Miscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]

EE 434 Lecture 33. Logic Design

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter

CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Inverter: A First Look

9/18/2008 GMU, ECE 680 Physical VLSI Design

Lecture 8: Logic Effort and Combinational Circuit Design

ECE 342 Electronic Circuits. Lecture 35 CMOS Delay Model

CMOS Inverter: CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Properties.

ECE 425 Midterm Overview. Fall 2017

CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance

EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University

EE5311- Digital IC Design

Lecture 8: Combinational Circuits

Digital Integrated Circuits A Design Perspective

Lecture 7 Circuit Delay, Area and Power

Digital Integrated Circuits A Design Perspective

The Physical Structure (NMOS)

CMOS Logic Gates. University of Connecticut 181

Lecture 14: Circuit Families

CMOS logic gates. João Canas Ferreira. March University of Porto Faculty of Engineering

E40M Capacitors. M. Horowitz, J. Plummer, R. Howe

EE 330 Lecture 37. Digital Circuits. Other Logic Families. Propagation Delay basic characterization Device Sizing (Inverter and multiple-input gates)

CMOS Logic Gates. University of Connecticut 172

Lecture 5: CMOS Transistor Theory

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

The CMOS Inverter: A First Glance

CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002

VLSI Design, Fall Logical Effort. Jacob Abraham

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Properties of CMOS Gates Snapshot

EE141Microelettronica. CMOS Logic

Homework Assignment #3 EE 477 Spring 2017 Professor Parker , -.. = 1.8 -, 345 = 0 -

Lecture 3: CMOS Transistor Theory

2007 Fall: Electronic Circuits 2 CHAPTER 10. Deog-Kyoon Jeong School of Electrical Engineering

CS/EE N-type Transistor

EE115C Digital Electronic Circuits Homework #3

EE 330 Lecture 36. Digital Circuits. Transfer Characteristics of the Inverter Pair One device sizing strategy Multiple-input gates

CMOS Technology for Computer Architects

ECE 342 Electronic Circuits. 3. MOS Transistors

Digital Integrated Circuits A Design Perspective

L2: Combinational Logic Design (Construction and Boolean Algebra)

High-to-Low Propagation Delay t PHL

COMBINATIONAL LOGIC. Combinational Logic

EE213, Spr 2017 HW#3 Due: May 17 th, in class. Figure 1

ENEE 359a Digital VLSI Design

Chapter 5. The Inverter. V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov Inverter

Transcription:

Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design

Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation Readings 2.5, 4.1-4.3 2

Pass Transistors We have assumed source is grounded What if source > 0? e.g. pass transistor passing V g = If V s > -V t, V gs < V t Hence transistor would turn itself off nmos pass transistors pull no higher than -V tn Called a degraded 1 Approach degraded value slowly (low I ds ) pmos pass transistors pull no lower than V tp Transmission gates are needed to pass both 0 and 1 3

Pass Transistor Ckts V s = -V tn -V tn -V tn -V tn V s = V tp -V tn -2V tn V SS 4

DC Response DC Response: V out vs. V in for a gate Ex: Inverter When V in = 0 -> V out = When V in = -> V out = 0 In between, V out depends on transistor size and current By KCL, must settle such that I dsn = I dsp We could solve equations V in But graphical solution gives more insight I dsp I dsn V out 5

Transistor Operation Current depends on region of transistor behavior For what V in and V out are nmos and pmos in Cutoff? Linear? Saturation? 6

nmos Operation Cutoff Linear Saturated V gsn < V tn V in < V tn V gsn > V tn V in > V tn V dsn < V gsn V tn V out < V in - V tn V gsn > V tn V in > V tn V dsn > V gsn V tn V out > V in - V tn V gsn = V in I dsp V dsn = V out V in I dsn V out 7

pmos Operation Cutoff Linear Saturated V gsp > V tp V in > + V tp V gsp < V tp V in < + V tp V dsp > V gsp V tp V out > V in - V tp V gsp < V tp V in < + V tp V dsp < V gsp V tp V out < V in - V tp V gsp = V in - V tp < 0 V dsp = V out - V in I dsp I dsn V out 8

I-V Characteristics Make pmos is wider than nmos such that b n = b p V gsn5 I dsn V gsn4 -V dsp V gsn3 V gsp1 V gsp2-0 V gsn2 V gsn1 V gsp3 V dsn V gsp4 -I dsp V gsp5 9

Current vs. V out, V in V in0 V in5 I dsn, I dsp V in1 V in4 V in2 V in3 V in3 V in4 V in2 V in1 V out 10

Load Line Analysis For a given V in : Plot I dsn, I dsp vs. V out V out must be where currents are equal in V in0 V in5 I dsn, I dsp V in1 V in4 V in2 V in3 I dsp V in3 V in4 V in2 V in1 V in I dsn V out V out 11

Load Line Analysis V in = 0.2V0 0.4V 0.6V 0.8V DD V in0 V in5 V in5 I dsn, I dsp I dsn, I dsp V in1 V in4 V in2 V in3 V in3 V in4 V in2 V in0 in1 V out V out 12

DC Transfer Curve Transcribe points onto V in vs. V out plot V in0 V in5 A B V in0 V in1 V in2 V in1 V in4 V out C V in2 V in3 V in3 V in4 V in2 V in1 0 V in3 D V in4 V E in5 V tn /2 +V tp V out V in 13

Operating Regions Revisit transistor operating regions V in V out Region nmos pmos A Cutoff Linear B Saturation Linear C Saturation Saturation D Linear Saturation E Linear Cutoff V out A B 0 C D E V tn /2 +V tp V in 14

Beta Ratio If b p / b n 1, switching point will move from /2 Called skewed gate Other gates: collapse into equivalent inverter V out b p 0.1 b n b p 10 b n 2 1 0.5 0 V in 15

Noise Margins How much noise can a gate input see before it does not recognize the input? Logical High Output Range Output Characteristics V OH NM H Input Characteristics Logical High Input Range V IH V IL Indeterminate Region Logical Low Output Range V OL NM L GND Logical Low Input Range 16

Logic Levels To maximize noise margins, select logic levels at unity gain point of DC transfer characteristic V out Unity Gain Points Slope = -1 V OH b p /b n > 1 V in V out V OL 0 V tn V IL V IH - V tp V in 17

Transient Response DC analysis tells us V out if V in is constant Transient analysis tells us V out (t) if V in (t) changes Requires solving differential equations Input is usually considered to be a step or ramp From 0 to or vice versa 18

Inverter Step Response I Ex: find step response of inverter driving load cap dsn V V in out dv ( t) () t u( t ( t t ) out dt ( t) 0 t ) V 0 V I DD dsn C DD () t load 0 t t0 b 2 2 V V Vout V V Vout () t b VDD V t V () 2 out t Vo ut VD D V DD t DD t t V in (t) t 0 I dsn (t) V in (t) V out (t) V out (t) C load t 19

Delay Definitions t pdr : rising propagation delay From input to rising output crossing /2 t pdf : falling propagation delay From input to falling output crossing /2 t pd : average propagation delay t pd = (t pdr + t pdf )/2 t r : rise time From output crossing 0.2 to 0.8 t f : fall time From output crossing 0.8 to 0.2 20

Delay Definitions t cdr : rising contamination delay From input to rising output crossing /2 t cdf : falling contamination delay From input to falling output crossing /2 t cd : average contamination delay t pd = (t cdr + t cdf )/2 21

Simulated Inverter Delay Solving differential equations by hand is too hard SPICE simulator solves the equations numerically Uses more accurate I-V models too! But simulations take time to write, may hide insight 2.0 1.5 1.0 (V) V in t pdf = 66ps t pdr = 83ps 0.5 V out 0.0 0.0 200p 400p 600p 800p 1n t(s) 22

Delay Estimation We would like to be able to easily estimate delay Not as accurate as simulation But easier to ask What if? The step response usually looks like a 1 st order RC response with a decaying exponential. Use RC delay models to estimate delay C = total capacitance on output node Use effective resistance R So that t pd = RC Characterize transistors by finding their effective R Depends on average current as gate switches 23

Effective Resistance Shockley models have limited value Not accurate enough for modern transistors Too complicated for much hand analysis Simplification: treat transistor as resistor Replace I ds (V ds, V gs ) with effective resistance R I ds = V ds /R R averaged across switching of digital gate Too inaccurate to predict current at any given time But good enough to predict RC delay 24

RC Delay Model Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nmos has resistance R, capacitance C Unit pmos has resistance 2R, capacitance C Capacitance proportional to width Resistance inversely proportional to width d s kc kc R/k d 2R/k d g k g kc g k g s kc kc s kc s d 25

RC Values Capacitance C = C g = C s = C d = 2 ff/mm of gate width in 0.6 mm Gradually decline to 1 ff/mm in 65 nm Resistance R 10 KW mm in 0.6 mm process Improves with shorter channel lengths 1.25 KW mm in 65 nm process Unit transistors May refer to minimum contacted device (4/2 l) Or maybe 1 mm wide device Doesn t matter as long as you are consistent 26

Inverter Delay Estimate Estimate the delay of a fanout-of-1 inverter R 2C A 2 1 Y 2 1 R 2C C Y 2C C R 2C C 2C C C d = 6RC 27

Delay Model Comparison 28

Example: 3-input NAND Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R). 2 2 2 3 3 3 29

3-input NAND Caps Annotate the 3-input NAND gate with gate and diffusion capacitance. 2C 2C 2C 2C 2C 2 2 2 2C 2C 5C 5C 5C 3C 3C 3C 3 3 3 2C 2C 9C 3C 3C 3C 3C 30

Elmore Delay ON transistors look like resistors Pullup or pulldown network modeled as RC ladder Elmore delay of RC ladder t R C pd itosource i nodes i R C R R C... R R... R C 1 1 1 2 2 1 2 R 1 R 2 R 3 R N N N C 1 C 2 C 3 C N 31

Example: 3-input NAND Estimate worst-case rising and falling delay of 3-input NAND driving h identical gates. h copies 2 2 2 3 3 3 n 1 9C n 2 3C 3C Y 5hC t pdr 95h RC pdf R R R R R R 3 3 3 3 3 9 5 3 3 3 12 5h RC t C C h C 32

Delay Components Delay has two parts Parasitic delay 9 or 12 RC Independent of load Effort delay 5h RC Proportional to load capacitance 33

Contamination Delay Best-case (contamination) delay can be substantially less than propagation delay. Ex: If all three inputs fall simultaneously 2 2 2 3 3 3 n 1 9C n 2 3C 3C Y 5hC R 5 tcdr 9 5hC 3 h RC 3 3 34

Diffusion Capacitance We assumed contacted diffusion on every s / d. Good layout minimizes diffusion area Ex: NAND3 layout shares one diffusion contact Reduces output capacitance by 2C Merged uncontacted diffusion might help too Shared Contacted Diffusion Merged Uncontacted Diffusion 2C 2C Isolated Contacted Diffusion 2 2 2 3 3 7C 3C 3C 3C 3C 3 3C 35

Layout Comparison Which layout is better? A B A B Y Y GND GND 36

Summary Continued on transistors Pass Transistors, Operations, I-V Characteristics, DC Response, Noise Margins, Transient Response, etc. Delay Models and Delay Estimation Next lecture SPICE Readings 8.1-8.2 CMOS VLSI Design 37