UNIERSITY OF CAIFORNIA College of Engineering Deartment of Electrical Engineering and Comuter Sciences Fall 006 Borivoje Nikolic Homework #4 Solution EECS 4 Problem A This is a PMOS device. Negative gate-source, drain-source, currents should be your biggest hint. B T0-0.646 The device is in velocity, so we use the velocity equations of the unified model. The measurements you should use are and 4. I D,4 [( GS, T 0 [( GS,4 T 0 ]( + λ DS, ]( + λ DS,4 γ 0.3 / Use measurements and 5 in the same fashion as roblem A. Use the EOCITY SATURATION equations from the unified model. I D,5 [( GS, T 0 [( GS,5 T 0 ]( + λ DS, ]( + λ DS,5 λ -0.95 - Use measurements and 6 in the same fashion as roblem A. Use the EOCITY SATURATION equations from the unified model. I D,6 T 6 T 0 γ [( GS, T 0 [( GS,6 T 6 ]( + λ DS, ]( + λ DS,6 ( SB,6 Φ F Φ F C The answers are rovided in the table above and are shaded in the last column. I D 0 > CUTOFF min min ( GT, DS, DS > INEAR min min ( GT, DS, GT > SATURATION min min ( GT, DS, > EOCITY SATURATION
Measurement Number GS DS SB I D Oeration Region -.5 -.5 0-584.9uA velocity.0 0 0.0 cutoff 3-0.7-0.8 0 -.3uA 4 -.9 -.5 0-349.3uA velocity 5 -.5 -.5-0.8-505.69uA velocity 6 -.5 -.4 0-500.0uA velocity 7 -.5-0.7 0-333.9uA linear Problem # Proagation Delay and Energy a hat is the delay of a minimum sized inverter driving another inverter f times its size? For the minimum sized inverter, assume inut caacitance equal to C unit, equivalent resistance through the NMOS or PMOS equal to R unit, and intrinsic (self-loading caacitance on the outut also equal to C unit. Assume that the caacitance and resistance values scale linearly with size. Your answer will be in terms of these arameters (no calculations!. Take the limit as f goes to 0 and call the result τ inv. τ 0.69R unit C unit γ (+f/γ γ C int / C g 0.5 As f goes to zero, τ inv 0.69R unit C unit γ b From art a, how much energy is consumed by the driving inverter after successive low to high ( H and high to low (H transitions, in terms of a suly voltage dd? Energy C unit γ (+f/ γ dd c In order to drive a large caacitance (C60C unit from a minimum size gate (with inut caacitance Cin C unit, you decided to introduce a two-stage buffer as shown in Fig. 3. From (a, the roagation delay of a self-loaded minimum size inverter is τ inv. Assume that the caacitance and resistance values scale linearly with size. Determine the sizing of the two additional buffer stages that will minimize the roagation delay. hat is the corresonding roagation delay?
e want to size the buffers geometrically. f (70/ /3 4. τ Nτ inv γ (+f/ γ 7.7 τ inv Fig. 3: Buffer Chain d Given a suly voltage of dd, and a robability of inut going from zero to one P 0 0.5, what is the average energy-delay roduct of the circuit in art (c? E C dd *( C unit ( + f + f γ (+f/ γ + C unit dd EDP ½*E* τ 430 C unit τ inv dd Problem 3 Rules are: i Poly minimum width 0.4um ii Minimum active width 0.36um iii Minimum contact size 0.4um*0.4um iv Minimum sacing from contact to gate 0.4um v Active enclosure of contact 0.um Use these values a. 0.4um b. 0.36um (0.48um ok just add or subtract a 0.um*0.um diffusion area at the next-to-the-gate corner of each of the diffusion regions (Source/Drain, this also means add/subtract a diffusion area under the oly (gate in order to form a channel c. drain 0.4um+0.4um+0.um 0.6um (Some eole figured out how to draw a drain of 0.48 um. It is also correct. A D, A S, P D, P S below showed one solution, but not the only solution, as long as the calculations are consistent with the, values above. A D A S 0.48 * 0.6um 0.um*0.um 0.736um (0.88 um ok d. P D P S 0.6um*+0.48um+0.um.8um (.68um ok
a e will use equation 5.5 from the text book, note the NMOS is in velocity and the PMOS is in. ( / ( / n kn' k, n ( '( M DD t, n M + t,, n The gate lengths will be identical and thus we can calculate.54 µm, A D 0.3809 µm, and P D.4544 µm. b e are using Keq. (Ok if you calculate K eq PMOS: C gc saturated /3 (C ox.04 ff triode C ox.806 ff C gb cutoff C ox.806 ff C gdo C O P 0.34 ff C gso C O P 0.34 ff NMOS: C gc saturated /3 (C ox n n 0.346 ff triode C ox n n 0.58 ff C gb cutoff C ox n n 0.58 ff C gdo C O n 0. ff C gso C O n 0. ff hen outut transitions from DD to DD/, PMOS is OFF and assume NMOS stays in SATURATION (at least initially. (It is also ok if you assume NMOS is in linear. C in C gb + *C gdo + *C gdon + C gsn.806 ff + *0.34 ff + *0. ff + 0.346 ff 3.056 ff Similarly, when outut transitions from 0 to DD/, NMOS is OFF and assume PMOS stays in SATURATION. (It is also ok if you assume PMOS is in linear. C in C gbn + *C gdon + *C gdo + C gs 0.58 ff + *0. ff + *0.34 ff +.04 ff.66 ff. c
Hw3 Prob3d.lib'g5.mod' TT.aram vdd.5.aram ln_min0.4u.aram l_min0.4u.aram l_drain0.6.aram arean(w'(w*l_drain*'.aram area(w'(w*l_drain*'.aram erin(w'((w*u+(l_drain*u'.aram eri(w'((w*u+(l_drain*u' DD vdd 0 'vdd' IIN 0 in u M out in vdd vdd mos l'l_min' w.04u M out in 0 0 nmos l'ln_min' w0.36u.ic v(in0.meas t trig v(in val0.000 cross targ v(in val.5 cross.meas t trig v(in val.5 cross targ v(in val.5 cross.otions ost nomod.o.tran 0.ns 0ns.end d Follow Examle 5. in the textbook (Note: various formulas can be used to solve this. Credit should be given as long as the results are reasonable. I D ( M 59 ua and g -8. Then use equations 5.7 to solve: IH M - M /g.94 I M + ( DD - M /g.06 NM H DD IH.06 NM I.06