Electronic Supplementary Material (ESI) or Nanoscale. This journal is The Royal Society o Chemistry 017 Supplementary Materials Eective electro-optic modulation in low-loss graphene-plasmonic slot waveguides Y. Ding, 1 * X. Guan, 1 X. Zhu, 3 H. Hu, 1 S. I. Bozhevolnyi, 4 L. K. Oxenløwe, 1 K. J. Jin 5, N. A. Mortensen, 1,,4 Sanshui Xiao 1, * (1) Department o Photonics Engineering, Technical University o Denmark, DK-800 Kongens Lyngby, Denmark () Center or Nanostructured Graphene, Technical University o Denmark, DK-800 Kongens Lyngby, Denmark (3) Department o Micro- and Nanotechnology, Technical University o Denmark, DK-800 Kongens Lyngby, Denmark (4) Centre or Nano Optics & Danish Institute or Advanced Study, University o Southern Denmark, Campusvej 55, DK-530 Odense M, Denmark (5) Beijing National Laboratory or Condensed Matter Physics, Institute o Physics, Chinese Academy o Sciences, Beijing 100190, China *yudin@otonik.dtu.dk *saxi@otonik.dtu.dk S1. Theory and calculation o propagation loss The schematic o the designed graphene-plasmonic slot waveguide is shown in Fig. S1. Graphene 1 n 1 Gap Graphene h n Si substrate Fig. S1. Cross section o the designed graphene-plasmonic slot waveguide. 1
In order to accurately calculate the mode (including the leaky mode) o a plasmonic slot waveguide, the thickness o buried oxide layer (BOX) o the silicon-on-insulator (SOI) waer and silicon substrate has to be considered. The thickness o BOX layer is 3 µm. The thickness o the sheet h that orms the plasmonic slot waveguide is varied. The Al O 3 between the graphene layer 1 and plasmonic slot waveguide is designed to be 5 nm thick, and the Al O 3 between the two layers o graphene sheet is designed to be 10 nm. The thickness o the graphene sheet is considered to be 0.5 nm, and the Fermi level E dependent complex dielectric constant ( ε G = ε G ' + jε'' G) o graphene can be described under the random phase approximation and the Kramers-Kronig relations E p E e E E p p E e ' G E p1 ln 8 E d d E 1 p 0 0 e 1 E 1 p E E 1 p E E e '' G E p 1 tan tan 4Ep 0d Ep 0d Ep 1 (Eq.S1) where E p is the photon energy, d is the thickness o the two graphene layers, Γ is the inter-band broadening, and 1/τ is the ree carrier scattering rate. The reractive indices o Si, Al O 3, are considered to be 3.45, and 1.746 and -131.94+j1.65, and the reractive indices o the upper cladding the substrate are denoted by n 1 and n respectively. With the complex dielectric constant o graphene and, the complex eective reractive index (n e = n e,real + jn e,imag ), the corresponding propagation is then obtained 6 4.34310 db m k0 n e, imag (Eq.S) where 4.343 10-6 is the constant or converting rom m -1 to db/µm. S. Study o coupling between silicon waveguide and plasmonic waveguide The plasmonic slot waveguide can be eectively coupled with silicon waveguides by introducing inverse taper in the silicon waveguide tip, as shown in Fig. S.
L 750nm. µm Gap Monitor 600nm Si Fig. S. Top view o the plasmonic slot waveguide coupled with silicon waveguides with inverse tip. The transmission T is investigated by monitoring the output monitor calculated by three-dimensional Finitedierence time-domain method (3D-FDTD) simulation, and the coupling eiciency a between the silicon waveguide mode and the plasmonic leaky mode, can be express as a 10log T (Eq.S3) where L = 0 µm is considered. Fig. S3(a) shows the calculated coupling eiciency (CE) as a unction o coupling gap or dierent thicknesses. The coupling eiciency decreases as plasmonic gap increases. Increasing the thickness slightly increases the coupling eiciency. A highest CE o ~-0.86 db can be achieved or small plasmonic gap o 80 nm, which may be challenge to abricate. A CE o -1.06 db and -1.3 db is expected or plasmonic gap o 10 nm and 150 nm with thickness o 90 nm, respectively. This coupling coniguration is also quite abrication tolerant. Fig. S3(b) presents the CE as a unction o misalignment between the silicon waveguide and plasmonic slot waveguide, showing that a misalignment o 45 nm and 60 nm misalignment tolerance is expected or plasmonic gap o 10 nm and 150 nm, respectively. (a) (b) CE (db) h 100nm h 90nm h 80nm CE (db) Gap 150nm Gap 10nm Gap (nm) Misalignment (nm) Fig. S3. (a) 3D FDTD calculated CE between a silicon waveguide and plasmonic slot waveguide as a unction o plasmonic gap or dierent thickness. (b) 3D FDTD calculated CE as a unction o alignment error or dierent plasmonic gap size. 3
S3. Fabrication process The details o the abrication process are shown in Fig. S4. The top silicon o a commercial SOI waer was irst thinned down to 90 nm in order to obtain a comparable thickness o the plasmonic slot waveguide (Fig. S4(i)~S4(ii)) by inductively coupled plasma (ICP) etching (STS Advanced Silicon Etcher). Ater that, standard SOI processing, including e-beam lithography (EBL, JEOL JBX-9300FS, e-beam resist: ZEP50A) and ICP etching, was irst used to abricate the etched silicon waveguides (Fig. S4(iii)~S4(iv)). Then the plasmonic slot waveguide was abricated by a second EBL ollowed by metal deposition and lito process (Fig. S4(v)~S4(vii)). Ater that, the whole chip was coated with 5 nm Al O 3 deposited by Atomic Layer Deposition (ALD) (Fig. S4(viii)) in order to isolate the contact between the plasmonic slot waveguide and graphene layer 1 that will be transerred later. At the same time, AZ514E photoresist was spin-coated onto the graphene covered copper oil and baked at 90 C or 1 min (Fig. S4(ix)~Fig. S4(x)). Following that, AZ514E/graphene membrane was obtained by wet-etching away the copper oil in a Fe(NO 3 ) 3 /H O solution, and transerred onto the silicon chip (Fig. S4(xi)~S4(xii)). Finally, the AZ514E was dissolved in acetone and wet transer o the graphene layer 1 was inished (Fig. S4(xiii)~S4(xiv)). The graphene coverage area was then deined by standard UV lithography and ollowed by oxygen plasma etching and resist removing (Fig. S4(xv)~S4(xvii)). The contact or graphene was then abricated by standard UV lithography ollowed by /Ti deposition and lito process (Fig. S4(xviii)~S4(xx)). Ater that, 1 nm Al was deposited on the chip, and oxidized to Al O 3 in air. This native Al O 3 layer will be seed layer or the urther Al O 3 deposition in ALD machine. Eventually, 10 nm Al O 3 was obtained (Fig. S4(xxi)). The graphene layer was wet-transerred with the same transerring process (Fig. S4(xxii)~S4(xxvii)). The coverage area o graphene layer was then deined by UV lithography ollowed by oxygen plasma etching and resist removing (Fig. S4(xxviii)~S4(xxx)). Finally, the contact or graphene layer was abricated by UV lithography ollowed by /Ti deposition and lito process (Fig. S4(xxxi)~S4(xxxiii)). 4
Silicon and plasmonic slot waveguide abrication (i) (ii) (iii) SiO Si substrate (vi) (v) SiO Si substrate (iv) Graphene layer 1 wet transer (ix) (x) graphene AZ514E (xii) Cu (xi) (vii) (viii) Fe(NO3)3/ HO (xiii) Patterning graphene layer 1 and metal contact abrication (xiv) (xv) (xvi) Graphene layer wet transer (xix) (xviii) (xvii) (xxii) (xxv) graphene Cu (xxiii) (xxiv) AZ514E (xx) (xxi) Fe(NO3)3/ HO Patterning graphene layer and metal contact abrication (xxvi) (xxvii) (xxviii) (xxix) (xxxii) (xxxi) (xxx) (xxxiii) Fig.S4. Detailed abrication process low o the graphene-plasmonic slot waveguide based E/O modulator. S4. Characterization setup The experimental setup or measuring the graphene-plasmonic slot waveguide based E/O modulator is exhibited in Fig. S5. Light rom a tunable laser source (TLS, ANDO AQ431A) was polarization-tuned by a polarization controller (PC), and injected into the grating coupler which was designed on the TE mode. The 5
light output rom the chip was coupled to the output iber by a grating coupler, and detected by the optical spectral analyzer (OSA, AQ6317B). The electrical contacts or the two graphene layers were connected to a power supply (Keithley 38, High Current Source Measure Unit). In the E/O switching experiment, the square waveorm is generated by a waveorm generator (Stanord Researcher Systems Inc., Model DG 535, Four Channel Digital Delay/Pulse Generator). Power supply OSA PC SSMF TLS Fiber holder 75 Z Y X X Y Z Silicon chip Fig. S5. Experimental setup or characterizing graphene-silicon devices. (a) (b) Graphene layer 1 µm Graphene layer 1 boundary µm Graphene layer (c) Si Fig. S6. Scanning electron microscope (SEM) images o abricated graphene-plasmonic slot waveguide ater (a) contact abrication on the graphene layer 1, corresponding to step Fig. S5(xxi). and (b) contact abrication on the graphene layer, corresponding to the inal step Fig. S5(xxxiii). (c) SEM image o the zoom-in o the coupling area between silicon waveguide with inverse taper and plasmonic slot waveguide, clearly indicating good coverage by two graphene layers. 6