407 Computer Aided Design for Electronic Systems Simulation Instructor: Maria K. Michael Overview What is simulation? Design verification Modeling Levels Modeling circuits for simulation True-value simulation algorithms Compiled-code simulation Event-driven simulation Summary 2 407: Computer-Aided Design for VLSI
Simulation Defined Definition: Simulation refers to modeling of a design, its operation (functionality) and performance (timing) A software simulator is a computer program; an emulator is a hardware simulator. Simulation is used for design verification: Validate assumptions Verify logic Verify performance (timing) 3 Simulation for Verification Specification Synthesis Response analysis Design changes Design (netlist) Computed responses True-value simulation Input stimuli 4 407: Computer-Aided Design for VLSI 2
Simulation for Verification Complexity for full simulation is huge! Example: Simulate a 32-bit Full-Adder 64 inputs, 33 outputs, ~ 200 gates Let µs for true time to simulate pattern è (2 64 x 0-6 )/(3,600x24x365) = 584,942 years to simulate all possible input patterns!! 5 Types/Levels of Simulation Behavioral/Functional Logic Switch Timing Circuit Less accurate/complex More accurate/complex 6 407: Computer-Aided Design for VLSI 3
Levels of Simulation Behavioral/Functional/RTL: models large pieces of a system as black boxes w/ inputs/outputs (usually uses HDL) Logic/Gate: basic components are Boolean gates and FFs which are all treated as black boxes modeled by a function whose variables are the gate s input signals. Can also model delay. Switch: more accurate simulation than gate-level. Models transistors as switches (ON/OFF). Can see connectivity of transistors, their sizes and types, and node capacitances. Does not have the ability to use logic delays. Timing: uses a switch-level model including voltage-current characteristics which allow to see timing behavior. Circuit/Transistor: most accurate but most complex type of simulation. Must be able to model transistors and describe their non-linear voltage and current characteristics (ex SPICE). 7 Modeling Levels Modeling level Function, behavior, RTL Circuit description Programming language-like HDL Signal values 0, Timing Clock boundary Application Architectural and functional verification Logic Connectivity of Boolean gates, flip-flops and transistors 0,, and Z Zero-delay unit-delay, multipledelay Logic verification and test Switch Transistor size and connectivity, node capacitances 0, and Zero-delay Logic verification Timing Circuit Transistor technology data, connectivity, node capacitances Tech. Data, active/ passive component connectivity Analog voltage Analog voltage, current Fine-grain timing Continuous time Timing verification Digital timing and analog circuit verification 8 407: Computer-Aided Design for VLSI 4
When are Simulators used? Pre-layout: includes logic cell delays but not interconnect delays Post-layout: after physical design in order to take into consideration capacitance estimates Which modeling level is used in each case? 9 Modeling for Simulation Modules, blocks or components described by Input/output (I/O) functions Delays associated with I/O signals Examples: binary adder, Boolean gates, FET, resistors and capacitors Interconnects represent ideal signal carriers, or ideal electrical conductors Netlist: a format (or language) that describes a design as an interconnection of modules. A netlist may use flat descriptions or hierarchy. 0 407: Computer-Aided Design for VLSI 5
Hierarchical Descriptions Example: A Full-Adder a b d HA e c f HA; inputs: a, b; outputs: c, f; AND: A, (a, b), (c); AND: A2, (d, e), (f); OR: O, (a, b), (d); NOT: N, (c), (e); A B C HA D E HA2 F Carry Sum FA; inputs: A, B, C; outputs: Carry, Sum; HA: HA, (A, B), (D, E); HA: HA2, (E, C), (F, Sum); OR: O2, (D, F), (Carry); a b Logic Model of MOS Circuit Static CMOS NAND V pmos FETs DD C a C b C c c nmos FETs a b Equivalent ideal Boolean gate D a D b D c D a and D b are interconnect or propagation delays c C a, C b and C c are parasitic capacitances D c is inertial delay of gate 2 407: Computer-Aided Design for VLSI 6
Necessity of transistor-level models Ideal Boolean gate representation not always possible Example: Busses (next slide) Use mixed-mode models: Memory: functional level Random logic: gate/hierarchical Bus/Tri-state: switch level 3 Necessity of transistor-level models 0 V DD depends on T th of NOT Static NAND V DD 0 NOT 4 Static NOR 407: Computer-Aided Design for VLSI 7
Inputs Options for Inertial Delay (simulation of a NAND gate) a b 0 5 Transient region c (CMOS) fall=5 Logic simulation c (zero delay) c (unit delay) c (multiple delay) c (minmax delay) min a Unknown () max a min b max b rise=5, fall=5 min =2, max =5 Time units 5 Signal States Two-states (0, ) can be used for purely combinational logic with zero-delay. Three-states (0,, ) are essential for timing hazards and for sequential logic initialization. Four-states (0,,, Z) are essential for MOS devices (ex. Busses) à the larger the set of possible states/values, the most accurate the simulation but, also the most expensive Analog signals are used for exact timing of digital logic and for analog circuits (ex SPICE). 6 407: Computer-Aided Design for VLSI 8
7 Inputs a b Signal States 3-valued logic: (0,, ) AND (a b) Outputs OR (a +b) NOT (a ) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Truth table has 3 2 lines This is a pessimistic model, i.e., it may give an value when a 0/ value exists 3-value simulation reality Inputs a b 8 Signal States 4-valued logic: (0,,, ) Outputs AND (a b) OR (a+b) NOT (a ) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3-value simulation 4-value simulation 407: Computer-Aided Design for VLSI 9
Logic Strength A logic system may be defined w.r.t. logic values (see previous slides) as well as logic strength: Strong (S) Weak (W) High impedance (Z) Unknown (U) 9 Logic Strength (cont) Remember the IEEE Std A 3-value logic system with 4 64_993 logic system which strength levels becomes a 2-value defines variable type logic system: std_logic w/ 9 values: Logic strength Logic value Symbol Description 0 Strong (S) S0 S S Weak (W) W0 W W High Impedance (Z) Z0 Z Z Unknown (U) U0 U U * In reality, such system usually uses only the values {S0, S, W0, W, Z,, U} 0 Strong low Strong high L H W Z Weak low Weak high Strong unknown Weak unknown High impedance - Don t care U Uninitialized 20 407: Computer-Aided Design for VLSI 0
Discrete Event Simulation Simulation is the process of computing the signal values of an electronic circuit, as a function of time For analog circuits, time is a continued parameter For digital circuits, only certain discrete values of signals are meaningful (either ignore fine-grain transients or approximate them) à Time is assumed to advance in discrete jumps à The change of a signal form one value to another is defined as an event à The simulator computes the events occurring in the circuit as a result of the applied primary input signals (source events) à Digital simulation is also known as discrete event simulation 2 Simulation Algorithms Compiled-code simulation Circuit described in HDL. High-level (e.g., C language) models can also be used Effective for zero-delay 2-value (0, ) combinational logic Also used for cycle-accurate synchronous sequential circuits for logic verification Efficient for highly active circuits, but inefficient for low-activity circuits Event-driven simulation Only gates or modules with input events are evaluated (event means a signal change) Delays (and hazards, race conditions, etc) can be accurately simulated for timing verification Efficient for low-activity circuits Can be extended for fault simulation 22 407: Computer-Aided Design for VLSI
Compiled-Code Algorithm Step : Levelize circuit logic and encode in a compilable programming language Step 2: Initialize data variables (internal state variables such as FFs and other memory) Step 3: For each input vector Set primary input variables Repeat (until steady-state or max. iterations) Execute compiled code (all code!!!) Report or save computed variables 23 Event-Driven Algorithm (Example) Scheduled events Activity list a = c = 0 2 b = g 2 d = 0 4 e = 2 f =0 g = Time stack t = 0 2 3 4 5 6 c = 0 d =, e = 0 g = 0 f = d, e f, g g 0 4 8 Time, t 7 8 g = 24 407: Computer-Aided Design for VLSI 2
Time Wheel (Circular Stack) max: largest delay experienced by any event + Current time pointer max t=0 2 3 4 5 6 7 Event link-list To avoid having the time stack grow along with the simulation time 25 Efficiency of Event-driven Simulator Simulates events (value changes) only Speed up over compiled-code can be ten times or more; in large logic circuits about 0. to 0% gates become active for an input change Steady 0 0 to event Steady 0 (no event) Large logic block without activity 26 407: Computer-Aided Design for VLSI 3
VHDL Event-Driven Simulation Elaboration phase: done before simulation to put together all the pieces of the code (entities, architectures, configurations) Initialization phase: brings known values at circuit nets Simulation phase: repeated continuously; processes are executed and signals are updated 27 VHDL Event-Driven Simulation Simulation Cycle:. Current time t c = t n 2. Update each active signal à events may occur 3. For each process P, if P is sensitive to a signal s for which an event has occurred during this cycle then resume P 4. Execute each resumed process until it suspends 5. The time for the next simulation cycle, t n, is the smallest of:. Next time a driver becomes active 2. Next time a process resumes 6. If t n = t c, then the next simulation cycle is a delta cycle; otherwise is a real cycle. Simulation ends when t n = TIME HIGH (max time reached) and there are no active drivers/procedures Delta cycle: takes delta time (real time does not advance); used for simulation purposes, to update multiple signals/execute events concurrently Real time: updated/advanced only after all events have been completed and signals have been updated within a delta cycle 28 407: Computer-Aided Design for VLSI 4
Delay Mechanisms in VHDL Inertial delay: allows to consider pulse rejection Out <= In after 0 ns; -- default is inertial Out <= inertial In after 0 ns; Out <= reject 0 ns inertial In after 0 ns; Out <= reject 2 ns inertial In after 0 ns; equivalent Transport (propagation) delay: no rejection time; it can be modeled by inertial delay with 0 rejection time Out <= transport In after 0 ns; Out <= reject 0 ns inertial In after 20 ns; equivalent 29 Out <= transport In after 0 ns, not In after 20 ns; Out <= reject 0 ns inertial In after 0 ns, not In after 20 ns; equivalent Summary Logic or true-value simulators are essential tools for design verification. Verification vectors and expected responses are generated (often manually) from specifications. A logic simulator can be implemented using either compiled-code or event-driven algorithms. Per vector, complexity of a logic simulator is approximately linear in circuit size. Modeling level determines the evaluation procedures used in the simulator. 30 407: Computer-Aided Design for VLSI 5