ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization
Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2
Lecture Outline! Euler Path for Layout! Energy and Power Basics! Energy and Power Optimization 3
Performance Design
NOR2 Layout 5
NAND2 Layout 6
Layout of Complex CMOS Gate S DDS GND 7
Layout of Complex CMOS Gate 8
Layout of Complex CMOS Gate diffusion breaks d d d. d d i.e. n, p Euler paths with identical sequences of inputs 9
Minimize Number of Diffusion Paths 10
Minimize Number of Diffusion Paths 11
Minimize Number of Diffusion Paths 12
Minimize Number of Diffusion Paths 13
Gate Layout Algorithm! 1. Find all Euler paths that cover the graph! 2. Find common n- and p- Euler paths! 3. If no common n- and p- Euler paths are found in step 2, partition the gate n- and p- graphs into the minimum number of sub-graphs that will result in separate common n- and p- Euler paths 14
Review Motivation, Abstraction, and Design Tradeoffs
Digital Logic: Gate Level! We care about design for performance " Functionality (e.g. F = A + B*C) " Speed " Each gate has a delay " Critical path defines delay " Power " Area " Switching power (comprised of dynamic and short circuit power) and static power (I.e P tot =P dyn +P SC + P stat ) " For a gate the standard cell area 16
Digital Logic: Transistor Level 17
Digital Logic: Transistor Level! We care about design for performance " Functionality (e.g. F = A + B*C) " Speed " Power " Area " Design for abstraction (VTC: switching voltage, restoration, noise margins) " Transistor sizing affects the output resistance and capacitance allowing for a tau estimate of each gate dependent on W and L of transistors " Switching power (comprised of dynamic and short circuit power) and static power (I.e P tot =P dyn +P SC + P stat ). Transistor sizing affects drive current and impacts power consumption " For a gate the standard cell area, dependent on W and L of transistors 18
Review: MOS Inverter Dynamic Performance! ANALYSIS (OR SIMULATION): For a given MOS inverter schematic and C load, estimate (or measure) the propagation delays! DESIGN: For given specs for the propagation delays and C load*, determine the MOS inverter schematic METHODS: 1. Average Current Model τ PHL C load 2. Differential Equation Model i C = C load dv out dt ΔV HL I avg,hl = C load V OH V 50% I avg,hl dv dt = C out load dt τ PHL or τ PLH 3. 1 st Order RC delay Model i C Assume V in ideal τ PHL 0.69 C load R n 19
Review: nmos IV Characteristics 2 4 4 4 4 4 I D = 3 4 4 4 4 4 5 I S! # " W L! # " $ &e % V GS V th nkt /q $ & %!! # " 1 e # " V DS $ & kt /q % $ & 1+ λv DS % ( ) V GS V Tn Subthreshold µ n C ox W ( 2 L 2 ( V GS V Tn (V SB ))V DS V 2 DS )(1+ λ V DS ) V GS > V Tn,V DS < V GS Linear µ n C ox W ( 2 L V V (V ) GS Tn SB ) 2 (1+ λ V DS ) V GS > V Tn,V DS V GS V Tn Saturation, v sat C OX W ( V GS V th ) V / dsat -. 2 0 1 E y > E cn (short channel) Velocity Saturation 20
nmos 1st Order RC Delay Model Equiv. R n κ n C d R n = R un /κ n κ n κ n C g ON/ OFF Where W n = κ n W un κ n 1, usually κ n = 1 κ n C d s κ p C d R p = R up /κ p Where W p = κ p W up κ p ON/ OFF κ p 1, usually κ p µ n /µ p κ p C g d κ p C d 21
Energy and Power Basics
Today! Power Sources " Static power " Dynamic switching power " Short circuit power 23
Power! P = I V! Tricky part: " Understanding I " (pairing with correct V) 24
Understanding Currents Static Power 25
Operating Modes! Steady-State: What modes are the transistors in? " V in =V dd " V in =Gnd! What current flows in steady state? 26
Operating Modes! Steady-State: V in =V dd " PMOS: subthreshold " NMOS: resistive 27
Operating Modes! Steady-State: V in =V dd " PMOS: subthreshold " NMOS: resistive $ I DSp = I S #& W % L ' ) e ( $ & % V GS V T nkt / q ' $ $ V DS ) & ( 1 e % & % ' ) kt / q ( ' ) 1 λv DS ( ( ) I DSn = µ n C OX! # " W L $ ( & ( V GS V T )V DS V 2 DS * %) 2 + -, Which current determines I static? 28
Static Power! P = I V! What V should we use? " Where is the static current flowing? 29
Understanding Currents Dynamic Switching Currents 30
Power: During Switching! P = IV! Input switch: 1#0! Where does I go? " V in =Gnd 31
Power: During Switching! P = IV! Input switch: 1#0! Where does I go? " V in =Gnd 32
Power: During Switching! P = IV! Input switch: 1#0! Where does I go? " V in =Gnd (Saturation/Linear) I dyn Subtheshold Leakage 33
Power: During Switching! P = IV! Input switch 0#1! Where does I go? " V in =V dd 34
Power: During Switching! P = IV! Input switch 0#1! Where does I go? " V in =V dd 35
Power: During Switching! P = IV! Input switch 0#1! Where does I go? Subtheshold Leakage " V in =V dd I dyn (Saturation/Linear) 36
Switching Currents! Dynamic current flow: 37
Understanding Currents Short Circuit Currents 38
Power: During Switching! P = IV! Where does I go? " V in =V dd /2 " And V dd >V thn + V thp 39
Power: During Switching! P = IV! Where does I go? " V in =V dd /2 " And V dd >V thn + V thp Saturation Vout 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 CMOS Inverter DC Transfer 0 0.2 0.4 0.6 0.8 1 Vin Saturation 40
Switching Currents! Dynamic current flow:! If both transistor on: " Current path from V dd to Gnd " Short circuit current 41
Currents Summary! I changes over time! At least two components " I static no switching " I switch when switching " I dyn and I sc 42
Switching Dynamic Power 43
Switching Currents! I total (t) = I static (t)+i switch (t)! I switch (t) = I sc (t) + I dyn (t) I dyn I static I sc Penn ESE 570 Spring 2018 - Khanna 44
Charging! I dyn (t) why changing? " I ds = f(v ds,v gs ) " and V gs, V ds changing % I DS ν sat C OX W V GS V T V DSAT ' & 2 I DS = µ n C OX " $ # W L ( * ) %) ' ( V & GS V T )V DS V 2 DS + * 2,. - 45
Switching Energy! Do we know what this is? Q = I dyn (t)dt! What is Q? I dyn E = P(t)dt Q = CV = I(t)dt = I(t)V dd dt = V dd I(t)dt E = CV dd 2 Capacitor charging energy 46
Switching Power! Every time output switches 0#1 pay: " E = CV 2! P dyn = (# 0#1 trans) CV 2 / time! # 0#1 trans = ½ # of transitions! P dyn = (# trans) ½CV 2 / time 47
Switching Short Circuit Power 48
Short Circuit Power! Between V TN and V dd - V TP " Both N and P devices conducting Penn ESE 570 Spring 2018 - Khanna 49
Short Circuit Power! Between V TN and V dd - V TP " Both N and P devices conducting! Roughly: I sc Vin Vdd-Vthp Vthn time Vdd Vdd Isc Vout tsc tsc time 50
Peak Current! I peak around V dd /2 " If V TN = V TP and sized equal rise/fall % I DS ν sat C OX W V GS V T V ( DSAT ' * & 2 ) I(t)dt I t % ' 1( peak sc & 2 * ) # E = V dd I peak t sc % 1& ( $ 2' Vin Vdd-Vthp Vthn Vdd Isc Vdd time Vout tsc tsc time 51
Short Circuit Energy! Make it look like a capacitance, C SC " Q=I t " Q=CV " " E = V dd I peak t sc 1 %% $ $ '' # # 2 && E = V dd Q SC E = V dd (C SC V dd ) = C SC V 2 dd Penn ESE 570 Spring 2015 - Khanna 52
Short Circuit Energy! Every time switch " Also dissipate short-circuit energy: E = CV 2 " Different C = C sc " C cs fake capacitance (for accounting) Penn ESE 570 Spring 2018 - Khanna 53
Switching Power! Every time output switches 0#1 pay: " E = CV 2! P dyn = (# 0#1 trans) CV 2 / time! # 0#1 trans = ½ # of transitions! P dyn = (# trans) ½CV 2 / time 54
Charging Power! P dyn = (# trans) ½CV 2 / time! Often like to think about switching frequency! Useful to consider per clock cycle " Frequency f = 1/clock-period! P dyn = (#trans/clock) ½CV 2 f 55
Charging Power! P dyn = (# 0#1 trans) CV 2 / time! Often like to think about switching frequency! Useful to consider per clock cycle " Frequency f = 1/clock-period! P dyn = (# 0#1 trans/clock) CV 2 f 56
Switching Power! P dyn = (#0#1 trans/clock) CV 2 f! Let a = activity factor a = average #tran 0#1 /clock! P dyn = acv 2 f! P sc = ac sc V 2 f Penn ESE 570 Spring 2018 - Khanna 57
Activity Factor! Let a = activity factor " a = average #tran 0#1 /clock a = p(out i = 0) p(out i+1 =1) a = N N 0 1 2 N 2 = N 0 (2N N 0 ) N 2 2N Penn ESE 570 Spring 2018 - Khanna 58
Activity Factor! Let a = activity factor " a = average #tran 0#1 /clock a = p(out i = 0)p(out i+1 =1) a = N 0 N 1 2 N 2 = N (2 N 0 N 0 ) N 2 2 N Penn ESE 570 Spring 2018 - Khanna 59
Reduce Dynamic Power?! P dyn = acv 2 f! How do we reduce dynamic power? Penn ESE 570 Spring 2018 - Khanna 60
Reduce Activity Factor Tree Chain A B O 1 A B O 1 C D O 2 F C D O 2 F a = p(out i = 0)p(out i+1 =1) a = N 0 N 1 2 N 2 = N (2 N 0 N 0 ) N 2 2 N Penn ESE 570 Spring 2018 - Khanna 61
Reduce Activity Factor Tree Chain A B 3/16 O 1 A B O 1 C D O 2 3/16 F a = p(out i = 0)p(out i+1 =1) C D O 2 F a = N 0 N 1 2 N 2 = N (2 N 0 N 0 ) N 2 2 N Penn ESE 570 Spring 2018 - Khanna 62
Reduce Activity Factor Tree Chain A B 3/16 O 1 15/256 A B O 1 C D O 2 3/16 F a = p(out i = 0)p(out i+1 =1) C D O 2 F a = N 0 N 1 2 N 2 = N (2 N 0 N 0 ) N 2 2 N Penn ESE 570 Spring 2018 - Khanna 63
Reduce Activity Factor Tree Chain A B C D O 1 O 2 F A B C 3/16 O 1 D 7/64 O 2 15/256 F a = p(out i = 0)p(out i+1 =1) a = N 0 N 1 2 N 2 = N (2 N 0 N 0 ) N 2 2 N Penn ESE 570 Spring 2018 - Khanna 64
Reduce Activity Factor Tree Chain A B C D 3/16 O 1 O 2 3/16 15/256 F A B C 3/16 O 1 a = p(out i = 0)p(out i+1 =1) D 7/64 O 2 15/256 F a = N 0 N 1 2 N 2 = N (2 N 0 N 0 ) N 2 2 N Penn ESE 570 Spring 2018 - Khanna 65
Total Power! P tot = P static + P sc + P dyn! P sw = P dyn + P sc = a(c load V 2 f) + C sc V 2 f! P tot a(c load V 2 f) + C sc V 2 f + VI s (W/L)e-Vt/(nkT/q)! Let a = activity factor a = average #tran 0#1 /clock 66
Energy and Power Optimization
Power Sources Review: P tot = P static + P dyn + P sc
Worksheet Problem 1 V in I static I dynamic I sc 0V 140mV 400mV 500mV 600mV 860mV 1V 69
Worksheet Problem 1 V in I static I dynamic I sc 0V 180pA 126uA 140mV 6nA 100uA 400mV 36uA 18uA 500mV 36uA 600mV 36uA 18uA 860mV 6nA 100uA 1V 180pA 126uA 70
Idea! Gate layout optimization " Euler Paths! Power Basics Review! Energy and Power Tradeoffs 71
Admin! HW 6 " Out now " Due Tuesday 3/28 Penn ESE 570 Spring 2018 - Khanna 72