Semiconductor References: Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey UCB Principles of CMOS VLSI Design: A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian Prof. Kaushik Roy @ Purdue Univ.
Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies
Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM
Memory Architecture: Decoders M bits M bits S 0 Word 0 S 0 Word 0 words S 1 S 2 Word 1 Word 2 Storage cell A 0 A 1 Word 1 Word 2 Storage cell N S N 2 2 Word N 2 2 A K 2 1 Word N 2 2 S N 2 1 Word N 2 1 Word N 2 1 K 5 log 2 N Input-Output ( M bits) Decoder Input-Output ( M bits) Intuitive architecture for N x M memory Too many select signals: N words == N select signals Decoder reduces the number of select signals K = log 2 N
Array-Structured Memory Architecture Problem: ASPECT RATIO or HEIGHT >> WIDTH Amplify swing to rail-to-rail amplitude Selects appropriate word
Hierarchical Memory Architecture Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings
Read-Only Memory Cells BL BL BL 1 WL WL WL BL BL BL 0 WL WL WL GND Diode ROM MOS ROM 1 MOS ROM 2
MOS OR ROM BL [0] BL [1] BL [2] BL [3] WL [0] WL [1] WL [2] WL [3] V bias Pull-down loads
MOS NOR ROM Pull-up devices WL [0] WL [1] GND WL [2] GND WL [3] BL [0] BL [1] BL [2] BL [3]
Precharged MOS NOR ROM f pre Precharge devices WL [0] WL [1] GND WL [2] GND WL [3] BL [0] BL [1] BL [2] BL [3] PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design.
MOS NOR ROM Layout Cell (9.5l x 7l) Programmming using the Active Layer Only Polysilicon Metal1 Diffusion Metal1 on Diffusion
MOS NOR ROM Layout Cell (11l x 7l) Programmming using the Contact Layer Only Polysilicon Metal1 Diffusion Metal1 on Diffusion
MOS NAND ROM Pull-up devices BL [0] BL [1] BL [2] BL [3] WL [0] WL [1] WL [2] WL [3] All word lines high by default with exception of selected row
MOS NAND ROM Layout Cell (8l x 7l) Programmming using the Metal-1 Layer Only No contact to VDD or GND necessary; drastically reduced cell size Loss in performance compared to NOR ROM Polysilicon Diffusion Metal1 on Diffusion
NAND ROM Layout Cell (5l x 6l) Programmming using Implants Only Polysilicon Threshold-altering implant Metal1 on Diffusion
Non-Volatile The Floating-gate transistor (FAMOS) Source Floating gate Gate Drain D t ox G n + Substrate p t ox n +_ S Device cross-section Schematic symbol
Floating-Gate Transistor Programming 20 V 0 V 5 V 10 V 5 V 20 V 2 5 V 0 V 2 2.5 V 5 V S D S D S D Avalanche injection Removing programming voltage leaves charge trapped Programming results in higher V T.
FLOTOX EEPROM Floating gate Source Gate Drain I 20 30 nm n 1 Substrate n 1 p 10 nm -10 V 10 V V GD FLOTOX transistor Fowler-Nordheim I-V characteristic
EEPROM Cell BL WL Absolute threshold control is hard Unprogrammed transistor might be depletion 2 transistor cell
Flash EEPROM Control gate Floating gate erasure n 1 source programming p- substrate Thin tunneling oxide n 1 drain Many other options
Cross-sections of NVM cells Flash EPROM Digital Integrated Circuits 2nd Courtesy Intel
Basic Operations in a NOR Flash Memory Erase Digital Integrated Circuits 2nd
Basic Operations in a NOR Flash Memory Write Digital Integrated Circuits 2nd
Basic Operations in a NOR Flash Memory Read Digital Integrated Circuits 2nd
Characteristics of State-of-the-art NVM
Read-Write (RAM) STATIC (SRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential DYNAMIC (DRAM) Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended
6-transistor CMOS SRAM Cell WL M 2 M 4 Q M Q M 5 6 M 1 M 3 BL BL
CMOS SRAM Analysis (Read) WL BL M 4 Q = 0 Q = 1 M 6 M 5 BL M 1 C bit C bit
Voltage Rise (V) CMOS SRAM Analysis (Read) 1.2 1 0.8 0.6 0.4 0.2 Voltage rise [V] 0 0 0.5 1 1.2 1.5 2 Cell Ratio (CR) 2.5 3
CMOS SRAM Analysis (Write) WL M 4 Q = 0 M 6 M 5 Q = 1 M 1 BL = 1 BL = 0
6T-SRAM Layout M2 M4 Q Q M1 M3 M5 M6 GND WL BL BL
Resistance-load SRAM Cell WL R L R L M 3 Q Q M 4 BL M 1 M 2 BL Static power dissipation -- Want R L large Bit lines precharged to to address t p problem
SRAM Characteristics
3-Transistor DRAM Cell BL 1 BL 2 WWL RWL WWL M 3 RWL M 1 X M 2 X 2 V T C S BL 1 BL 2 2 V T D V No constraints on device ratios Reads are non-destructive Value stored at node X when writing a 1 = V WWL -V Tn
3T-DRAM Layout BL2 BL1 GND RWL M3 M2 WWL M1
1-Transistor DRAM Cell Write: C S is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance D V = V BL V PRE = V BIT V PRE C S ------------ C S + C BL Voltage swing is small; typically around 250 mv.
DRAM Cell Observations 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells. The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a 1 into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than
Sense Amp Operation V BL V (1) V PRE D V (1) Sense amp activated Word line activated V (0) t
1-T DRAM Cell Capacitor Metal word line Poly n + n + Inversion layer Poly induced by plate bias Cross-section SiO 2 Field Oxide Diffused bit line Polysilicon gate Layout Polysilicon plate M 1 word line Uses Polysilicon-Diffusion Capacitance Expensive in Area
SEM of poly-diffusion capacitor 1T-DRAM
Advanced 1T DRAM Cells Word line Insulating Layer Cell plate Capacitor dielectric layer Cell Plate Si Capacitor Insulator Refilling Poly Transfer gate Storage electrode Isolation Storage Node Poly 2nd Field Oxide Si Substrate Trench Cell Stacked-capacitor Cell
Periphery Decoders Sense Amplifiers Input/Output Buffers Control / Timing Circuitry
Row Decoders Collection of 2 M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder
Hierarchical Decoders Multi-stage implementation improves performance WL 1 WL 0 A 0 A 1 A 0 A 1 A 0 A 1 A 0 A 1 A 2 A 3 A 2 A 3 A 2 A 3 A 2 A 3 A 1 A 0 A 0 A 1 A 3 A 2 A 2 A 3 NAND decoder using 2-input pre-decoders
Dynamic Decoders Precharge devices GND GND WL 3 WL 3 WL 2 WL 2 WL 1 WL 0 WL 1 WL 0 f A 0 A 0 A 1 A 1 A 0 A 0 A 1 A 1 f 2-input NOR decoder 2-input NAND decoder
4-input pass-transistor based column decoder BL 0 BL 1 BL 2 BL 3 A 0 S 0 S 1 S 2 A 1 S 3 2-input NOR decoder Advantages: speed (t pd does not add to overall memory access time) Only one extra transistor in signal path Disadvantage: Large transistor count D
4-to-1 tree based column decoder BL 0 BL 1 BL 2 BL 3 A 0 A 0 A 1 A 1 D Number of devices drastically reduced Delay increases quadratically with # of sections; prohibitive for large decoders Solutions: buffers progressive sizing combination of tree and pass transistor approaches
Decoder for circular shift-register WL 0 R f f f f R WL 1 f f f f R WL 2 f f f f
Sense Amplifiers t p = C D V ---------------- I av make D V as small as possible large small Idea: Use Sense Amplifer small transition s.a. input output
Differential Sense Amplifier M 3 M 4 y Out bit M 1 M 2 bit SE M 5 Directly applicable to SRAMs
Differential Sensing SRAM PC BL EQ BL y M 3 M 4 2 y WL i x M 1 M 2 2 x x 2 x SE M 5 SE SRAM cell i SE x Diff. Sense 2 x Amp y Output Output (a) SRAM sensing scheme SE (b) two stage differential amplifier
Latch-Based Sense Amplifier (DRAM) EQ BL BL SE SE Initialized in its meta-stable point with EQ Once adequate voltage gap created, sense amp enabled with SE Positive feedback quickly forces output to a stable operating point.
Reliability and Yield
Noise Sources in 1T DRam BL substrate Adjacent BL C WBL a -particles WL leakage C S electrode C cross
Open Bit-line Architecture Cross Coupling EQ BL WL 1 WL 0 WL C D WL WBL C D WL 0 WL 1 WBL BL C BL C C C Sense Amplifier C C C C BL
Folded-Bitline Architecture WL 1 WL 1 WL 0 WL 0 WL D C WBL WL D BL C BL x y C C C C C C EQ Sense Amplifier BL C BL x y C WBL
Transposed-Bitline Architecture BL 9 BL BL BL 99 C cross (a) Straightforward bit-line routing SA BL 9 BL BL BL 99 C cross SA (b) Transposed bit-line architecture
Alpha-particles (or Neutrons) a -particle WL BL n 1 1 1 2 1 1 2 2 2 2 1 2 1 SiO 2 1 Particle ~ 1 Million Carriers
Redundancy Redundant columns Redundant rows Memory Array Row Address Fuse : Bank Column Decoder Row Decoder Column Address
Error-Correcting Codes Example: Hamming Codes with e.g. B3 Wrong 1 1 = 3 0
Redundancy and Error Correction
Sources of Power Dissipation in CHIP I DD 5 S C i D V i f 1S I DCP C PT V INT f nc DE V INT f selected m mi act I DCP n ROW DEC non-selected ARRAY m(n 2 1)i hld PERIPHERY mc DE V INT f COLUMN DEC V SS From [Itoh00]
Programmable Logic Array Pseudo-NMOS PLA GND GND GND GND GND GND GND X 0 X 0 X 1 X 1 X 2 X 2 f 0 f 1 AND-plane OR-plane
Dynamic PLA f AND GND f OR f AND X 0 X 0 X 1 X 1 X 2 X 2 f 0 f 1 GND f OR AND-plane OR-plane
Semiconductor Memory Trends (updated) From [Itoh01]
Trends in Memory Cell Area From [Itoh01]
Semiconductor Memory Trends Technology feature size for different SRAM generations