OptiMOS 2 Small-Signal-Transistor

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not recommended for new designs

Transcription:

OptiMOS Small-Signal-Transistor Features Dual N-channel Enhancement mode Ultra Logic level (1.8V rated) Avalanche rated Qualified according to AEC Q11 1% lead-free; RoHS compliant Product Summary V DS V R DS(on),max V GS =.5 V 4 mw V GS =1.8 V 56 I D.88 A PG-SOT-363 6 5 4 Halogen-free according to IEC6149--1 1 3 Type Package Tape and Reel Information Marking Lead Free Packing PG-SOT-363 H637: 3 pcs/ reel XBs Yes Non dry Maximum ratings, at T j =5 C, unless otherwise specified Parameter 1) Symbol Conditions Value Unit Continuous drain current I D T A =5 C.88 A T A =7 C.71 Pulsed drain current I D,pulse T A =5 C 3.5 Avalanche energy, single pulse E AS I D =.88 A, R GS =16 W 1.6 mj Reverse diode dv /dt dv /dt I D =.88 A, V DS =16 V, di /dt = A/µs, T j,max =15 C 6 kv/µs Gate source voltage V GS ±8 V Power dissipation ) P tot T A =5 C.5 W Operating and storage temperature T j, T stg -55... 15 C ESD Class JESD-A114 -HBM (<5V) Soldering Temperature 6 C IEC climatic category; DIN IEC 68-1 55/15/56 1) Remark: only one of both transistors in operation. Rev.4 page 1 14-9-19

Parameter Symbol Conditions Values Unit min. typ. max. Thermal characteristics Thermal resistance, junction - ambient R thja minimal footprint ) - - 5 K/W Electrical characteristics, at T j =5 C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS = V, I D =5 µa - - V Gate threshold voltage V GS(th) V DS =V GS, I D =1.6 µa.3.55.75 Drain-source leakage current I DSS V DS = V, V GS = V, T j =5 C V DS = V, V GS = V, T j =15 C - - 1 ma - - 1 Gate-source leakage current I GSS V GS =8 V, V DS = V - - 1 na Drain-source on-state resistance R DS(on) V GS =1.8 V, I D =.19 A - 373 56 mw V GS =.5 V, I D =.88 A - 7 4 Transconductance g fs V DS > I D R DS(on)max, I D =.71 A.5 - S ) Performed on 4 mm FR4 PCB. The traces are 1mm wide, 7μm thick and mm long; they are present on both sides of the PCB Rev.4 page 14-9-19

Parameter Symbol Conditions Values Unit min. typ. max. Dynamic characteristics Input capacitance C iss - 55 78 pf Output capacitance C oss V GS = V, V DS =1 V, f =1 MHz - 5 36 Reverse transfer capacitance C rss - 3.5 - Turn-on delay time t d(on) - 1.9 - ns Rise time t r V DD =1 V, V GS =.5 V, -. - Turn-off delay time t d(off) I D =.88 A, R G,ext =6 W - 7.8 - Fall time t f -.9 - Gate Charge Characteristics Gate to source charge Q gs -.1 - nc Gate to drain charge Q gd V DD =1 V, I D =.88 A, -.1 - Gate charge total Q g V GS = to.5 V -.6 - Gate plateau voltage V plateau - 1.7 - V Reverse Diode Diode continous forward current I S T A =5 C - -.5 A Diode pulse current I S,pulse - - 3.5 Diode forward voltage V SD V GS = V, I F =.88 A, T j =5 C -.94 1.1 V Reverse recovery time t rr V R =1 V, I F =.88 A, - 5.3 - ns Reverse recovery charge Q rr di F /dt =1 A/µs -.8 - nc Rev.4 page 3 14-9-19

Z thja [K/W] P tot [W] 1 Power dissipation Drain current P tot =f(t A ) I D =f(t A ); V GS.5 V.6 1.5.8.6.3..1. 4 8 1 16 4 8 1 16 T A [ C] T A [ C] 3 Safe operating area 4 Max. transient thermal impedance I D =f(v DS ); T A =5 C; D = Z thja =f(t p ) parameter: t p parameter: D =t p /T 1 1 1 3 1 µs 1 µs 1 1 µs.5 1-1 DC 1 ms 1 ms 1..1.5.1 1-1 1 single pulse 1-3 1-1 -1 1 1 1 1 V DS [V] 1 1-5 1-4 1-3 1-1 -1 1 1 1 1 t p [s] Rev.4 page 4 14-9-19

g fs [S] R DS(on) [mw] 5 Typ. output characteristics 6 Typ. drain-source on resistance I D =f(v DS ); T j =5 C R DS(on) =f(i D ); T j =5 C parameter: V GS parameter: V GS 9 8 1.3 V 1.4 V 1.6 7 1.5 V 1.6 V 6 1. 5 1.8 V.8.5 V V 1.8 V 1.6 V 1.5 V 4 3 V.5 V 1.4 V 1.3 V 1 1. V..6.8 1..6.8 1 V DS [V] 7 Typ. transfer characteristics 8 Typ. forward transconductance I D =f(v GS ); V DS > I D R DS(on)max g fs =f(i D ); T j =5 C 5 1.6 4 1. 3.8 15 C 5 C 1..5 1. 1.5..5 V GS [V] 1 1 3 3 Rev.4 page 5 14-9-19

C [pf] I F [A] R DS(on) [mw] V GS(th) [V] 9 Drain-source on-state resistance 1 Typ. gate threshold voltage R DS(on) =f(t j ); I D =.88 A; V GS =.5 V V GS(th) =f(t j ); V DS =V GS ; I D =1.6 µa parameter: I D 7 1. 6 5.8 98 % 98 % 4 typ 3 typ % 1-6 - 6 1 14 18 T j [ C] - -6-6 1 14 18 T j [ C] 11 Typ. capacitances 1 Forward characteristics of reverse diode C =f(v DS ); V GS = V; f =1 MHz; T j =5 C I F =f(v SD ) parameter: T j 1 1 1 Ciss Coss 1 1 1 1-1 Crss 15 C 1-5 C 15 C, 98% 5 C, 98% 1 5 1 15 1-3.8 1. 1.6 V DS [V] V SD [V] Rev.4 page 6 14-9-19

V BR(DSS) [V] I AV [A] V GS [V] 13 Avalanche characteristics 14 Typ. gate charge I AS =f(t AV ); R GS =16 W parameter: T j(start) 1 V GS =f(q gate ); I D =.88 A pulsed parameter: V DD 5 5 C 4 1-1 1 V 1 C 3 4 V 1-15 C 1 1 1 1 1 3 1 4 1 16 V t AV [µs].1..3.5 Q gate [nc] 15 Drain-source breakdown voltage 16 Gate charge waveforms V BR(DSS) =f(t j ); I D =5 µa 5 4 3 V GS Q g 1 V gs(th) 19 18 17 Q g(th) Q sw Q gate 16-6 - 6 1 14 T j [ C] Q gs Q gd Rev.4 page 7 14-9-19

SOT-363 Package Outline: Footprint: Packing: Reflow soldering: Note: For symmetric types there is no defined Pin 1 orientation in the reel. Dimensions in mm Rev.4 page 8 14-9-19

Published by Infineon Technologies AG 8176 Munich, Germany 8 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev.4 page 9 14-9-19