INTRODUTION TO LOGI IRUITS Notes - Unit 1 OOLEN LGER This is the oundtion or designing nd nlyzing digitl systems. It dels with the cse where vriles ssume only one o two vlues: TRUE (usully represented y the symol '1'), nd LSE (usully represented y the symol '0'). This is lso clled Two-vlued oolen lger or Switching lger. circuit consisting o switches cn e represented in terms o oolen lgeric equtions. The equtions cn e then mnipulted into the orm representing the simplest circuit. The circuit my then e immeditely drwn rom the equtions. This powerul method irst ppered in: symolic nlysis o Rely nd Switching ircuits, lude E. Shnnon, Trnsctions o the IEE, vol. 57, no. 12, Dec. 198, pp. 71-721. SI OPERTIONS nd re oolen vriles. oolen vriles re used to represent the inputs or outputs o digitl circuit. OPERTION OOLEN EPRESSION OPERTION NOT ( or ) Logicl negtion ND. Logicl conjunction o two sttements OR + Logicl disjunction o two sttements TRUTH TLES ND LOGI GTES Truth Tle: tulr listing o unction vlues or ll possile comintions o vlues on its input rguments. I there re n inputs, there re 2 n possile comintions. Logic Gtes: Hrdwre components tht produce logic 1 or logic 0 depending on the stte o inputs. oolen unctions cn e implemented with logic s. NOT = ' 0 1 1 0 = ' ND =. =. OR = + = + Logic Gtes (ND, OR) cn hve multiple inputs: Z =..Z... Z = ++Z+......... IOMS 0.0 = 0 1.1 = 1 0.1 = 1.0 = 0 0 = 1 1+1=1 0+0 = 0 1+0 = 0+1 = 1 1 = 0 1 Instructor: Dniel Llmocc
THEOREMS Vrile dominnt rule ommuttive rule omplement rule Idempotency Identity Element Doule negtion ssocitive rule Distriutive rule. 1 = + 0 =. =. + = +. = 0 + = 1. = + =. 0 = 0 + 1 = 1 =. (. Z) = (. ). Z + ( + Z) = ( + ) + Z. ( + Z) =. +. Z +. Z = ( + ). ( + Z) Other Theorems sorption djcency onsensus DeMorgn Simpliiction. ( + ) =. +. = +. =. (1 + ) = +. =. (1 + ) =. +. = ( + )( + ) =. + Z + Z = + Z ( + )( + Z)( + Z) = ( + )( + Z) orollry: ( + )( + Z) = + Z. = +,.. Z = + + Z + + =., + + Z+... =.. Z. ( + ) =. + = + useul ppliction o the theorems is on the simpliiction o oolen unctions which leds to the reduction o the mount o logic s: = ( + + D + E)( + + D ) + E = ( + )( + ), = +, = D + E = ( + )( + ) = = + = ( )Z + + Z = Z + Z = Z( + ) = Z = + Z = ( + )( + ) = + + + = + ( + ) = + = = x 1 x 2 + x 1 x 2 + x 2 x 1 = x 1 x 2 + (x 1 2 + x ) 2 = x 1 x 2 + x 1 = x 1 + x 1 x 2 = (x 1 + x 1 )(x 1 + x 2 ) = x 1 + x 2 = ( + ) + = (. + ) = ( + ). + = ( ). + = 2 Instructor: Dniel Llmocc
DERIVING OOLEN UNTIONS ROM TRUTH TLES Using 1s: 0 0 1 0 1 1 1 1 = + + Using 0s: 0 0 1 0 1 1 1 1 = ( + + )( + + ) Other Logic Gtes NND NOR OR = + = NOR = + = Instructor: Dniel Llmocc
SUM O PRODUTS (SOP) ND PRODUT O SUMS (POS) USING MINTERMS ND MTERMS: MINTERMS nd MTERMS ( vrile unction) x 1 x 2 x Minterms Mxterms 0 m 0 = x 1 x 2 x M 0 = x 1 + x 2 + x 1 m 1 = x 1 x 2 M 1 = x 1 + x 2 + x 2 m 2 = x 1 x 2 x M 2 = x 1 + x 2 + x m = x 1 x 2 x M = x 1 + x 2 + x 4 m 4 = x 1 x 2 x M 4 = x 1 + x 2 + x 5 m 5 = x 1 x 2 M 5 = x 1 + x 2 + x 6 m 6 = x 1 x 2 x M 6 = x 1 + x 2 + x 7 m 7 = x 1 x 2 x M 7 = x 1 + x 2 + x unction with n vriles cn hve up to 2 n minterms (or 2 n mxterms) rom m 0 to m 2 n 1 (or rom M 0 to M 2 n 1) Note tht: m i = M i. lso, or n vriles, the totl numer o dierent unctions is 2 2n. unction cn e expressed s sum o minterms or s product o mxterms: When minterm evlutes to 1, it implies tht the unction evlutes to 1. Exmple: (x, y) = xy + x y. Here, (x, y) = 1 i xy = 00,11. Thus, the minterms re m 0 nd m. (x, y) = m 0 + m When mxterm evlutes to 0, it implies tht the unction evlutes to 0. Exmple: (x, y) = (x + y )(x + y). Here, (x, y) = 0 i xy = 10,01. Thus, the mxterms re M 1 nd M 2. (x, y) = M 1 M 2 sum o products (SOP) tht include only minterms or product o sums (POS) tht contin only mxterms re clled nonicl orms. I SOP includes terms tht re not minterms (or POS includes terms tht re not mxterms), they re clled noncnonicl orms. or exmple: (x 1, x 2, x ) = x 1 x 2 x + x 1 x 2 (x 1, x 2, x ) = (x 1 + x 2 + x )(x 1 + x ) 2 (x 1, x 2, x ) = x 1 x 2 x + x 1 x 2 + x 1 2 x + (x 1 + x 2 + x ) Exmple: Z Sum o Products 0 = Z + Z + Z + Z 0 (,, Z) = (m 1, m 4, m 5, m 6 ). 0 (,, Z) = m(1,4,5,6) lso: (,, Z) = m(0,2,,7) 0 1 Product o Sums 1 = ( + + Z)( + + Z)( + + Z )( + + Z ) 1 (,, Z) = (M 0, M 2, M, M 7 ). 0 (,, Z) = M(0,2,,7) lso: (,, Z) = M(1,4,5,6) Note how (,, Z) = m(1,4,5,6) = M(0,2,,7). TIMING DIGRMS G G 4 Instructor: Dniel Llmocc
ILIN PG IMPLEMENTTION - DESIGN LOW Design Entry: Here, the circuit is speciied vi Hrdwre Description Lnguge (HDL), Schemtic, or wveorm. The process o veriiction o the HDL syntx o schemtic connections is clled Synthesis. ehviorl Simultion: This is crucil step. our Design Entry might e 'error-ree' syntx-wise, ut it might not work s expected. Here, we provide time-vrying stimuli to the inputs o logic circuit nd veriy tht the outputs re correct. When the stimuli is written in HDL, it is clled 'test-ench'. This process is very similr to using signl genertor to crete the inputs, nd using scope to visulize the outputs over time. Physicl Mpping: Here we speciy which inputs nd outputs mp to the speciic components o the PG we selected nd the Printed ircuit ord (P) tht houses the PG. In ilinx Vivdo, this is done vi ile clled onstrints ile (.xdc) Timing Simultion: ehviorl Simultion only simultes the circuit 'logiclly', i.e., it does not tke into ccount nlog nd electricl eects. Timing simultion does consider the dely tht exist etween inputs nd outputs, nd thereore it is very useul to determine glitches, hzrds, etc. Implementtion: Here, we "progrm" the PG. In this step, we gr conigurtion ile (clled 'itstrem') nd then downlod it onto the PG conigurtion memory. PRTIE EERISES Simpliy the ollowing unctions: = Z + Z + Z + Z (,, Z) = (m 0, m 2, m 6 ) = ( + + Z)( + + Z ) = ( + + D)( + D) = ( + D ) + (,, Z) = (M, M 4, M 7 ) Using oolen lger Theorems, prove tht: The OR opertion is ssocitive: c = ( ) c = ( c) = ( c). ( c) = () (c) Provide the oolen unctions nd sketch the logic circuit. Use the two representtions: i) Sum o Products, ii) Product o Sums. lso, provide the minterms nd mxterms representtions. 1 2 4 5 6 7 1 0 0 1 1 1 0 0 1 1 1 0 1 0 1 1 0 0 1 1 1 1 1 Otin the logic unction (nd minimize i possile) o the ollowing circuits: Drw the timing digrm o the ollowing circuit: Design circuit tht veriies the logicl opertion o the OR. = '1' (LED ON) i the OR works properly. ssumption: when the OR is not working, it is generting 1's insted o 0's nd vice vers. Tip: irst, generte the truth tle. x? Security comintion: lock only opens when the 8 switches re set s in the igure. Get the unction tht opens the lock ( logicl '1' is generted) when the switches re conigured s in the igure. Ech switch represents oolen vrile. Here, n open lock is represented y n LED tht is ON. ON (1) O (0) 5 Instructor: Dniel Llmocc