EE 505 Lecture 11 Offset Voltages DC Design
Offset Voltages ll DCs have comparators and many DCs and DCs have operational amplifiers The offset voltages of both amplifiers and comparators are random variables and invariably are key factors affecting the performance of a data converter Operational mplifiers: Generally differential amplifiers whose offset is dominantly determined by randomness in the first stage Comparators: High Gain Operational mplifiers Latching Structures (often clocked) Combination of High Gain mplifiers and Latching Structures Offset voltages of high-gain amplifiers well understood Offset voltage of Latching Structures often difficult to determine and can be very large
Consider First Offset in Operational mplifiers V 1 V Differential mplifier Input-referred Offset Voltage: Differential Voltage that must be applied to the input to make the output assume its desired value Note: With a good design, a designer will have at the desired value if the components assume the values used in the design ny difference in the output from what is desired when components assume the nominal values used in a design is attributable to a systematic offset voltage
nalysis of Offset Voltage Review from previous lecture: but VT 0 Cox L W V T R C OXR L R W R WL WL WL WL W L C L W N OXN N N So the offset variance can be expressed as L VTn0 p 1 VTp0 V OS W1L 1 nw1 L3 plw 1 3 1 1 1 n p VEB3 Cox W L nl3w 1 W3L3 W1L 1 W3L3 W1L 1 W3 L3 W1 L1 W1L 1 W3L3 Often this can be approximated by 0 pl1 VTp 0 plw 1 3 1 VTn 1 1 n p V V OS EB3 Cox W1L 1 nw1 L3 nl3w 1 W3L3 W1L 1 W3L3 W1L 1 Or even approximated by L VTn0 p 1 VTp0 V OS W1L 1 nw1 L3
Offset Voltage Two types of offset voltage: Systematic Offset Voltage Random Offset Voltage V ICQ Definition: The output offset voltage is the difference between the desired output and the actual output when V id =0 and V ic is the quiescent commonmode input voltage. OFF = - VOUTDES Note: OFF is dependent upon V ICQ although this dependence is usually quite weak and often not specified
Offset Voltage V OFF V ICQ Definition: The input-referred offset voltage is the differential dc input voltage that must be applied to obtain the desired output when V ic is the quiescent common-mode input voltage. Note: V OFF is usually related to the output offset voltage by the expression V V OUTOFF OFF= C Note: V OFF is dependent upon V ICQ although this dependence is usually quite weak and often not specified
Offset Voltage Two types of offset voltage: Systematic Offset Voltage Random Offset Voltage V ICQ fter fabrication it is impossible (difficult) to distinguish between the systematic offset and the random offset in any individual op amp Measurements of offset voltages for a large number of devices will provide mechanism for identifying systematic offset and statistical Characteristics of the random offset voltage
Systematic Offset Voltage Offset voltage that is present if all device and model parameters assume their nominal value Easy to simulate the systematic offset voltage lmost always the designer s responsibility to make systematic offset voltage very small Generally easy to make the systematic offset voltage small Can tweak out systematic offset after design is almost done Random Offset Voltage Due to random variations in process parameters and device dimensions Random offset is actually a random variable at the design level but deterministic after fabrication in any specific device Distribution of native offset nearly Gaussian (If offset compensation is not employed) Has zero mean Characterized by its standard deviation or variance Often strongly layout dependent
Offset Voltage V OS Can be modeled as a dc voltage source in series with the input
Offset Voltage Effects of Offset Voltage - an example V IN R 1 R Desired I/O relationship V M t V IN
Effects of Offset Voltage - an example Desired I/O relationship Offset Voltage V IN R 1 R V M t ctual I/O relationship due to offset V IN V M t V IN V M t V IN
Offset Voltage V OS V OS Effects can be reduced or eliminated by adding equal amplitude opposite phase DC signal (many ways to do this) One such technique is dynamic offset compensation Widely used in offset-critical applications Comes at considerable effort and expense Prefer to have designer make V OS small in the first place though penalty for making it sufficiently small without correction is often unacceptable
Dynamic Offset Compensation V OS V OS Most basic dynamic offset compensation at input
Effects of Offset Voltage Deviations in performance will change from one instantiation to another due to the random component of the offset Particularly problematic in high-gain circuits major problem in many other applications Not of concern in many applications as well
Offset Voltage Distribution number -6-5 -4-3 - -1 1 3 4 5 6 Offset Voltage Bins Typical histogram of native offset voltage (binned) after fabrication
Offset Voltage Distribution Gaussian (Normal) pdf number -6-5 -4-3 - -1 1 3 4 5 6 Offset Voltage Bins Typical histogram of offset voltage (binned) after fabrication Mean is nearly 0 (actually the systematic offset voltage)
Offset Voltage Distribution number -6-5 -4-3 - -1 1 3 4 5 6 Offset Voltage Bins Typical histogram of offset voltage (binned) in shipped parts when entire population used for a single produce Extreme offset parts have been sifted at test
Offset Voltage Distribution number -6-5 -4-3 - -1 1 3 4 5 6 Offset Voltage Bins Typical histogram of offset voltage (binned) in shipped parts Low-offset parts sold at a premium Extreme offset parts have been sifted at test
Source of Random Offset Voltages Consider as an example: R 1 R M 1 M V SS Ideally R 1 =R =R N, M 1 and M are matched I V = V - T R OUT DD N ssume this is the desired output voltage
Source of Random Offset Voltages Consider as an example: R 1 R M 1 M If everything ideal except R 1 =and R I V T OUT-R = - R V SS R 1 =R N +R R1 R =R N +R R Thus at the design stage, is also a random variable IT V OUT = VDD- R N +RR R
Source of Random Offset Voltages Consider as an example: R 1 R R 1 R M 1 M -V d / M 1 M V d / V SS V SS g m VN = - R N
Source of Random Offset Voltages Determine the offset voltage i.e. value of V X needed to obtain desired output R N +R R1 R N +R R V X M 1 M g m V = - R N IT I V T OUT= VDD - RN - R R - VVX I V T OUT-DES= VDD - RN Setting =-DES and solving for V X, we obtain V SS -1 I V =V T R X OFF R V
Source of Random Offset Voltages Determine the offset voltage i.e. value of V X needed to obtain desired output R N +R R1 R N +R R V X M 1 M V SS g m V = - R -1 I V =V T R X OFF R V I I R I R R V X= R R = VEB g R g R I /V R R T T R T R R m N m N T EB N N V = V OS EB R R R N
Source of Random Offset Voltages Determine the offset voltage i.e. value of V X needed to obtain desired output R N +R R1 R N +R R V X M 1 M V SS If resistors are integrated and is the resistor area R R R N = R V = V OS VOS EB = V R R R N R EB R R N where R is the Pelgrom parameter Thus VOS = V EB R
Source of Random Offset Voltages The random offset voltage is almost entirely that of the input stage in most op amps V X M 3 M 4 V X M 3 M 4 V 1 M 1 M V S V V 1 M 1 M V V S (a) (b)
Random Offset Voltages Bulk Source Gate Drain Bulk Source n-channel MOSFET Gate Drain n-channel MOSFET Impurities vary randomly with position as do edges of gate, oxide and diffusions Model and design parameters vary throughout channel and thus the corresponding equivalent lumped model parameters will vary from device to device
Random Offset Voltages The random offset is due to missmatches in the four transistors, dominantly missmatches in the parameters {V T, μ,c OX,W and L} V X M 3 M 4 The relative missmatch effects become more pronounced as devices become smaller V 1 M 1 M V S V V Ti =V TN +V TRi C OXi =C OXN +C OXRi μ i =μ N +μ Ri W i =W N +W Ri L i =L N +L Ri Each design and model parameter is comprised of a nominal part and a random component
Random Offset Voltages V Ti =V TN +V TRi V X M 3 M 4 C OXi =C OXN +C OXRi μ i =μ N +μ Ri V 1 M 1 M V S V W i =W N +W Ri L i =L N +L Ri For each device, the device model is often expressed as μn μri COXN COXRi W N+WRi L L I = V -(V V ) 1+ λ +λ V Di GSi TN TRi N Ri DS N Ri Because of the random components of the parameters in every device, matching from the left-half circuit to the right half-circuit is not perfect This mismatch introduces an offset voltage which is a random variable
Offset Voltages V X M 3 M 4 I 3 I 4 I 1 I V OFF V INC M 1 M V S V INC R L V XX ssume currents at output node must satisfy relation I =I 4 Strategy: 1) Obtain expression for V OFF (referred to input) that forces I =I 4 ) Linearize expression in terms of design variables and decorrelate 3) Obtain σ VOS
nalysis of Offset Voltage μ C W I = V +V -V -V n1 OX1 1 D1 OFF INC S TH1 L1 μ C W I = V -V -V n OX D INC S TH L μ C W I = V -V -V p3 OX3 3 D3 X DD TH3 L3 μ C W I = V -V -V p4 OX4 4 D4 X DD TH4 L4 V X M 3 M 4 I 3 I 4 I 1 I M 1 M V OFF V S V INC V INC R L V XX Since I I D1 D3 μ C W L V +V -V -V = V -V -V OFF p3 OX3 3 1 INC S TH1 X DD TH3 μn1cox1w1 L3 Since I I D D4 μ C W L V -V -V = V -V -V p4 OX4 4 INC S TH X DD TH4 μncoxw L4
nalysis of Offset Voltage Define: L1 p3cox 3W3 a L C W 3 n1 OX1 1 b L C W p4 OX 4 4 L C W 4 n OX V X M 3 M 4 I 3 I 4 Substituting for a and b, it follows on eliminating V S that I 1 I ssume V V V X XN XR a a a N b b b N R R VTni VTnN VTnRi i 1, V V V i 3,4 Tpi TpN TpRi V V V a b V -V bv av OFF TH1 TH X DD TH4 TH3 V OFF V INC M 1 M V S V INC R L V XX Observe a N =b N and V XN - -V TpN =V EB3 Since the random part of V X multiplies only a-b which is small, it follows that V V an V VEB 3N V OFF TnR TpR ar br Will now obtain a R and b R V V V a b V bv av OFF TH1 TH EB3N TH4 TH3 V V V a b V a V V OFF THR1 THR R R EB3N N THR 4 THR3
nalysis of Offset Voltage V V V b a V a V V OFF TnR TnR R R EB3 N TpR 3 TpR 4 V X M 3 M 4 I 3 I 4 a LN 1 LR1 Np3 R3 COXN3 COXR3 WN 3 WR 3 L L C C W W N3 R3 Nn1 R1 OXN1 OXR1 N1 R1 x Recall for x small, 1 x 1 Likewise b R 1 1 1 x x L W 1 L L C C W W a 1 L W L L C C W W Thus L 1 3W 3 N Np N 1 LR1 L 3 3 1 3 1 3 3 3 1 1 R R R C C W W a OXR OXR R R R LN Nn WN LN 1 LN 3 N 3 N1 COXN 3 COXN1 WN 3 WN 3 a N N 1 Np 3 N 3 R1 R 3 R 3 R1 OXR 3 OXR 1 R 3 R 3 N3 Nn1 N1 N1 N3 Np3 Nn1 OXN 3 OXN1 N3 N3 L L W N1 Np3 N 3 W N 3 Nn1 N1 M 1 M L W 1 L L C C W W L W L L C C W W N1 Np3 N 3 R R 4 R 4 R OXR 4 OXR R 4 R V OFF N 3 Nn1 N1 N N 4 Np4 Nn OXN 4 OXN N 4 N V INC I 1 I V S V INC R L V XX
nalysis of Offset Voltage V X M 3 M 4 I 3 I 4 I 1 I V OFF V INC M 1 M V S V INC R L V XX a R b R LR1 LR LR 4 LR3 R3 R4 R R1 LN 1Np3W N3 1 LN 1 LN LN 4 LN 3 Np3 Np4 Nn Nn1 L W C C C C W W W W C C C C W W W W N3 Nn1 N1 OXR3 OXR 4 OXR OXR1 R3 R4 R R3 OXN3 OXN 4 OXN OXN1 N 3 N 4 N N 3 L W 1 N1 Np3 N3 a b L L C C W W N3 Nn1 N1 L L C C W W 1 3 3 3 1 3 1 L W R R R R R R OXR OXR R R N1 N 3 Np3 Nn OXN 3 OXN 1 N 3 N1 Thus L N1 Np3WN 3 V V V L W OFF TnR TpR 3 N3 Nn1 N1 L W 1 V N 3 Np 3 OXN 3 OXN 1 N 3 N1 Np3 N3 EB3 L L C C W W LN 3Nn1WN 1 L L C C W W R1 R 3 R 3 R OXR 3 OXR1 R 3 R1 N1 Nn N1
nalysis of Offset Voltage but VT 0 Cox L W V T R C OXR L R W R WL WL WL WL W L C L W N OXN N N So the offset variance can be expressed as V OFF V INC V X M 3 M 4 I 3 I 4 I 1 I M 1 M V S V INC R L V XX pl VTn W L W L 0 1 VTp0 VOFF 1 1 n 1 3 plw 1 3 1 1 1 n p VEB3 Cox W L nl3w 1 W3L3 W1L 1 W3L3 W1L 1 W3 L3 W1 L1 W1L 1 W3L3 Often this can be approximated by 0 pl1 VTp 0 plw 1 3 1 VTn 1 1 n p V V 3 OFF EB Cox W1L 1 nw1 L3 nl3w 1 W3L3 W1L 1 W3L3 W1L 1 Or even approximated by pl VTn W L W L 0 1 VTp0 VOFF 1 1 n 1 3
Random Offset Voltages Since V EBn and V EBp are related, this is often expressed in simpler form as: 1 1 1 1 + + μ μ COX + VTO n μ W L W L W L W L p L n V EB n σ + + VOS VTO p W nl n μ n W nl 4 p 1 1 1 1 + L + + w + W n L n W p L p L n W n L p W p n p n n p p n n p p where the terms VT0, μ, COX, L, and W are process parameters 1mV μ (n-ch) VT0 5mV μ (p-ch) μ+ C OX.016μ (n-ch).03μ (p-ch) V X M 3 M 4 L=W 0.017μ VTO n μ p L n VOS W VTO p n L n μ n W n L p σ + 3 Usually the VT0 terms are dominant, thus the variance simplifies to V 1 M 1 M V S V
Correspondingly: Random Offset Voltages V OS Wn L VTOn n p n L n n p W L VTOp V EBn 4 1 Wn L n L n 1 Wn L n 1 W L p p 1 p W L p p COX w L 1 W L n 1 n W n n L 1 W L p 1 p W p p which again simplifies to VTO n μ p L n VOS W VTO p n L n μ n W n L p σ + V X M 3 M 4 V 1 M 1 M V V S Note these offset voltage expressions are identical!
Random Offset Voltages Example: Determine the 3σ value of the input offset voltage for The MOS differential amplifier is a) M 1 and M 3 are minimum-sized and b) the area of M 1 and M 3 are 100 times minimum size V X a) VTO n μ p L n VOS W VTO p n L n μ n W n L p σ + μ p σ V + OS W VTO n VTO p n L n μ n 1 σ.01 +.05 OS 0.5 3 V σ V OS 7mV M 3 M 4 V 1 M 1 M V V S 3 σ 16mV V OS Note this is a very large offset voltage!
Random Offset Voltages Example: Determine the 3σ value of the input offset voltage for The MOS differential amplifier is a) M 1 and M 3 are minimum-sized and b) the area of M 1 and M 3 are 100 times minimum size VTO n μ p L n VOS W VTO p n L n μ n W n L p μ p σ + VOS W VTO n VTO p n L n μ n σ + b) 1 σ.01 +.05 VOS 1000.5 3 V X M 3 M 4 V 1 M 1 M V V S σ V OS 7.mV 3 σ 1.6mV V OS Note this is much lower but still a large offset voltage! The area of M 1 and M 3 needs to be very large to achieve a low offset voltage
Random Offset Voltages V CC V CC Q 3 V X Q 4 Q 3 V X Q 4 V 1 Q 1 Q V V 1 Q 1 Q V V E V E (a) (b) It can be shown that V OS where very approximately V Jn t + En = = 0.1μ Jn Jp Jp Ep
Random Offset Voltages V CC Example: Determine the 3σ value of the offset voltage of a the bipolar input stage if E1 = E3 =10μ Q 3 V X Q 4 V OS Jn V t + En Jp Ep V 1 Q 1 V E Q V V OS V t J E 1 5mV 0.1μ 1.6mV V OS 10μ 3 4.7mV V OS Note this value is much smaller than that for the MOS input structure!
Random Offset Voltages Typical offset voltages: MOS - 5mV to 50MV BJT - 0.5mV to 5mV These can be scaled with extreme device dimensions Often more practical to include offset-compensation circuitry
Offset voltage difficult to determine in come classes of comparators 1 1 M 13 M 5 M 6 M 14 V V 1 C 1 M 11 M 1 1 C 1 M 3 M 4 V IN M 7 M 8 V REF Dynamic clocked comparator When φ 1 is low, V 1 and V are precharged to and no static power is dissipated When φ 1 is high, enters evaluate state and no static power is dissipated
Offset voltage difficult to determine in come classes of comparators VDD Very small, very fast, low power 1 1 V C 1 M13 M5 M6 M11 M1 M14 1 V1 C1 But offset voltage can be large (100mV or more) M3 M4 VIN M7 M8 VREF Dynamic clocked comparator H V 1 or V Metastable Output L V or V 1 CLK Transition Decision is being made shortly after clock transition when devices are deep in weak inversion and signal levels are very small
dditional details about offset voltage, statistical circuit analysis, and matching can be found in the draft document Statistical Characterization of Circuit Functions by R.L. Geiger
Summary of Offset Voltage Issues Random offset voltage is generally dominant and due to mismatch in device and model parameters MOS Devices have large V OS if area is small σ decreases approximately with Multiple fingers for MOS devices 1/ offer benefits for common centroid layouts but too many fingers will ultimately degrade offset because perimeter/area ration will increase ( W and L will become of concern) Offset voltage of dynamic comparators is often large and analysis not straightforward Offset compensation often used when low offsets important MOS: Bipolar: VTO n μ p L n VOS W VTO p n L n μ n W n L p σ + V OS Jn V t + En Jp Ep
End of Lecture 11