Lecture 04 Review of MOSFET

ECE 541/ME 541 Microelectronic Fabrication Techniques Lecture 04 Review of MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu)

What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D

The MOS Transistor Polysilicon Aluminum

MOS Transistors - Types and Symbols D D G G S NMOS Enhancement D NMOS S Depletion D G G B PMOS S Enhancement S NMOS with Bulk Contact

The Gate Capacitance Polysilicon gate Source n + d d W Drain n + L d Top view Gate-bulk overlap t o Gate oide n + L n + Cross section

Threshold Voltage: Concept S - V GS + G D n+ n+ n-channel p-substrate Depletion Region B

The Threshold Voltage

The Body Effect 0.9 0.85 0.8 0.75 0.7 V T (V) 0.65 0.6 0.55 0.5 0.45 0.4 -.5 - -1.5-1 -0.5 0 V BS (V)

Current-Voltage Relations -4 10 6 VGS=.5 V 5 4 Resistive Saturation VGS=.0 V I D (A) 3 V DS = V GS -V T Quadratic Relationship VGS= 1.5 V 1 VGS= 1.0 V 0 0 0.5 1 1.5.5 V DS (V)

Transistor in Linear S V GS G V DS D I D n + V() + n + L p-substrate B MOS transistor and its bias conditions

Transistor in Saturation V GS G V DS > V GS - V T S D n+ - V GS - V T + n+ Pinch-off

Current-Voltage Relations Long-Channel Device

Velocity Saturation n (m/s) sat = 10 5 Constant velocity Constant mobility (slope = µ) c = 1.5 (V/µm)

Perspective I D Long-channel device V GS = V DD Short-channel device V DSAT V GS -V T V DS

I D versus V GS 6 10-4.5 10-4 5 4 quadratic 1.5 linear I D (A) 3 I D (A) 1 1 0 0 0.5 1 1.5.5 V GS (V) Long Channel 0.5 quadratic 0 0 0.5 1 1.5.5 V GS (V) Short Channel

I D versus V DS I D (A) 6 10-4 5 4 3 VGS=.5 V Resistive Saturation VGS=.0 V V DS = V GS -V T VGS= 1.5 V I D (A) 1.5 1-4.5 10 VGS=.5 V VGS=.0 V VGS= 1.5 V 1 VGS= 1.0 V 0.5 VGS= 1.0 V 0 0 0.5 1 1.5.5 V DS (V) Long Channel 0 0 0.5 1 1.5.5 V DS (V) Short Channel

A PMOS Transistor 0 10-4 VGS = -1.0V -0. VGS = -1.5V -0.4 I D (A) -0.6 VGS = -.0V Assume all variables negative! -0.8 VGS = -.5V -1 -.5 - -1.5-1 -0.5 0 V DS (V)

Outline (1) MOS fundamentals () MOS electrostatic: Quantitative analysis (3) MOS C-V characteristics (4) MOSFET (5) MOSFET small-signal equivalent circuit (6) Non-ideal MOS

(1) MOS fundamentals Metal-oide-semiconductor FET is the most important device in modern microelectronics. Hightlights Ideal MOS structure electrostatics MOS band diagram under applied bias Gate voltage relationship capacitance-voltage relationship under low frequency and under high frequency. 19

MOSFET N-channel MOSFET (NMOS) uses p-type substrate electrons P-Si 0

MOSFET operation I D Pinch-off V G3 V G V G3 > V G > V G1 V G1 V D When a positive voltage V G is applied to the gate relative to the substrate, mobile negative charges (electrons) gets attracted to Sioide interface. These induced electrons form the channel. For a given value of V G, the current I D increases with V D, and finally saturates. 1

Ideal MOS capacitor Let us consider a simple MOS capacitor and call it ideal Oide has zero charge, and no current can pass through it. No charge centers are present in the oide or at the oidesemiconductor interface. Semiconductor is uniformly doped M = S = + (E C E F ) FB

Equilibrium energy band diagram for an ideal MOS structure 3

Effect of an applied bias Let us ground the semiconductor and start applying different voltages, V G, to the gate V G can be positive, negative or zero with respect to the semiconductor E F, metal E F, semiconductor = qv G (Since electron energy = q V, when V < 0, electron energy increases) Since oide has no charge, d E oide / d = / = 0; i.e. the E- field inside the oide is constant. 4

Consider p-type Si, apply V G < 0 ' m qv G Accumulation of holes E C Ei E V E Fs Negative voltage attracts holes to the Si-oide interface. This is called accumulation condition. E i E F should increases near the surface of Si. E oide 0 Eoide const. 1 q E i The oide energy band has constant slope as shown. No current flows in Si E F in Si is constant. 5

Accumulation condition, V G < 0, p-type Si V G < 0 M O p-type Si E Sheet of electrons charge density E small + + Sheet of holes Accumulation of holes near silicon surface, and electrons near the metal surface. Similar to a parallel plate capacitor structure. 6

Consider p-type Si, apply V G > 0 (Depletion condition) E Depletion positive E + Finite depletion layer width + E FM E C E i E Fs E V + 0 ---- ---- negative M O S E 7

Consider p-si, apply V G >> 0 (Inversion condition) E + + + Immobile acceptors E C E i + ------- E FS ------- - E V - Mobile electrons E FM E FM E 8

Inversion condition If we continue to increase the positive gate voltage, the bands at the semiconductor bends more strongly. At sufficiently high voltage, E i can be below E F indicating large concentration of electrons in the conduction band. We say the material near the surface is inverted. The inverted layer is not gotten by doping, but by applying E-field. Where did we get the electrons from? When E i (surface) E i (bulk) = [E F E i (bulk)], the condition is start of inversion, and the voltage V G applied to gate is called V T (threshold voltage). For V G > V T, the Si surface is inverted. 9

Energy band diagrams and charge density diagrams describing MOS capacitor in n-type Si 30

Energy band diagrams and charge density diagrams describing MOS capacitor in p-type Si 31

Eample 1 Construct line plots that visually identify the voltage ranges corresponding to accumulation, depletion and inversion in ideal n- type Si (i.e. p-channel) and p-type Si (i.e. n-channel) MOS devices. Answer: 3

() MOS electrostatic: Quantitative analysis Highlights Derive analytical epressions for the charge density, electric field and the electrostatic potential. Epression for the depletion layer width Describe delta depletion solution Derive gate voltage relationship Gate voltage required to obtain inversion 33

Electrostatic potential, () Define a new term, () taken to be the potential inside the semiconductor at a given point. [The symbol instead of V used in MOS work to avoid confusion with eternally applied voltage, V] 1 ( ) [ Ei (bulk) Ei q ( )] Potential at any point S 1 q [ E i (bulk) E i (surface)] Surface potential F 1 q [ E i (bulk) E F ] F related to doping concentration F > 0 means p-type F < 0 means n-type 34

Electrostatic parameters S is positive if the band bends downward S = F at the depletion-inversion transition point 35

Eample Consider the following F and S parameters. Indicate whether the semiconductor is p-type or n-type, specify the biasing condition, and draw the energy band diagram at the biasing condition. (i) F = 1 kt/q; S = 1 kt/q F = +1 kt/q means that E i E F in the semiconductor is 1 kt (a positive value); So, p-type. N A = n i ep [(E i E F ) / kt] S =1 kt/q means E i (bulk) E i (surface) = 1 kt; i.e. the band bends downward near the surface. E C 1kT E i E F E V 36

Eample (continued) (ii) F = 9 kt/q; S = 18 kt/q here F = 9 kt/q means [E i (bulk) E F ] = 9 kt; i.e., E i E F. Thus the semiconductor is n-type. is below S = 18 kt/q means that E i (bulk) E i (surface) = 18 kt; So band bends upwards near the surface. The surface is inverted since the surface has the same number of holes as the bulk has electrons. E C -9kT E i E F E V 37

Delta-depletion solution Consider p-type silicon Accumulation condition V G < 0 M O S p-si The accumulation charges are mobile holes, and appear close to the surface and fall-off rapidly as increases. Assume that the free carrier concentration at the oidesemiconductor interface is a - function. Accumulation of holes Charge on metal = Q M Charge on semiconductor = (charge on metal) Q Accumulation = Q M 38

39 Homo-pn-junction Diode i D A i n p bi ln ln n N N q kt n n p q kt V n n D bi p ) p A 0 ) ( 0 ( ) ( qn V qn V n p n n D p p A 0 0 ) ( ) ( ; qn o qn E E ma = q N A p / = qn D n / N A N D D A D p A A n D N N N W N N N W W = n + p 1 bi D A D A / V N N N N q W Review

40 Schottky diode W W qn for 0 0 for D W qn 0 for d d Si D Si E Si D 0) ( W q N E FB F C B bi ) ( 1 E E q V 1 A bi D Si ) ( / V V q N W Review

Delta depletion solution (cont.) Consider p-type Si, depletion condition Apply V G such that s < F Charges in Si are immobile ions - results in depletion layer similar to that in pn junction or Schottky diode. V G > 0 M O S p-si W q N A A W = Q M () (+) If surface potential is s (with respect to the bulk), then the depletion layer width W will be qn Si A S 1 and E Si qn A W Q M At the start of inversion, s = F and E W W w E Si Depletion of holes de/d = qn A / si Si T qna F 1/ 41

Review Depletion layer width, W and E-field For a p + n junction, or a MS (n-si) junction, the depletion layer width is given by: 1/ Where V W Si Vbi qn bi is related to the amount of band bending. V bi in Volts is numerically D equal to the amount of band bending in ev. E ma qn Si D W qn Si D V bi 1/ For MOS, the same equation applies, ecept that V bi is replaced by s. E ma (in Si) qn Si D n-type s 1/ or qn Si A p-type s 1/ 4

Delta depletion solution (cont.) Consider p-si, strong inversion. Once inversion charges appear, they remain close to the surface since they are mobile. Any additional voltage to the gate results in etra Q M in gate and get compensated by etra inversion electrons in semiconductor. V G >>0 Q M M O S w p-si Depletion of holes Inversion electrons: -function-like So, depletion layer does not have to increase to balance the charge on the metal. Electrons appear as -function near the surface. Maimum depletion layer width W = W T 43

Gate voltage relationship Applied gate voltage will be equal to the voltage across the oide plus the voltage across the semiconductor. Consider p-type Si. V G = o + Semi Semi = ( = 0) (bulk) = S o = o E o V G > 0 M O o S p-si Semi Since the interface does not have any charges up to inversion, we can say that o E o = Si E Si E o = ( Si / o ) E Si 44

45 Gate voltage relationship (cont.) 1 s Si A F s 1 s A Si Si A Si A Si 0 for / / qn qn qn W qn E F s 1 s Si A o Si o s Si o Si o s o o s G 0 for / qn V E E

Gate-voltage relationship (Alternative method) Consider p-type silicon V G = o + Semi o = Q M /C o = Q s /C o where C o is oide capacitance and Q s is the depletion layer charge in semiconductor Q s = q A N A W C o = o A / o V G o s q A N A / o Si o A W o o qn Si A Si o W o s qn Si A Si o W o 1/ qna s Si (same as before) 46

(3) MOS C-V characteristics The measured MOS capacitance (called gate capacitance) varies with the applied gate voltage A very powerful diagnostic tool for identifying any deviations from the ideal in both oide and semiconductor Routinely monitored during MOS device fabrication Measurement of C-V characteristics Apply any dc bias, and superimpose a small ac signal Generally measured at 1 MHz (high frequency) or at variable frequencies between 1KHz to 1 MHz The dc bias V G is slowly varied to get quasi-continuous C-V characteristics 47

C-V characteristics of MOS-capacitor on p- and n-type Si C G C G V G V G p-type n-type The C-V data depends on the measurement frequency as well. The dotted line represents the low-frequency C-V data. 48

Measured C-V characteristics on an n-type Si N D = 9.0 10 14 cm 3 o = 0.119 m 49

MOS-capacitor under accumulation Consider p-type Si under accumulation. V G < 0 M O S p-si V G < 0. Looks similar to parallel plate capacitor. Accumulation of holes C G = C o where C o = ( o A) / o Thus, for all accumulation conditions, the gate capacitance is equal the oide capacitance. 50

MOS-capacitor under depletion Depletion condition: V G > 0 V G > 0 M O S p-type Si C G is C o in series with C s where C s can be defined as semiconductor capacitance Q M C o W C s Depletion of holes C o = o A / o C s = Si A / W C G = C o C s /(C o + C S ) W qn Si A s where s is surface potential In this case, the gate capacitance decreases as the gate voltage is increased. Why? 51

MOS-capacitor under inversion V G = V T and V G > V T Inversion condition s = F W W Si T qna F 1/ At high frequency, inversion electrons are not able to respond to ac voltage. So, to balance the charge on the metal, the depletion layer width will vary with the ac. V G >>0 Q M M O S W p-si Depletion of holes Inversion electrons - function C o = o A/ o C s = Si A/W T C G ()= C o C s / (C o + C S ) C o C s So, C G will be constant for V G V T 5

MOS-capacitor under inversion At low frequency, the inversion electrons will be able to respond to the ac voltage (Why?). So, the gate capacitance will be equal to the oide capacitance (similar to a parallel plate capacitance). C G (0) = C o = o A / o C o C G Low frequency For V G > V T, the high frequency capacitance remains constant. Why? C o C s / (C o +C s ) High frequency V T V G p-type Si 53

Eample 3 Consider n-type silicon doped with N A =10 16 cm 3. The oide thickness is 100 nm. Plot the C G vs. V G characteristics when V G is varied slowly from 5 V to +5 V. Assume MOS has area of 1 cm. Find C o. C o.98.910 10010 3 8 3.510 7 14 F/cm 1cm cm Find C s (min) when W = W T (Note that C s decreases as the depletion layer width increases. It is minimum when the depletion layer width is maimum, i.e. when W = W T ). W T 14 1/ 5 3.110 16 11.98.8510 19 1.610 C10 F/cm 0.357 V 3 cm F cm 0.31 μm C s (min) 14 11.98.8510 F/cm 5 3.110 cm 1cm 3.410 8 F C G (min) = (3.510 8 3.410 8 ) /(3.510 8 +3.410 8 ) F = 1.7 10 8 F 54

V Eample 3 (continued) 1/ Si qna G VT s o s when s o Si =.15 V Plot the C-V characteristics Eplain why C G does not vary for V G > V T 34.7 nf C G low-f 34.7nF F Question: How will you calculate C G when V G = 1V? Answer: Calculate s when V G = 1V using the eqn. above. From s find W, then calculate C s. Then, calculate C G = (C o C s ) / (C o + C s ) 17nF high-f.17 V p-type V G 55

MOS-capacitor characteristics: Deep depletion The previous discussions pertain to the condition when the gate voltage is ramped slowly, from accumulation condition to depletion and then to inversion condition. When the ramp rate is high, the inversion layer does not form and does not have time to equilibrate. This is called deep depletion condition. In this case, W will continue to increase beyond W T and C G will continue to decrease as shown when the dc bias is varied from accumulation bias to deep depletion bias. To calculate W under deep depletion condition, invert the V G versus s relationship. Solve for s 1/ and hence s. Then, calculate W using W versus s relationship. 56

Some observations V T = gate voltage required for start of inversion = (+) for p-type Si = () for n-type Si Si qn V A T F o o Si (+) () F 1/ (+) - for p-type Si () - for n-type Si Higher the doping, higher the V T value C ma = C o and C min = C o C s / (C o + C s ) Lower the doping, lower C s and hence lower C min 57

Doping dependence of MOS-capacitor high frequency C- V characteristics, with o = 0.1m 58

MOS-capacitor under deep depletion V G s o Si o qn Si A s 1/ W qn Si A s 1/ n-type Si C s = Si A / W C o = o A / o C G = C o C s / (C o + C s ) 59

Eample 4 Consider eample 1. Plot C-V characteristics if V G is varied from 5 V to + 5 V rapidly. C G (5 V) = C o =34.7 nf, as before. C G (V G = V T ) = 17 nf, as before. C G (V G > V T ) will continue to reduce (unlike the quasi-steady state condition of eample 1). When V G = 5 V, 5 y s 100010 1. 69y 8 where 1. 610 3 10 y s 19 1 Solving for s, we get s =.38 V 10 W = 0.545 m; C s = 18.3 nf; C G = 1 nf 16 s 1/ 34.7 nf C G.15 V Not under steady state 1 nf 5V V G 60

(4) MOSFET MOSFET based ICs have become dominant technology in the semiconductor industry. Qualitative theory of operation Quantitative I D vs. V DS characteristics Small-signal equivalent circuits. N-channel MOSFET Substrate: p-type Si 61

Qualitative discussion: NMOS N + N + 0 < V G < V T ; V DS small or large no channel, no current p-si V G > V T ; V DS 0 I D increases with V DS V G > V T ; V DS small, > 0 I D increases with V DS, but rate of increase decreases. V G > V T ; V DS pinch-off I D reaches a saturation value, I D,sat The V DS value is called V DS,sat V G > V T ; V DS > V DS,sat I D does not increase further, saturation region. 6

I D -V DS characteristics for NMOS derived from qualitative discussions Linear region Saturation region 63

I D -V DS characteristics epected from a long channel (L << L) MOSFET (n-channel), for various values of V G 64

Threshold voltage for NMOS and PMOS When V G = V T, s = F ; using equation 16.8, we get epression for V T. Si qn V A T F o o Si F 1/ Ideal n-channel (p-silicon) device both terms positive V qn Si Si D T F o o F 1/ Ideal p-channel (n-silicon) device both terms negative Si / o = ( Si o ) / ( o o ) = 11.9 / 3.9 3 65

Quantitative I D -V DS relationships G (V G ) S D (V DS ) 0 Q N = inversion layer charge Let be the potential along the channel V D For V G < V T, Inversion layer charge is zero. For V G > V T, Q n (y) = Q G = C o (V G V T ) In general, J n = q n n E when the diffusion current is neglected. Here, current I D is the same everywhere, but J n (current density) can vary from position to position. 66

Device structure, dimension, and coordinate orientations assumed in the quantitative analysis 67

68 Quantitative I D -V DS relationships (Shockley model) y n q n q J J y d d n n n n E y y d d ) ( E since To find current, we have to multiply the above with area, but J ny, n, etc. are functions of and z. Hence, area unit charge ) ( ) ( d d d d d d d d n n n n n n D / y Q y Q y Z qn y Z J Z z J I y y Integrating the above equation, and noting that I D is constant, we get d ) n ( 0 n D DS y Q L Z I V Since we know epression for Q n (y) in terms of, we can integrate this to get I D

Quantitative I D -V DS Relationships (cont.) I D Z L n C o V G V T V DS DS V 0 V V DS DS, sat ; V G V T I D will increase as V DS is increased, but when V G V DS = V T, pinchoff of channel occurs, and current saturates when V DS is increased further. This value of V DS is called V DS,sat. i.e., V DS,sat = V G V T and the current when V DS = V DS,sat is called I DS,sat. I D,sat ZC L o V V G T V ; VG VT D V DS, sat Here, C o is the oide capacitance per unit area, C o = o / o 69

Eample 5 Plot the I D vs. V DS characteristics for an NMOS with the following parameters: Substrate doping: 10 16 cm 3. Oide thickness = 100 nm Gate width = 15m; Gate length = 1 m. Assume n = 500 cm /(Vs) Find C o : C o = o / o = 33.3 nf/cm V I T D,sat F ZC L o o Si o V V G qn Si T A F V 1/. 15 V DS V DS, sat ; V G V T V DS,sat = V G V T Find I D,sat for different values of V G and plot the graph 70

(5) MOSFET small-signal equivalent circuit The dc characteristics for NMOS are reviewed below. I D I Z L D,sat n C o V ZC L G o V T V DS DS V V V G T 0 V V DS DS, sat DS V DS, sat ; VG V T V ; VG VT Linear region Saturation region 71

MOSFET ac response MOSFET ac response is routinely epressed in terms of smallsignal equivalent circuits. This circuit can be derived from the two-port network shown below: G input S MOSFET D output S The input looks like an open circuit, ecept for the presence of the gate capacitor. At output, we have a current I D which is controlled by V G and V DS. I D = f (V G, V DS ) 7

MOSFET small-signal equivalent circuit Any ac signal in V G or V DS will result in corresponding ac variation in I D I D I V D G V DS V G I V D DS V G V DS i d g m v g g d v d where g m I V D G V DS and g d I V D DS V G g m = trans-conductance g d = drain or channel conductance Note: i d,v g and v d are small-signal ac currents and voltages. They are different from I D, V G and V DS which are dc currents and voltages. 73

Small-signal equivalent circuit So, the equivalent circuit at low-frequency looks like (neglecting the gate capacitance low frequency): For high-frequency, we have to include the capacitive effects: 74

MOSFET small-signal parameters When V DS < V DS,sat (i.e., below pinch-off or linear region) g d Z C L n o ( VG VT VDS) g m Z C L n o V DS When V DS > V DS,sat (i.e., above pinch-off or saturation region) g d = 0 g m Z C L n o ( V VT ) G Note: the parameters depend on the dc bias, V G and V DS 75

Frequency response of MOSFET The cut-off frequency f T is defined as the frequency when the current gain is 1. Input current = Output current = J C G v G g m v G v G here is ac signal C GS is approimately equal to the gate capacitance, Z L C o g So, at f T, mvg 1 f C v T GS G So, f T g C m GS 76

C G -V G characteristics: MOS-C versus MOSFET C G vs. V G characteristics of a MOSFET at high frequency looks similar to the lowfrequency response (unlike the MOS-C). This is because, even at high frequency, the source and drain can supply the minority carriers required for the structure to follow the ac fluctuations in the gate potential when the device is inversion biased. C G vs. V G characteristics of a MOSFET with V DS = 0 77

Enhancement mode MOSFETs The devices we discussed so far are called enhancement-mode MOSFETs. For NMOS, V T is positive and one has to apply a positive gate voltage to turn on the device. At zero gate voltage, the device will be off. For PMOS, V T is negative and one has to apply a negative gate voltage to turn on the device. At zero gate voltage, the device will be off. Eercise: Draw the I D -V DS characteristics for NMOS and PMOS enhancement-mode devices. Net class, we will discuss depletion-mode devices. 78

(6) Non-ideal MOS So far, we have discussed MOS characteristics making some assumptions - calling it ideal. Assumed that the M = S, i.e. the bands are flat when no voltage is applied. Assumed that the oide and oide-semiconductor interface are free of charges. These assumptions do not hold good in an actual MOS device, and we have to consider the deviations from the ideal case. For the purpose of discussions, we call these as real. 79

Metal-semiconductor work function difference - ideal When M = S, the Fermi level is aligned before we make the device. So, when the MOS structure is made, the band remains flat when the applied gate voltage is zero. Assumption MS = M S = 0 S Flat band condition M E FM M O S E FS 80

Metal-semiconductor work function difference - real M depends on the metal. Eample: M (Al) 4 ev, M (Au) 5.1 ev S depends on the semiconductor doping. S = + (E C E F ) FB So, MS = M S 0 in a real device. E FM M S So, actual band alignment before making the MOS-C structure looks as shown for Al-Si (p) M = Al M O S E FS 81

Band diagram for MS = M S 0 M S E FM M = Al E FS E FM E FS M O S S We have to apply a gate voltage = MS /q to get flat-band condition. 8

Polysilicon gate MOS Modern day devices generally use heavily doped polysilicon as the gate material. For p + -polysilicon gate, E FM can be assumed to be at E V. For n + -polysilicon gate, E FM can be assumed to be at E C. Question: If the substrate is intrinsic silicon, and the gate material is p + -polysilicon, calculate MS. ( MS = E g / = 0.55 ev) What is the voltage that has to be applied to the gate to get flat-band condition? V G = 0.55 ev/q = 0.55 V Question: If the substrate is n + -silicon, and the gate material is p + -polysilicon, calculate MS. ( MS = + 1.1 ev) Show MS by drawing the band diagram. 83

Interface and oide charges For the ideal device, we have assumed that the oide and the interface is devoid of any ecess charges. This is not true in practice. Na + Na + + + + + + + + + + + + + + + + + + + + ++ Si Q metal Q of Q of Q it Assume that all these charges are situated close to the interface on the oide side (even though they aren t) and their concentration is Q i Coulombs/cm. Q i = net interface charges in C/cm 84

Effect of interface charges, Q i (C/cm ) The interface charge Q i in the oide (assumed positive) will induce some negative charges (Q i /cm ) in the semiconductor. The effect is as though we have applied a positive gate voltage to the gate, and the negative charges in the semiconductor causes band bending. To get flat-band condition, we have to apply a negative voltage to the gate. Voltage to be applied to the gate to get flat-band condition Q C i o where C o o o Q i is usually positive (but can be both positive or negative in general). 85

Effects of work function difference and interface charges If we consider the effects of work function difference and the interface charges, the silicon band diagram may not be flat even when no voltage is applied to the gate. Hence, a correction has to be applied to the threshold voltage calculations carried out earlier assuming ideal MOS conditions. V FB 1 q ms Q C i o = voltage to be applied to the gate to get flat band condition. V T V FB V ' T where V T is the threshold voltage assuming ideal conditions (using equation 17.1 in tet). 86

Effects of MS and Q i on C G -V G characteristics of MOScapacitor C G C G V FB V FB actual ideal ideal actual p-type V G n-type V G A horizontal shift in C-V curve is observed. Routinely used to characterize MOS-C during IC fabrication. 87

Enhancement and depletion mode MOSFETs Device is off when V G = 0 enhancement-mode MOSFET Device is on when V G = 0 depletion-mode MOSFET 88

Threshold adjustment using ion implantation S Boron (+) ions Phosphorous () ions G B-ion D V T Q C ion o qb C qp C dose o dose o N + p-type Si N + = positive shift for acceptor implantation = negative shift for donor implantation B dose = # of boron ions/cm ; P dose = # of phosphorus ions/cm 89

Eample 6 Consider an NMOS with oide thickness of 0.1 m. The threshold voltage measured to be 0.5 V. Calculate the boron or phosphorous ions to be implanted to make V T equal to V. V T = +1.5 V a positive shift. So use boron ions C o 14 3. 98. 8510 F/cm 8 3 4510 4. 0. 110 cm F/cm q B V ions T Calculate B ions. (3. 10 11 ions/cm ) Co During IC fabrication, ion-implantation is routinely used to tailor the the threshold voltage MOSFET device. 90