EE 505 Lecture 10. Statistical Circuit Modeling

Similar documents
EE 505 Lecture 10. Statistical Circuit Modeling

EE 505 Lecture 11. Statistical Circuit Modeling. R-string Example Offset Voltages

EE 505 Lecture 8. Clock Jitter Statistical Circuit Modeling

EE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET

EE 435. Lecture 22. Offset Voltages Common Mode Feedback

EE 330 Lecture 25. Small Signal Modeling

EE 435. Lecture 22. Offset Voltages

EE 508 Lecture 13. Statistical Characterization of Filter Characteristics

EE105 - Fall 2006 Microelectronic Devices and Circuits. Some Administrative Issues

EE 435. Lecture 38. DAC Design Current Steering DACs Charge Redistribution DACs ADC Design

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

EE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors

EE 435. Lecture 36. Quantization Noise ENOB Absolute and Relative Accuracy DAC Design. The String DAC

EE 434 Lecture 33. Logic Design

EE 505. Lecture 11. Offset Voltages DAC Design

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:

EE105 - Fall 2006 Microelectronic Devices and Circuits

ECE 342 Electronic Circuits. 3. MOS Transistors

D/A Converters. D/A Examples

MOS Transistor Theory

EE 330 Lecture 31. Current Source Biasing Current Sources and Mirrors

ECE 546 Lecture 10 MOS Transistors

Lecture 12: MOSFET Devices

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR

EE105 - Fall 2005 Microelectronic Devices and Circuits

EE 330 Lecture 22. Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits

EE 330 Lecture 17. MOSFET Modeling CMOS Process Flow

EE 435. Lecture 2: Basic Op Amp Design. - Single Stage Low Gain Op Amps

Random Offset in CMOS IC Design

EE 434 Lecture 34. Logic Design

EE 330 Lecture 16. MOSFET Modeling CMOS Process Flow

Practice 3: Semiconductors

EE 330 Lecture 16. MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow

EE 330 Lecture 37. Digital Circuits. Other Logic Families. Propagation Delay basic characterization Device Sizing (Inverter and multiple-input gates)

EE 435. Lecture 37. Parasitic Capacitances in MOS Devices. String DAC Parasitic Capacitances

Lecture 4: CMOS Transistor Theory

EE 330 Lecture 16. MOSFET Modeling CMOS Process Flow

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

EEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EE 330 Lecture 36. Digital Circuits. Transfer Characteristics of the Inverter Pair One device sizing strategy Multiple-input gates

Studio 3 Review MOSFET as current source Small V DS : Resistor (value controlled by V GS ) Large V DS : Current source (value controlled by V GS )

EE 505 Lecture 7. Spectral Performance of Data Converters - Time Quantization - Amplitude Quantization Clock Jitter Statistical Circuit Modeling

EE247 Lecture 16. Serial Charge Redistribution DAC

EE 330 Lecture 15. Devices in Semiconductor Processes. Diodes Capacitors MOSFETs

Lecture 10, ATIK. Data converters 3

Nyquist-Rate D/A Converters. D/A Converter Basics.

EECS240 Spring Lecture 21: Matching. Elad Alon Dept. of EECS. V i+ V i-

The K-Input Floating-Gate MOS (FGMOS) Transistor

PARALLEL DIGITAL-ANALOG CONVERTERS

MOS Transistor Theory

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1

Lecture 4 Propagation of errors

MOS Transistor I-V Characteristics and Parasitics

P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions

The Gradual Channel Approximation for the MOSFET:

University of Toronto. Final Exam

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models

VLSI Design and Simulation

EE 330 Lecture 3. Basic Concepts. Feature Sizes, Manufacturing Costs, and Yield

Figure 1: MOSFET symbols.

Analysis and Design of Analog Integrated Circuits Lecture 14. Noise Spectral Analysis for Circuit Elements

The Mismatch Behavior P(x,y)

EE5780 Advanced VLSI CAD

1 Introduction. 2 Measure theoretic definitions

DC and Transient Responses (i.e. delay) (some comments on power too!)

EE 505 Lecture 9. Statistical Circuit Modeling

EE 330 Lecture 3. Basic Concepts. Feature Sizes, Manufacturing Costs, and Yield

MOSFET Physics: The Long Channel Approximation

!P x. !E x. Bad Things Happen to Good Signals Spring 2011 Lecture #6. Signal-to-Noise Ratio (SNR) Definition of Mean, Power, Energy ( ) 2.

Lecture 5: DC & Transient Response

Lecture 12 CMOS Delay & Transient Response

EE 330 Lecture 18. Small-signal Model (very preliminary) Bulk CMOS Process Flow

University of Toronto. Final Exam

ECE-305: Spring 2016 MOSFET IV

Using MOS Models. C.K. Ken Yang UCLA Courtesy of MAH EE 215B

Chapter 5 continued. Chapter 5 sections

Chapter 4 Field-Effect Transistors

Circuits. L2: MOS Models-2 (1 st Aug. 2013) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number

Scaling Issues in Planar FET: Dual Gate FET and FinFETs

ELEN0037 Microelectronic IC Design. Prof. Dr. Michael Kraft

EE105 Fall 2015 Microelectronic Devices and Circuits Frequency Response. Prof. Ming C. Wu 511 Sutardja Dai Hall (SDH)

Chapter 6: Field-Effect Transistors

Circuits. L5: Fabrication and Layout -2 ( ) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number

ECE315 / ECE515 Lecture-2 Date:

Lecture Notes 1 Probability and Random Variables. Conditional Probability and Independence. Functions of a Random Variable

1. Review of Circuit Theory Concepts

Lecture 5: DC & Transient Response

Introduction to Probability and Statistics (Continued)

Lecture Notes 1 Probability and Random Variables. Conditional Probability and Independence. Functions of a Random Variable

MOSFET Capacitance Model

Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model

EE 330 Lecture 14. Devices in Semiconductor Processes. Diodes Capacitors MOSFETs

ELEN 610 Data Converters

HW Solution 12 Due: Dec 2, 9:19 AM

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson

A Probability Review

Data Analysis, Standard Error, and Confidence Limits E80 Spring 2015 Notes

EE 508 Lecture 16. Filter Transformations. Lowpass to Bandpass Lowpass to Highpass Lowpass to Band-reject

Transcription:

EE 505 Lecture 10 Statistical Circuit Modeling

mplifier Gain ccuracy eview from previous lecture: - +

eview from previous lecture: String DC Statistical Performance 1 1 k k k ILk j 1 j 1 k 1 OM j1 1 1 jk1 Since the resistors are identically distributed and the coefficients are not a function of the index i, it follows that 1 k k k 1 1 k 1 j1 1 jk1 1 OM ILk Since the index in the sum does not appear in the arguments, this simplifies to ILk 1k k 1 k 1 1 OM ote there is a nice closed-form expression for the IL k for a string DC!!

eview from previous lecture: String DC Statistical Performance IL k assumes a maximum variance at mid-code ILk max OM

String DC Statistical Performance How about statistics for the IL? eview from previous lecture: IL is not zero-mean and not Gaussian and closed form solutions do not exist

eview from previous lecture: Current Steering DC Statistical Characterization Unary weighted FF I0=0 I1 I I-1 s for the string DC, the maximum IL k occurs near mid-code at about k=/ thus XI n Binary to Thermometer Decoder S0 S1 S S-1 OUT IL kmx I I OM I j=i +Ij nd, as for the string DC, the IL is an order statistic and thus a closed-form solution does not exist

eview from previous lecture: Current Steering DC Statistical Characterization Binary Weighted IL b=<1000..0> 1 1 IGk 1 1 I LSBX FF XI n I1 S1 I S I3 S3 In Sn OUT ILMX ILb=<1,0,...0> I I G LSBX ote this is the same result as obtained for the unary DC But closed form expressions do not exist for the IL of this DC since the IL is an order statistic

Statistical Modeling of Current Sources I D I X GS Simple Square-Law MOSFET Model Usually dequate for static Statistical Modeling ssumption: Layout used to marginalize gradient effects, contact resistance and drain/source resistance neglected μc W I = - L OX D GS TH andom ariables: {µ, C OX, TH, W, L } From previous analysis, need: I I D D Thus I D is a random variable

Statistical Modeling of Current Sources μc W I = - L OX D GS TH I X GS I D andom ariables: {µ, C OX, TH, W, L } Thus I D is a random variable Will assume {µ, C OX, TH, W, L } are uncorrelated This is not true : T OX is a random variable that affects both TH and C OX This assumption is widely used and popularized by Pelgrom It is also implicit in the statistical model available in simulators such as SPECTE Statistical information about T OX often not available Drenen and Mcndrew (XP) published several papers that point out limitations Would be better to model physical parameters rather than model parameters but more complicated Statistical analysis tools at XP probably have this right but not widely available ssumption simplifies analysis considerably Error from neglecting correlation is usually quite small but don t know how small

Statistical Modeling of Current Sources Model parameters are position dependent μc W I = - L OX D GS TH W D µ(x,y), C OX (x,y), TH (x,y) L (x,y) S

Statistical Modeling of Current Sources Model parameters are position dependent μc W I = - L OX D GS TH ssume that model parameters can be modeled as a position-weighted integral C OX TH OX TH easonably good assumption if current density is constant x,y dxdy C x,y dxdy x,y dxdy L W (x,y) D S

Statistical Modeling of Current Sources ssume that model parameters can be modeled as a position-weighted integral s seen for resistors, this model is not good if current density is not constant D C W I L OX D GS TH1 L W TH1 ε W TH THEQ x,y dxdy TH TH1 TH If TH1 =1, TH = W X THEQ =1.5 S ote dramatically different current densities But reasonably good assumption if current density is constant

Statistical Modeling of Current Sources μcoxw I D= GS -TH L Model parameters characterized by following equations μ = μ μ = C = C TH TH TH OX OX OX L L L W W W C eglecting random part of W and L which are usually less important C μ μ COX OX W I D= GS -TH - L TH

Statistical Modeling of Current Sources C μ μ COX OX W I D= GS -TH - L This appears to be a highly nonlinear function of random variables!! Will now linearize the relationship between I D and the random variables Since the random variables are small, we can do a Taylor s series expansion and truncate after first-order terms to obtain μ C W C W μw μ C W I - + - + L L L L μ C - - OX OX OX D GS TH GS TH OX GS TH TH GS TH TH This is a linearization of I D in the random variables µ, C OX, and TH COX W μw μcox W I D μ GS - TH + OX GS -T H TH GS - L L L C C W μ W μ C W - - - OX OX I GS TH GS TH GS D μ L + L L COX TH ID ID ID ID Could easily include L and W but usually not important unless lots of perimeter TH TH

Statistical Modeling of Current Sources C W μ W μ C W - - - OX OX I GS TH GS TH GS D μ L + L L COX TH ID ID ID ID μ C W I = - L OX D GS TH COX W μw μcox W I GS -TH GS -TH GS -TH D μ L L L + COX TH I μ COXW μ COXW μ COXW D GS -TH I GS -TH GS -TH L L L TH Thus ID μ COX TH + I μ C - D OX GS TH 4 TH ID μ C I μ C GS TH D OX TH OX TH or I D μ C I μ C GS TH D OX TH OX

Statistical Modeling of Current Sources 4 TH ID μ C I μ C GS TH D OX TH OX TH or I D μ C I μ C GS TH D OX TH OX It will be assumed that μ μ C C OX OX T 0 TH WL Cox WL WL where µ, Cox, T0 are Pelgrom process parameters 1 4 ID Cox T 0 I WL EB D Define Cox Thus 1 4 ID T 0 I WL EB D Often only β is available

Statistical Modeling of Current Sources 1 4 ID T 0 I WL EB D Gate area: =WL Standard deviation decreases with Large EB reduces standard deviation Operating near cutoff results in large mismatch Often threshold voltage variations dominate mismatch ID T 0 I EB WL D

Statistical Modeling of Circuits The previous statistical analysis was somewhat tedious Will try to formalize the process ssume Y is a function of n random variables x 1, x n where the mean and variance of x i are small Y = f x, x,... x 1 n n f Y = f X + x + x x x X 0 x,,... j1 j X 0 x x X =... x 1 n j 1 n where x, x,... x 1 n small

Statistical Modeling of Circuits n f f X x X 0 x Y = + X 0 j1 j1 j n Y f X 1 f = + Y Y Y x Y X 0 X j 0 n 1 f = Y x j1 Y xj Sˆ f xj = 1 Y f x j X = ˆ S Y Y n j1 f xj x j 0 X j 0 j x j

Statistical Modeling of Circuits lternatively, if we define S f x j = x Y i f x j X 0 f S x j is the more standard sensitivity function we thus obtain n = f S Y xj x Y j1 x j i

Claim: μ where µ is the Pelgrom matching parameter and is the gate area rgument: ssume, μ eq x y dxdy Let S k be a square of area k in the channel μ eq i1 ki x, y dxdy y D k S Channel x where the channel has been partitioned into disjoint regions each of area ki For convenience, assume ki = kj = k for all i,j

Theorem: If the random part of two uncorrelated current sources I 1 and I are identically distributed with normalized variance, then the random I I variable ΔI=I -I 1 has a variance given by the equation I I I I Proof: I I I 1 I I I I I I 1 I I I I I I I I I I I I 1 1 I I I I I I I I

Theorem: f(y) and F(y) are any pdf/cdf pair and if X~ U[0,1], then y F x has a pdf of f(y). 1 Corollary: If X~ U[0,1] and then y=f -1 (x) is [0,1] x 1 h F h e dx CDF showing random variable mapping of x 1 from U(0,1) 1 F x 1 x F -1 (x 1 )

Theorem: If y~[0,1], then z = σy+µ is [µ,σ]

Some useful relationships: erf x = x π -t e dt 0 The CDF of the (0,1) random variable x is given by 1 x F x = 1+erf Excel @OM.DIST @OM.S.DIST @OM.I @OM.S.I Older Excel @OMI @OMSI @OMDIST @OMI x f x f 1 x 1 x x F F F F x where f: PDF F:CDF

Example: Determine the area required for the resistors for an n-bit -string DC to achieve a yield of P if the device is marketable provided 1 IL kmx LSB ssume the area of each resistor is WL OM WL

Since P is fixed, can solve for X

P F X 1 where F (X ) is the CDF on (0,1) 1 P 1 X F X 1 x 1 WL X 1 X WL WL X 1 P 1 WL F

1 P 1 WL F WL X Total area n n n n 3n TOT WL X X X 3 n TOT X or equivalently 3n 1 P 1 TOT F

End of Lecture 10